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TKTTKT--1426 Digital design for 1426 Digital design for FPGA, 6cpFPGA, 6cpFall 2011Fall 2011http://www.tkt.cs.tut.fi/kurssit/1426/
Tampere University of TechnologyTampere University of TechnologyDepartment of Computer SystemsDepartment of Computer SystemsWaqar HussainWaqar Hussain
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Lecture ContentsLecture Contents
Lecture 1:• Introduction• Course arrangements• Recap of basic digital design concepts• EDA tool demonstration
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Course GoalsCourse Goals• Teach digital design for FPGAs
EDA tools, Altera DE2 FPGA platformHands-on work
• Bring the knowledge level and skill set up to par with finnish students
’Need-to-know’ approach• Prepare for studying more advanced courses• Prepare for M.Sc. Thesis work
FPGA design skills often needed in the department’s projects, and within industrial companies
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International StudiesInternational Studies
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Course ContentCourse Content• Computer-aided digital circuit design using EDA tools
Design software: Mentor Graphics' HDL Designer• Design fundamentals: Synchronous, hierarchical, and modular
designInterfaces, design re-use
• Modeling digital systems using different design entry methods: schematic capture, truth tables, and state diagrams
• Design verification: Test benches, simulationSimulation software: Mentor Graphics' ModelSim
o Delay simulation• Design implementation: Logic synthesis, place & route, FPGA
implementationFPGAs: structure and propertiesEDA tools: Altera Quartus, Mentor Graphics' LeonardoSpectrum
o Power, speed, and area optimization and analysis• Hardware description language (VHDL)
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General InfoGeneral Info• Prerequisites
Basics of digital circuitsRecommendable: Basic knowledge about digital design and microprocessors
• RequirementsAttendance to all lectures is COMPULSORY. In case you miss any lecture, you need to appear for the oral examination for that lecture. For that, you need to set an appointment for the oral examination with the lecturer by email.Final Examination (carries 50% of final grade)Compulsory computer exercises (carries 50% of final grade)
• Grading0-5, based on the exam and exercise project
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PlagiarismPlagiarism• Plagiarism
Copying of computer exercises from other group member, cheating in examination will result in serious consequences.
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PersonnelPersonnel• Lectures
Waqar Hussaino Room TG313o Email: [email protected]
Lecture notes will be available on POP• Exercises
Lasse Lehtonen, Temmu Pitkaneno Email: [email protected]
All exercise information will be on POPSend your exercises at [email protected]
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Course ScheduleCourse Schedule• Lectures
Period 1, 2: o See POP for the exact schedule and the room number
• ExercisesPeriods 1, 2
o See POP for the exact schedule and the laboratory number
• Web: http://www.tkt.cs.tut.fi/kurssit/1426/Announcements about possible changes will be also emailed to the registered students
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Course MaterialCourse Material
• Everything available on the course web pages
• Lecture notesNo text book
• Exercise materialEDA tool tutorials
• Additional materialVHDL guides, tutorials, coding rules etc.Extra slide sets (if needed)
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Exercises in PracticeExercises in Practice• Project work: calculator
Done alone or in groups of two/threeConstructed piece by piece during the weekly exercisesEach task must be completed and acceptedFinal assembly and testing on the last exerciseFPGA prototyping on the Altera DE2 platform
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Exercises in PracticeExercises in Practice• Two weekly exercise sessions
in TC417
• Person hours for each exercise must be reported
• Possible to do the exercises on your own PC
Instructions given on the course web pages
• Return deadline for each exercise is listed on the course web pages
• Exercise return by emailEmail address given on the exercise web page
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Altera DE2 FPGA PlatformAltera DE2 FPGA Platform• Development board
Includes an FPGA and lots of peripherals
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Altera DE2 FPGA PlatformAltera DE2 FPGA Platform
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Digital Design OverviewDigital Design Overview• Combinational system design• Design views
Functionality, Architecture, Implementation• Abstraction levels and hierarchy• Digital design flow & automation
Specification, Design, Verification, Implementation
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Digital Systems ClassificationDigital Systems Classification• Two main categories
Combinational (old name: combinatorial)Sequential
• Combinational systemNo memoryOutput determined only by the current inputsAny system can be designed with two levels of logic
• Sequential systemContains memoryOutput is determined by the inputs AND the current state
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Combinational System SpecificationCombinational System Specification• Specification defines at the highest level:
1. Set of values for the input: input set2. Set of values for the output: output set 3. Specification of the input-output function
• This information is always presented independent of the level of abstraction
• Input/output set definition must also include the data types
Example:o Inputs A, B: 8-bit unsigned integero Output Y: 16-bit unsigned integerEDA tools allow high-level data types such as floating-point numbers and enumerated typeso Eventually, however, everything will be represented with
only ones and zeros
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Design Example: HalfDesign Example: Half--AdderAdder• Specification
Inputs A, B: 1-bit unsigned integerOutput Y: 2-bit unsigned integerFunction: Y = A + B (arithmetic addition, not OR!)
• Truth table: Karnaugh maps:Y1 Y0
= =
• Boolean equations: Y1 = ABY0 = A’B + AB’ = A xor B
A B Y0 0 000 1 011 0 011 1 10
A B Y1 Y0
0 0 0 00 1 0 11 0 0 11 1 1 0 1
A01
0 1B
11
A01
0 1B
A B Y0 0 00 1 11 0 11 1 2
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Design Example: HalfDesign Example: Half--AdderAdder• Boolean equations: Y1 = AB
Y0 = A’B + AB’ = A xor B• Gate mapping:
=
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Combinational System DesignCombinational System Design• Any digital system can be designed using
this approach!1. Truth table
Relationship between the inputs and outputsSequential systems must include the current stateamong the input column, and the next state among the output columns
2. Karnaugh map for each output bit (and for each next state bit on sequential systems)
Select as large areas from the map as possible3. Form Boolean equations from the Karnaugh
mapsOptimize the equations, if possible
4. Transform the equations into logic gates
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Basic Gates RecapBasic Gates Recap
InverterANDORNANDNORXORNXOR
z = x’
x1x0z =
z = x1x0( )’
x1 x0z = +
z = x1 x0+( )’
z = +x1x0’ x1x0’1 0
z = +x1x0’ x1x0’= x x+
x
x1x0
x1x0
x1x0
x1x0
x1x0
x1x0
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Example: HDLExample: HDL• Graphical representation (logic gates):
• Hardware description language:A3 <= x3 AND x2;B4 <= x2 AND x1 AND x0;Z <= A3 OR B4;...or alternatively:Z <= (x3 AND x2) OR (x2 AND x1 AND x0);
Intermediate signals do not have to be used, but tometimes they help to clarify the design
x3
x2x1x0
zA
BC
1
2123
3
4
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Digital Design ViewsDigital Design Views
Architecture
Implementation
Functionality
• What should be done?• What is the behavior?
• What are the physical components?
• What kind are they?
• What are the logical building blocks?
• How are they organized?
Behavior
Physical
Structure
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Characteristics (example)Characteristics (example)
y = a+by(t+1) = x(t-1)+y(t)
Clock frequencyDelay
Power consumptionSize
Number of AND-gatesClock cycles
Architecture
Implementation
Functionality
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What is an ImplementationWhat is an Implementation• Realization of the desired functionality on the
available architecture• Direct mapping, one-to-one
Architecture is designed to realize the functionalityEach functional operation has corresponding realization in architectureArchitecture cannot realize any other functionalityExample: digital watch
• Indirect mappingArchitecture can realize also other functionalitiesThere is no exactly corresponding physical component for each functional operation
o Shared resources, re-used with respect to timeUltimate example: general-purpose processor
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Example:Example:Custom VLSI Chip ImplementationCustom VLSI Chip Implementation
• Functionality is the same as the architecture• Direct mapping, the smallest unit is gate (transistor)• Implementation = connecting building blocks together!
( )z ab cFunctionality:
Architecture:
Implementation:ASIC
Library of basiccomponents(all gate typesavailable)
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Example:Example:Discrete Logic Chip ImplementationDiscrete Logic Chip Implementation
• The smallest unit is chip
( )z ab cFunctionality:
Architecture:
Implementation:74-series discretelogic
z
ab
c
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Example:Example:FPGA ImplementationFPGA Implementation
• Indirect mapping, the smallest unit is Look-up Table (can perform all basic logic functions)
( )z ab cFunctionality:
Architecture:
Implementation:FPGA
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Design Views Design Views -- ProblemsProblems• SW engineer
Designs only functionalityExperience needed to fulfill e.g. performance requirementsCannot affect the architecture
• Electronics engineerDesigns architectureFunctionality = ArchitectureCannot understand separation of the two
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Design Views Design Views -- ProblemsProblems• Basic digital design courses
Exercises must be simple”Design” often means only architecture design
( )z ab cFunctionality Architecture
Specification(functional specification)
”Design” - often still same as functional specification in a graphical notation!
=
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Abstraction LevelsAbstraction Levels
Processors, memories
Registers
Gates
Transistors
AlgorithmsRegister transfer
Boolean expressionsDiff. equations
Transistor layout
Cells
ChipsBoards
Architecture
Implementation
Functionality
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Abstraction Levels in Design FlowAbstraction Levels in Design Flow• High abstraction level
Suitable to coarse planning of what is desiredTypically in the beginning of the design flow
• The lower the level, the more detailed the information
…and the more effort required if something is changed
• Abstraction levels and design hierarchy can be considered at the same time
• On this course, the abstraction level is lowRegister and gate-level
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Hierarchy in Digital DesignHierarchy in Digital Design
• Large designs must be partitioned into blocks to be manageable
• Compare: SW functions
Nobody writes only mainfunction?
• Example:
RX RY
ADD
Input
Output
Clock
Logical (gate andflip-flop) level
Physical (transistor)level
Transistor
Module level
Gates
Clock Flip-Flop
+5V
Registers
xin
xreg yreg
addout
Adder
clk
z
X(i)
Z
(a )
(b)
(c)
Z(i) = X(i-1) + Y(i-1)
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Design Flow & HierarchyDesign Flow & HierarchyTop-down design Bottom-up design
System
Modules
Gates andflip-flops
Transistors Bottom level
Top level
B
A DCDC
B
A
Hie
rarc
hy le
vel
Ord
er o
f des
ign
1.
2.
N. 1.
2.
N.
…
…
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Design PhasesDesign Phases1. Specification
Specify input/outputs and their protocols as well as functionality
2. DesignRefine the specificaiton, create simulation and implementation models
3. VerificationEnsure that models meet the specification
4. ImplementationSynthesize the design into target technology and execute on prototype
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Different Tools for Different PhasesDifferent Tools for Different Phases
1. SPECIFICATION, DOCUMENTATIONVarious tools and text-based formats for expressing the design behaviorOn this course, the specification is always given
2. DESIGN: HDL Designer (Mentor Graphics)A complete design creation environmentMakes it possible to instantiate different kind of design files in one top-level designMany description styles, good for educationProvides link to simulation and implementationo Push-button simulation, synthesis, and P&R
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Different Tools for Different PhasesDifferent Tools for Different Phases
3. VERIFICATION: ModelSim (Mentor Graphics)Simulator for digital designsWidely used in the industryVisualizes the behavior via, e.g. wave forms Can communicate with HDL Designero Interactive simulation and debugging
4. IMPLEMENTION: Quartus (Altera)Quartus implementation flow tasks1. Synthesize a netlist from the Hardware Description
Language source files (from HDL designer) 2. Map and fit the logic elements into the FPGA chip3. Program the FPGA device
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2. HDL Designer2. HDL Designer• A design environment allowing a broad range
of design styles:Block and gate diagrams (schematic)State diagramsTruth tablesHardware description languages (eg. VHDL)
• Generates standard VHDL code from the user’s block and state diagrams
VHDL allows the simulation and synthesis
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2. HDL Designer 2. HDL Designer –– Design StylesDesign Styles
1. RTL block diagram
2. state diagram, truth table
4. hand-written VHDL
3. top-level structural block diagram
as is
standard VHDL for other tools
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2. HDL Designer Design Flow2. HDL Designer Design Flow
HDL Designer
Auto-generatedVHDL
.sof programming file
FPGA chip
Simulation results
ASIC chip
.GDSII
.edif
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2. HDL Designer Main View2. HDL Designer Main View
• asdtest
User logic
Menubar
Toolbar
View selection
List of objectsProject info
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Hierarchical DesignHierarchical Design• Hierarchical design and component re-use are
extremely powerful methods • Same block can be instantiated multiple
times• Blocks can contain
sub-blocks
1202_s08
action buttons
library
details of selected blcok
Blocks defined top-down,
components bottom-up,
otherwise equal
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Automated VerificationAutomated Verification• All designs should be automatically verified
Ensure that they meet the specification• Assistants provide most of the test benches on this
course
testi
test input
resultsuser’s block
testbench
OK?
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2. HDL Designer in Practice2. HDL Designer in Practice1. Create a new project and library for your design files2. Create design files in your library
Designs can be used as components simply by dragging and dropping them into the upper level designs re-use and duplication
3. Connect your design into a test bench that generates the inputs and checks the outputs
4. Run ModelSim to simulate the designCorrect any problems in your design and re-run ModelSim until the design passes the test bench
5. Run Quartus synthesization and place&route flows6. Program the FPGA chip with Quartus Programmer7. Verify design by using the FPGA board
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3. ModelSim3. ModelSim• Powerful event-based simulator for VHDL (and
Verilog)Can automatically use VHDL files generated by the HDL DesignerWidely used in the industryUsed in several TKT-courses also
• Simulates only logical behavior (results)Does not know hardware-related issues eg. delaysDelays are accurately known only after synthesis, placement, and routing
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3. ModelSim Main View3. ModelSim Main View
simulated design and its sub-bloks
signals and parameters of selected component
simulated waveform
(this space can shown other info as well)
command prompt and messages will appear into transcript window on the bottom
Manubar and toolbar
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3. ModelSim Features3. ModelSim Features• Draws a waveform diagram including
Inputs OutputsAny internal signal of any design unit
• Supports different kinds of data representation forms Binary, decimal numbers, ascii data, analog
• Allows, for example,Searching for events in the waveformGeneration of input signals and Manipulation of any signalAdding breakpoints to the VHDL code
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3. ModelSim 3. ModelSim -- WaveformWaveform
Monitored signals
Values at cursor Cursor line
Analog view of bus
multibit bus
high-freq signal
1-bit signal
Time axis
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3. ModelSim in Practice3. ModelSim in Practice• ModelSim works
as standalone simulatortogether with HDL Designer
• Starting ModelSim from HDL Designer:a) Start from the topmost level including a test
bencho Do not have a design block selected!
b) Can be started from any design unit as wello However, inputs have to be generated manuallyo Impractical
• Always use a testbench to verify designs thoroughly!
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4. Quartus4. Quartus• Accepts HDL description of a system (VHDL,
Verilog)• Quartus flow phases
1. Setup2. Perform RTL synthesis3. Map basic gates into FPGA logic4. Place the logic into specific location in chip5. Route (connect) the logic elements together6. Provide statistics and analysis results7. Create a programming file and upload it into the FPGA
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