Text of Computer Organisation and Architecture Teaching Trends
1. Trends and innovations in Computer organisation and Computer
Architecture courses Yogesh Singh FDP on Emerging Trends in
Computing Education
2. WHY DO WE STUDY COMPUTER ARCHITECTURE ? Intuition? Brain?
The relationship between hardware and software.
3. ACM CURRICULUM GUIDELINES FOR COMPUTER ORGANISATION
ARCHITECTURE COURSES Computing professionals should not regard the
computer as just a black box that executes programs by magic.
Students should acquire an understanding and appreciation of a
computer systems functional components, their characteristics,
performance, and interactions Students need to understand computer
architecture to develop programs that can achieve high performance
through a programmers awareness of parallelism and latency. The
learning outcomes specified for core topics of AC by ACM. 1.
Digital Logic and Digital Systems Design the basic building blocks
of a computer: arithmetic-logic unit (gate-level), registers
(gate-level), central processing unit (register transfer-level),
memory (register transfer-level). 2.Machine Level Representation of
Data Explain why everything is data, including instructions, in
computers. Explain the reasons for using alternative formats to
represent numerical data. 3. Assembly Level Machine Organisation
Describe how an instruction is executed in a classical von Neumann
machine, with extensions for threads, multiprocessor
synchronisation, and SIMD execution.
4. 4. Memory System Organisation and Architecture Identify the
main types of memory technology (e.g., SRAM, DRAM, Flash, magnetic
disk) and their relative cost and performance. Describe how the use
of memory hierarchy (cache, virtual memory) is used to reduce the
effective memory latency. 5. Interfacing and Communication Explain
how interrupts are used to implement I/O control and data
transfers. Identify various types of buses in a computer system. 6.
Functional Organisation Compare alternative implementation of
datapaths. Discuss the concept of control points and the generation
of control signals using hardwired or microprogrammed
implementations Design and implement a complete processor,
including datapath and control. 7. Multiprocessing and Alternative
Architectures Discuss the concept of parallel processing beyond the
classical von Neumann model Describe alternative parallel
architectures such as SIMD and MIMD 8. Performance Enhancements
Describe superscalar architectures and their advantages. Explain
the concept of branch prediction and its utility.
5. CS/ECE 552: Introduction to Computer Architecture,
University of Wisconsin Where does the course t in your curriculum?
This is taken by juniors, seniors, and beginning graduate students
in computer science and computer engineering. Prerequisites include
courses that cover assembly language and logic design. This course
is a (recommended) prerequisite for a graduate course on advanced
computer architecture. Approximately 60 students take the course
per offering; it is offered two times per year (once each
semester). Assessment Assessment is a combination of homework,
class project, and exams. There are typically six homework
assignments. The project is a detailed implementation of a 16-bit
computer for an example instruction set. The project requires both
an unpipelined as well as a pipelined implementation and typically
takes close to a hundred hours of work to complete successfully.
The project and homeworks are typically done by teams of 2
students. There is a midterm exam and a final exam, each of which
is typically 2 hours long. 20% Homework 25% Project 25% Midterm 25%
Final 5% Class participation Tools Mentor, ModelSim, WISC-SP08
Simulator-debugger, cacheSim, wsrun.pl Knowledge Area Total Hours
of Coverage Architecture and Organization (AR) 39
6. Knowledge Unit Topics Covered Introduction and Performance
Technology trends, Measuring CPU performance ,Amdahls law and
averaging performance metrics Instruction Sets Components of an
instruction set,Understanding instruction sets from an
implementation perspective,RISC and CISC and example instruction
sets Computer Arithmetic Ripple carry, carry lookahead, and other
adder designs,ALU and Shifters,Floating-point arithmetic and
floating-point hardware design Datapath and Control Single-cycle
and multi-cycle datapaths,Control of datapaths and implementing
control finite-state machines Pipelining Basic pipelined datapath
and control,Data dependences, data hazards, bypassing, code
scheduling.Branch hazards, delayed branches, branch prediction
Memory Hierarchies Caches (direct mapped, fully associative, set
associative) ,Main memories,Memory hierarchy performance metrics
and their use,Virtual memory, address translation, TLBs Input and
Output Common I/O device types and characteristics,Memory mapped
I/O, DMA, program-controlled I/O, polling, interrupts,Networks
Multiprocessors Introduction to multiprocessors ,Cache coherence
problem . Course textbooks and materials David A. Patterson and
John L. Hennessy, Computer Organization and Design: The Hardware
and Software Interface Morgan Kaufmann Publishers, What is covered
in the course?
7. CC152: Computer Architecture and Engineering, University of
California, Berkeley Where does the course t in your curriculum?
This is a senior-level course in the computer science curriculum
for computer engineering students interested in computer design.
Assessment Examinations, homeworks, and hands-on laboratory
exercises.The class will have two mid-terms and no final. The class
will have two long homework assignments. Labs: The centerpiece of
the class is a set of computer architecture lab assignments based
on RISC-V processors implemented in the Chisel hardware description
language. Three architecture simulation labs are the focus of the
class: Lab 1 (directed, open-ended) covers static pipelined CPUs.
Lab 2 covers the memory hierarchy. Lab 3 covers
dynamically-scheduled CPUs. The heart of each lab is the open-ended
section. This section lists a set of computer architecture project
topics that are a good fit to a 3-week work schedule. Students pick
one of the open-ended projects, and focus on doing the best job
possible during the allotted time period. Academic Honesty: Copying
all or part of another person's work, or using reference material
not specifically allowed, are forms of cheating and will not be
tolerated. A student involved in an incident of cheating will be
assigned an F grade or a 'zero' grade to the subject work Knowledge
Area Total Hours of Coverage Architecture and Organization (AR)
33
8. Knowledge Unit Topics Covered Digital Logic and Digital
Systems N/A Machine Level Representation of Data N/A Assembly Level
Machine Organization Historical Perspectives Memory System
Organization and Architecture Memory Hierarchy, Virtual Memory,
Snooping Caches Interfacing and Communication Synchronization,
Sequential Consistency Functional Organization Pipelining
Multprocessing and Alternative Architecture Superscalar, VLIW,
Vector Processing Performance Enhancements Complex Pipelining .
Additional topics Case Study: Intel Sandy Bridge & AMD
Bulldozer (1.5); Warehouse-Scale Computing (1.5) Course textbooks
and materials J. L. Hennessy and D. A. Patterson, Computer
Architecture: A Quantitative Approach, 5th Edition, Morgan Kaufmann
Publishing Co., Menlo Park, CA. 2012. What is covered in the
course?
9. 6.823 Computer System Architecture - Spring 2015,
Massachusetts Institute of Technology Overview This course is a
study of the evolution of computer architecture and the factors
inuencing the design of hardware and software elements of computer
systems. This is graduate level course. Assessment 75% of the grade
will be based on the four quizzes, equally weighted. The remaining
25% of the grade will be based on four laboratory exercises. The
last two labs have twice the weight of the first two.Tools
Laboratory Exercises There will be four Laboratory Exercises that
will explore the concepts taught in lecture using industrial
strength tools. Two to three weeks will be allotted for the
completion of each lab. Tool Pin - A Dynamic Binary Instrumentation
Tool Knowledge Area Total Hours of Coverage Architecture and
Organization (AR) 40
10. What is covered in the course? Introduction & History
of Calculation and Computer Architecture Inuence of Technology and
Software on Instruction Sets: Up to the dawn of IBM 360 Hardwired,
Single-cycle ISA Implementation Instruction Pipelining and Hazards
Instruction Pipelining: Hazard Resolution and Timing Constraints
Caches Memory Management from Absolute Addresses to Demand Paging
ModernVirtual Memory Systems Complex Pipelining Out-of-Order
Execution, Register Renaming and Exceptions Branch Prediction
Speculative Execution Advanced Memory Operations Multithreading
Architectures On-chip Networking (I) On-chip Networking (II) Cache
Coherence (I) Cache Coherence (II) Memory Consistency Models
Transactional Memory Microcoded and VLIW Processors Vector
Computers Graphics Processing Units Reliability Course Reading
Material: Computer Architecture:A Quantitative Approach: 5th
Edition by J. L. Hennessy and D.A. Patterson
11. CSL 211 - Computer Architecture, IIT Delhi Where does the
course t in your curriculum? The 'Computer Architecture' course is
intended to teach undergraduate students in Electrical Engineering
and Computer Science the basics of computer architectures. Credits
: 5 [3-1-2] (L-T-P) Assessment MINOR - I 10%, MINOR -II 15%, MAJOR
25%, ASSIGNMENTS 50% Tools Tejas Architecture Simulator, EmuArm
(GUI based ARM Emulator), NASM assembler, Logisim ACADEMIC
MISCONDUCT Academic misconduct such as cheating will not be
tolerated. The work you submit in this class is expected to be your
own. If you submit work that has in part or in whole been copied
from some published or unpublished source (including current or
former students), or that has been prepared by someone other than
you, or that in any way misrepresents somebody else's work as your
own, you will face severe disciplinary action. Any detected cases
of cheating will be pursued. Penalties can include: receiving a
zero on the assignment (the minimum penalty), failing the course,
having a note placed in your permanent academic record, suspension,
and ultimately expulsion. Knowledge Area Total Hours of Coverage
Architecture and Organization (AR) 42
12. Knowledge Unit Topics Covered Introduction to Computer
Architecture The Language of Instructions, Instruction Set Design,
Design of Practical Machines Instruction Sets The Language of Bits,
Floating-Point Numbers, The Basics of Assembly Language,
SimpleRisc,ARM Assembly Language, x86 Assembly Language Computer
Arithmetic Ripple carry, carry lookahead, and other adder
designs,ALU and Shifters,Floating-point arithmetic and
floating-point hardware design, Multiplication of Floating-Point
Numbers, Division of Floating-Point Numbers Processor Design
Single-cycle and multi-cycle datapaths,Control of datapaths
Pipelining Basic pipelined datapath and control,Data dependences,
data hazards, bypassing, code scheduling.Branch hazards, delayed
branches, branch prediction Memory System Caches (direct mapped,
fully associative, set associative) ,Main memories,Memory hierarchy
performance metrics and their use,Virtual memory, address
translation, TLBs Input and Output Common I/O device types and
characteristics,Memory mapped I/O, DMA, program-controlled I/O,
polling, interrupts,Networks, Case StudiesI/O Protocols, Storage
Multiprocessors Design Space of Multiprocessors, MIMD
Multiprocessors, SIMD Multiprocessors,Interconnection Networks Case
Study: ARM Processors, NVIDIA Tesla Architecture, Course textbook
David A. Patterson and John L. Hennessy, Computer Organization and
Design: The Hardware and Software Interface Morgan Kaufmann
Publishers, What is covered in the course?
13. OCE:Computer Architecture(Course sponsored by Aricent)
NPTEL, IIT Madras ABOUT THE COURSE The course provides a detailed
understanding of various processor microarchitectural designs,
which include in-order scalar pipeline design, out-of-order
superscalar processor design, and multicore processor design.
Pre-requisites: Digital Logic Design or Digital Circuits and
Systems, Computer Organization CERTIFICATE Certificate will be
given to those who register and write the exam. Certificate will
have your name, photograph and the score in the final exam. It will
also have the logos of NPTEL and IIT Madras. It will also be
e-verifiable on the nptel.ac.in/noc website.The exam is optional.
Exams will be on 6 September 2015 and 13 September, 2015. Time:
1pm-4pm.The list of cities where the exam will be conducted will be
available in the registration form. SYLLABUS OUTLINE Week 1:
Introduction, Instruction Set Principles Week 2: Memory Hierarchy
Design Cache Memory Hierarchy Week 3: Memory Hierarchy Design Main
Memory Design Week 4: Fundamentals of Pipelining Week 5:
Instruction Level Parallelism Week 6: Out-of-Order Execution Week
7: Thread-Level Parallelism Multi-core Processors Week 8:
Thread-Level Parallelism Cache Coherency Problem, Synchronization,
and Memory Consistency Knowledge Area Total Hours of Coverage
Computer Architecture 20
14. VIRTUAL LABS An Initiative of Ministry of Human Resource
Development (MHRD) Under the National Mission on Education through
ICT http://vlab.co.in/index.php
15. This paper tells about principles and goals of the
curriculum, teaching philosophy and methods, improvements of
contents. COA course contents lie on the intersection of hardware
and software and tightly links to the operating system,
compiler/assembler, and programming, the design of hardware system
can affect programming strategy and execution efciency of programs.
Principles for designing the curriculum (1). The curriculum must
periodically update and adjust its topics and contents (2).
Hardware is tightly linked with software concepts and knowledge -
so understand hardware from the perspective of programmers. (3).
The course experiments should lead students make use of what they
have learned. - course experiments should be helpful for students
to develop their computer skills, (4). Include professional skills
as an integral part of the curriculum. -Introduce concrete examples
: American Patriot Missile failure to intercept an incoming Iraqi
Scud missile Intel Pentium Process Floating-Point Number Bug
ChunfengYuan;Yihua Huang; Zhesheng Zhang; Guihai Chen;Wanchun Dou,
"Improvements on Teaching Methods and Contents for the "Computer
Organization and Architecture" Curriculum," Scalable Computing and
Communications; Eighth International Conference on Embedded
Computing, 2009. SCALCOM-EMBEDDEDCOM'09. International Conference
on , vol., no., pp.560,565, 25-27 Sept. 2009 Improvements on
Teaching Methods and Contents for the "Computer Organization and
Architecture"
16. The curriculum refers to not only the hardware and the
Instruction Set Architecture design but also software design for
operating systems, compilers and programming. eg how oat no is
stored in hardware Begin from the programming perspective; stress
the relationship between hardware and software; place emphasis on
CPU design; and aim to enhance system performance (1). Based on
approach, high-level programming language-> assembly language
->machine code-> instructions CPU design, (2). In regard to
CPU design contents, design of the pipelined CPU and other advanced
technology. Based on a progressive order the IAS machines CPU
->bus-driven CPU ->single- cycle CPU ->multi-cycle CPU
->basic pipelined CPU-> advanced pipelined CPU, using MIPS
and Pentium 4 processors as blueprint, 3. interaction between
hardware and software, exception and interruption, memory access,
and I/O access into the execution process of instructions. 4.
Incorporating the pipelining of a CPU, we explain how to optimize
compilers. Experiments and Results Authors emphasize on designing a
pipelined CPU based on the strategy: begin with ISA simulator, then
functional components design, then designing a single-cycle CPU,
and nally pipelined CPU design. Altera DE2 experiment toolkits that
allow students to use hardware description language and FPGA to
conduct their CPU design experiments. The results have shown that
the majority of students can complete their CPU design projects
either a single-cycle CPU or a multi-cycle CPU, and some of them
can accomplish their design for a 5-segment pipelined CPU. Teaching
method and course content improvement
17. Nikolic, B.; Radivojevic, Z.; Djordjevic, J.;
Milutinovic,V., "A Survey and Evaluation of Simulators Suitable for
Teaching Courses in Computer Architecture and Organization,"
Education, IEEE Transactions on , vol.52, no.4, pp.449,458, Nov.
2009 This paper attempts to give a survey of simulators suitable
for teaching courses in computer architecture and
organization.
18. Generally, these simulators can be separated into two major
groups The rst group contains the appropriate tools and necessary
methods to enable the user rst to build specic computer system
congurations and then to simulate them. This type of simulator
implies ve-step procedure in which a user: 1. selects components
from the library; 2. places selected components onto the working
panel; 3. connects the selected component with other ones in order
to create a new component; 4. creates an interface for the created
new component; and 5. tests the created component. The most
representative simulators from this group are: HASE, ISE Design
Suite, JHDL, Logisim, M5, Quartus II, Simics, SMOK, and Virtual
Vulcan. The second group of simulators contains appropriate tools
that enable the user to simulate already created systems. This type
of simulator implies the ve step procedure in which a user: 1.
initializes the simulator with default options; 2. species the test
conguration; 3. creates test vectors and diagrams to be observed;
4. carries out the simulation; and 5. analyzes test results for the
specied test conguration. The most representative simulators from
this group used in the evaluation are: ANT, CASLE, CCSTUDIO,
CodeWar- rior, CPU Sim, DigLC2, DLXview, Easy CPU, EDCOMP, ESCAPE,
FastCache, HASE-Dinero, JCachesim, RM, RSIM, SIMCA, SimFlex, SimOS,
and SimpleScalar.
19. Conclusion The evaluation, based on the topics coverage
criteria, shows that there is no single simulator which covers all
topics. The best overall topics coverage is achieved with
simulators M5 (69.57%) and Simics (64.13%), while most of other
simulators achieve about 30.00% coverage. The evaluation, based on
the simulation features criteria, shows that there are many
simulators which meet a great number of these criteria. Simulators
EDCOMP, HASE, ISE Design Suite, JHDL, M5, and Quartus II meet most
of the criteria.
20. The paper presents the approach followed at the Faculty of
Engineering of the University of Porto, to introduce design
automation tools and structured design techniques in the rst course
on digital system design of our Integrated Master in Electrical and
Computer Engineering. Paper approach the use of Electronic Design
Automation tools with a recongurable platform based on a Xilinx
FPGA LABORATORY EXPERIMENTS In the rst laboratory assignment
students build a basic digital circuit with gate-level logic
devices The second block of laboratory experiments leads the
students from the gate-level design of an adder/subtractor to the
construction of an elementary microprocessor. It includes a
sequence of four lab assignments, leading to the construction of a
simple, albeit fully functional, 8-bit RISC-style microprocessor.
The third and nal block of labs deals with the MIPS assembly
programming FPGA board and development tools The sequence of
laboratory assignments leading to the development of the
microprocessor, makes use of a low cost development board with
recongurable logic: the Spartan-3 Starter Kit . After designing the
circuit with the ISE WebPACK Design Software from Xilinx, the
students program the FPGA and validate the expected results. Silva
Matos, J.;Alves, J.C.; Sousa Mendonca, H.;Araujo,A.J., "From
Boolean algebra to processor architecture and assembly programming
in one semester," Design of Circuits and Integrated Circuits
(DCIS), 2014 Conference on , vol., no., pp.1,5, 26-28 Nov. 2014
From Boolean algebra to processor architecture and assembly
programming in one semester