Computer Organisation and Architecture Teaching Trends

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  1. 1. Trends and innovations in Computer organisation and Computer Architecture courses Yogesh Singh FDP on Emerging Trends in Computing Education
  2. 2. WHY DO WE STUDY COMPUTER ARCHITECTURE ? Intuition? Brain? The relationship between hardware and software.
  3. 3. ACM CURRICULUM GUIDELINES FOR COMPUTER ORGANISATION ARCHITECTURE COURSES Computing professionals should not regard the computer as just a black box that executes programs by magic. Students should acquire an understanding and appreciation of a computer systems functional components, their characteristics, performance, and interactions Students need to understand computer architecture to develop programs that can achieve high performance through a programmers awareness of parallelism and latency. The learning outcomes specified for core topics of AC by ACM. 1. Digital Logic and Digital Systems Design the basic building blocks of a computer: arithmetic-logic unit (gate-level), registers (gate-level), central processing unit (register transfer-level), memory (register transfer-level). 2.Machine Level Representation of Data Explain why everything is data, including instructions, in computers. Explain the reasons for using alternative formats to represent numerical data. 3. Assembly Level Machine Organisation Describe how an instruction is executed in a classical von Neumann machine, with extensions for threads, multiprocessor synchronisation, and SIMD execution.
  4. 4. 4. Memory System Organisation and Architecture Identify the main types of memory technology (e.g., SRAM, DRAM, Flash, magnetic disk) and their relative cost and performance. Describe how the use of memory hierarchy (cache, virtual memory) is used to reduce the effective memory latency. 5. Interfacing and Communication Explain how interrupts are used to implement I/O control and data transfers. Identify various types of buses in a computer system. 6. Functional Organisation Compare alternative implementation of datapaths. Discuss the concept of control points and the generation of control signals using hardwired or microprogrammed implementations Design and implement a complete processor, including datapath and control. 7. Multiprocessing and Alternative Architectures Discuss the concept of parallel processing beyond the classical von Neumann model Describe alternative parallel architectures such as SIMD and MIMD 8. Performance Enhancements Describe superscalar architectures and their advantages. Explain the concept of branch prediction and its utility.
  5. 5. CS/ECE 552: Introduction to Computer Architecture, University of Wisconsin Where does the course t in your curriculum? This is taken by juniors, seniors, and beginning graduate students in computer science and computer engineering. Prerequisites include courses that cover assembly language and logic design. This course is a (recommended) prerequisite for a graduate course on advanced computer architecture. Approximately 60 students take the course per offering; it is offered two times per year (once each semester). Assessment Assessment is a combination of homework, class project, and exams. There are typically six homework assignments. The project is a detailed implementation of a 16-bit computer for an example instruction set. The project requires both an unpipelined as well as a pipelined implementation and typically takes close to a hundred hours of work to complete successfully. The project and homeworks are typically done by teams of 2 students. There is a midterm exam and a final exam, each of which is typically 2 hours long. 20% Homework 25% Project 25% Midterm 25% Final 5% Class participation Tools Mentor, ModelSim, WISC-SP08 Simulator-debugger, cacheSim, Knowledge Area Total Hours of Coverage Architecture and Organization (AR) 39
  6. 6. Knowledge Unit Topics Covered Introduction and Performance Technology trends, Measuring CPU performance ,Amdahls law and averaging performance metrics Instruction Sets Components of an instruction set,Understanding instruction sets from an implementation perspective,RISC and CISC and example instruction sets Computer Arithmetic Ripple carry, carry lookahead, and other adder designs,ALU and Shifters,Floating-point arithmetic and floating-point hardware design Datapath and Control Single-cycle and multi-cycle datapaths,Control of datapaths and implementing control finite-state machines Pipelining Basic pipelined datapath and control,Data dependences, data hazards, bypassing, code scheduling.Branch hazards, delayed branches, branch prediction Memory Hierarchies Caches (direct mapped, fully associative, set associative) ,Main memories,Memory hierarchy performance metrics and their use,Virtual memory, address translation, TLBs Input and Output Common I/O device types and characteristics,Memory mapped I/O, DMA, program-controlled I/O, polling, interrupts,Networks Multiprocessors Introduction to multiprocessors ,Cache coherence problem . Course textbooks and materials David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware and Software Interface Morgan Kaufmann Publishers, What is covered in the course?
  7. 7. CC152: Computer Architecture and Engineering, University of California, Berkeley Where does the course t in your curriculum? This is a senior-level course in the computer science curriculum for computer engineering students interested in computer design. Assessment Examinations, homeworks, and hands-on laboratory exercises.The class will have two mid-terms and no final. The class will have two long homework assignments. Labs: The centerpiece of the class is a set of computer architecture lab assignments based on RISC-V processors implemented in the Chisel hardware description language. Three architecture simulation labs are the focus of the class: Lab 1 (directed, open-ended) covers static pipelined CPUs. Lab 2 covers the memory hierarchy. Lab 3 covers dynamically-scheduled CPUs. The heart of each lab is the open-ended section. This section lists a set of computer architecture project topics that are a good fit to a 3-week work schedule. Students pick one of the open-ended projects, and focus on doing the best job possible during the allotted time period. Academic Honesty: Copying all or part of another person's work, or using reference material not specifically allowed, are forms of cheating and will not be tolerated. A student involved in an incident of cheating will be assigned an F grade or a 'zero' grade to the subject work Knowledge Area Total Hours of Coverage Architecture and Organization (AR) 33
  8. 8. Knowledge Unit Topics Covered Digital Logic and Digital Systems N/A Machine Level Representation of Data N/A Assembly Level Machine Organization Historical Perspectives Memory System Organization and Architecture Memory Hierarchy, Virtual Memory, Snooping Caches Interfacing and Communication Synchronization, Sequential Consistency Functional Organization Pipelining Multprocessing and Alternative Architecture Superscalar, VLIW, Vector Processing Performance Enhancements Complex Pipelining . Additional topics Case Study: Intel Sandy Bridge & AMD Bulldozer (1.5); Warehouse-Scale Computing (1.5) Course textbooks and materials J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 5th Edition, Morgan Kaufmann Publishing Co., Menlo Park, CA. 2012. What is covered in the course?
  9. 9. 6.823 Computer System Architecture - Spring 2015, Massachusetts Institute of Technology Overview This course is a study of the evolution of computer architecture and the factors inuencing the design of hardware and software elements of computer systems. This is graduate level course. Assessment 75% of the grade will be based on the four quizzes, equally weighted. The remaining 25% of the grade will be based on four laboratory exercises. The last two labs have twice the weight of the first two.Tools Laboratory Exercises There will be four Laboratory Exercises that will explore the concepts taught in lecture using industrial strength tools. Two to three weeks will be allotted for the completion of each lab. Tool Pin - A Dynamic Binary Instrumentation Tool Knowledge Area Total Hours of Coverage Architecture and Organization (AR) 40
  10. 10. What is covered in the course? Introduction & History of Calculation and Computer Architecture Inuence of Technology and Software on Instruction Sets: Up to the dawn of IBM 360 Hardwired, Single-cycle ISA Implementation Instruction Pipelining and Hazards Instruction Pipelining: Hazard Resolution and Timing Constraints Caches Memory Management from Absolute Addresses to Demand Paging ModernVirtual Memory Systems Complex Pipelining Out-of-Order Execution, Register Renaming and Exceptions Branch Prediction Speculative Execution Advanced Memory Operations Multithreading Architectures On-chip Networking (I) On-chip Networking (II) Cache Coherence (I) Cache Coherence (II) Memory Consistency Models Transactional Memory Microcoded and VLIW Processors Vector Computers Graphics Processing Units Reliability Course Reading Material: Computer Architecture:A Quantitative Approach: 5th Edition by J. L. Hennessy and D.A. Patterson
  11. 11. CSL 211 - Computer Architecture, IIT Delhi Where does the course t in your curriculum? The 'Computer Architecture' course is intended to teach undergraduate students in Electrical Engineering and Computer Science the basics of computer architectures. Credits : 5 [3-1-2] (L-T-P) Assessment MINOR - I 10%, MINOR -II 15%, MAJOR 25%, ASSIGNMENTS 50% Tools Tejas Architecture Simulator, EmuArm (GUI based ARM Emulator), NASM assembler, Logisim ACADEMIC MISCONDUCT Academic misconduct such as cheating will not be tolerated. The work you submit in this class is expected to be your own. If you submit work that has in part or in whole been copied from some published or unpu