VIRTEX - 4 LAYOUT
Virtex-4 FPGA Family Members
POWER PC
I/Os Pad Left Global Clock
DCMs
PCMDs
Buffer I/Os
BUFGCTRLs
I/O BanksI/Os Pad Right
DSP Block
BRAM
CLBs (32 CLBs)
pp
PowerPC
I/O PADS LEFT
I/O PADS RIGHT
BASIC I/O DIAGRAM
V4 I/O TILES
DCMs
PMCDs
Buffer I/Os
DCMS(Top Half)
DCMS(Bottom
Half)
PMCD(Top Half)
PMCD(Bottom
Half)
Buffer I/Os
BUFGCTRLs
(Top Half)BUFGCTRLs
(Bottom Half)
Buffer I/Os
ILOGIC
IOB
IOBank BUFGCTR
Ls
BUFGCTRLs
ICAP
BUFGCTRLs
BLOCK RAM
BLOCK RAM
Configurable Logic Blocks (CLBs)
Arrangement of Slices within the CLB
Simplified Virtex-4 General SliceL/ SliceM
THANKS