Sandbridge SDR Processor Technology with Application to
MIMO-OFDM Receivers
John Glossner, Ph.D., Co-Founder, CTO & EVP
Daniel Iancu, Ph.D., Chief Communications Architect
Hua Ye, Ph.D., Principal Engineer
Tanuj Raja, V.P. Business [email protected]
1 North Lexington Ave, 10th FloorWhite Plains, New York 10601
914-287-8500
Agenda
Sandbridge IntroductionMarket ObservationsSandbirdge Solution
Architecture
Hardware
SoftwareIDECompilerSimulator
Communications2.5G / 3GWLANDVB-T
MIMO OFDM DVB-T
Results
Summary
FablessSemiconductor
Company
developing…
Software reconfigurable
Wireless chipsets for low powerapplications
Sandbridge Technologies
What is it that we eventually carry with us ?
3 15 3570
140
0
100
200
300
400
500
600
700
M U
nits
2001 2002 2003 2004 2005camera enabled handsetstotal handset market
It has a color screen, camera, audio and antenna …… but all features need high computing performance
and ultra low power consumption Wireless communication 2G – 2.5G – 3G – WLAN – BT – etc.
GSM/IS-95a,b/IS-136/PDC/ iDEN – CDMA2k/GPRS/EDGE – FDD/TDD/TD-SCDMA/Jap.WCDMA/CDMA2k-3x– 802.11a,b,g
Radio broadcast GPS – radio – TV – etc.Location based services/911/tracking services – AM/FM/DAB – Sat./Terr.TV
Encryption – decryption – media encode – media decodeGames – speech to text – natural language processing
sources: In-Stat/MDR, TSR, Dresdner, Dataquest
A Whole Industry’s approach failed …
DSP
Fixed
ARM
WLAN802.11
GSM
Bluetooth
GPRS
CDMA2k
CDMAone
JavaWCDMA
FDD
IS-136
MPEG-4
MP3
EDGE
PDC
USB
DSP
ARM
VGA
… on advanced wireless systems …
… with multimedia
WCDMATD-SCDMA
WCDMATDD
GPS
DAB
The Sandbridge Approach …
Improved productivity C compiler70% reduction In time-to-marketUser-friendly
SandBlasterTM DSP
ProgrammableUltra-low powerHigh-performanceMultithreaded
SandBlasterTM Tools
DSP Platform
Scalable & Programmable
Integrated Sandblaster cores
Up to 2Mbit/sec data rate
40,000 RISC MIPS
Low Cost 0.13um CMOS
Integrated protocol stack
Low Cost
Power Efficient
Ultra-high performance
Fully tested / validated
Dedicated Customer Support
Flexible and upgradeable
DSP Ref Design
Core technology equally applicable to Networking, Storage, Automotive, GP-DSP, etc.
ONE platform for ALL Mobile Devices
Compiler
Architecture
OptimizeCost / PowerPerformance
Sandbridge provides the raw
processor platform
Implementany feature in SW
TD-SCDMATD-SCDMA802.11a802.11a
GSMGSM
BluetoothBluetoothGPSGPS
CDMACDMA
IS-95IS-95
JavaJava WCDMAWCDMA
IS-136IS-136
MPEG-4MPEG-4
MP3MP3AACAAC
PDCPDC
USBUSB
802.11b802.11b
Sandbridge One Global Solution
Memory MMC/SD
USIM PeripheralsCircuits
One Digital SolutionOne Digital SolutionRFRF
SW SW ApplicationsApplications
HWHWPlatformPlatform
CommunicationCommunication•• 2.5G2.5G•• 3G3G•• WLANWLAN•• GPSGPS•• ......
VideoVideo•• MPEG2/4MPEG2/4•• PhotoPhoto•• Video clipVideo clip•• ConferencingConferencing•• ……
AudioAudio•• MP3MP3•• AACAAC•• Atrac3• Vocoders• …
BroadcastingBroadcasting•• GPS GPS •• Dig. TVDig. TV•• Dig. AudioDig. Audio•• ……
Voice RecognitionVoice Recognition•• SpeechSpeech--toto--texttext•• CommandCommand•• Language Language •• ……
GamesGames SecuritySecurity•• EE--commercecommerce•• MM--commercecommerce•• EncryptionEncryption•• ……
Handset design at C level in min. timeSimulation Speed
(1GHz Laptop)
0.114 0.106
0.0020.013
24.639
0.001
0.010
0.100
1.000
10.000
100.000
Mill
ions
of I
nstru
ctio
ns P
er S
econ
d
SB 24.639
TI C64x (Code Composer) 0.114
TI C62x(Code Composer) 0.106
SC140(Metrow erks) 0.002
ADI Blackfin (Visual DSP) 0.013
Complete system design in CCycle accurate simulator delivers immediate feedbackDesign for conformance in C
System performance by designParallelizing compiler generates production assembly codeMultithreading (sea-of-threads) ensures concurrent execution
AMR Encoder(out-of-the-box C code)
0
100
200
300
400
500
600
700
SB TI C64x TI C62x SC140 ADI BlackFin
DSP's
Mhz
Sandbridge Design Approach
HWModel
HWProduct
Analysisand
Design partitioning
App. Modeling, SW Devand
Verification
Design Optimization
SDK HWModel
SW Tools Dev HW Dev
HWProductConformance Validation
SDR Drivers/Requirements
HWModel
HWProduct
Analysisand
Design partitioning
App. Modeling, SW Devand
Verification
Design Optimization
SDK HWModel
SW Tools Dev HW Dev
HWProductConformance Validation
SDR Drivers/Requirements
Communications Design Overview&
Modeling Demonstration
Communications Design Overview&
Modeling Demonstration
SW Tools Overview&
Tools Demonstration
SW Tools Overview&
Tools Demonstration
HW Overview&
HW Model Demonstration
HW Overview&
HW Model Demonstration
Beginning to-end designAll components of design considered
Sandblaster Architecture Performs
CompilableDSP
Java ProcessorControl
Processor
SystemProductivityAdvantage
9-12+ months
3G Applications Standard 3G, xDSL, 802.11Control Stacks
C programmedLatency hiding architecture
Multithreaded Architecture Enables C
Thread 0# Monitoring FCCH&SCHlu r1,M(r2) lu r1,M(r2) add r2,r3,r4cmp cf2,r5,r3jc cf2,(Synch_off)
Thread 7# Monitoring CPICHlu r1,M(r2)lu r1,M(r2) call (De_scrambler)
stu r3,M(r2)
Thread 6# Handover Code
ctsr r1,sr2 lu r1,M(r2).jc cf0,(UMTS_Mode)
Thread 5# FIR Filter
lvu vr1,M(r4)vmacs
vr3,vr1,vr2,wr0loop lcr0,label(4x)
Thread 4# Pulse shaping Code
lvuvr1,M(r4)vmacs vr3,vr1,vr2,wr0loop lcr0,label(4x)
Thread 3# WCDMA Handover Code
ctsr r1,sr2 lu r1,M(r2).jc cf0,(WCDMA_Mode)
Thread 2# Exit Code ..Start Thread33..Start Thread24
)
Thread 1# WCDMA Main
Start Thread0Start Thread1Start Thread2
Start Thread13Start Thread14loop lc1,0xf0
)
Sea of Threads
Java Processor
3G Applications Standard
Code&Data Sharing Across Threads
FastCross Thread
Interrupts
Key to Low Power Implementation
Hardware Scheduled
FullyInterlocked
HighlyParallel
CProgrammed
ControlProcessor
3G, xDSL, 802.11Control Stacks
CompilableDSP
C programmedLatency hiding architecture
CompilableDSP
Java ProcessorControl
Processor
SystemProductivityAdvantage
9-12+ months
3G Applications Standard 3G, xDSL, 802.11Control Stacks
C programmedLatency hiding architecture
Parallel DSP
I –C
ache
64K
B64
B L
ines
4W (2
-act
ive)
I- DecodeI- Decode
JumpQ PCCRJTRLCR
Data Buffer
MPY
VRABC
VPR0
MPY
VRABC
VPR1
PABC
MPY
VPR2
MPY
VPR3
SAT
VRABC VRABC
PABCPABCPABC
ACC ACC ACC ACCADD ADD ADD ADD
AGEN
(16) 32-bit GPR
LS IQ
LRA LRB
Address
DirLRU Replace
Data Memory64KB
Data Memory64KB
Data Memory64KB
Data Memory64KB
Data Memory64KB
Data Memory64KB
Data Memory64KB
Data Memory64KB
8-Banks
INT IQ
IRA IRB
ALU
WB
Bus/MemoryInterface
Interrupt SIMDIQ
High ParallelismVector / SIMD data parallelismMultiple instruction issueThread-level parallelism
SBTC 8/02
DSP
Ins & Data Memory(64KB / 64KB)
EXT
INT
RCVRI/O
I2C
TDMInfc (2)
RF DeviceControl
TDM
A/D Data
SPI
XMTRI/O
RF DeviceControl
D/A Data
To/FromExternalMemory
Memory Bus
GPIOStatic Cntl SystemClk/Cntl
0.18um CMOS ASICSingle DSP CoreSW Programmable
External Bus for L2 memoryInternal Inst/Data memoryControl Interfaces: I2C, SPI, TDM, A/D, D/A
SB3000 Handset Chip
GeneralPurpose I/O
Smart CardInterface
Sync SerialPort
KeyboardInterface
KeypadInterface
UART/IrDA
AudioCodec
Interface
GeneralPurpose I/O
Timers
RTC
MultimediaCard
Interface
32.768KHz
Multi PortMemory
Controller
USBInterface
LCDInterface
AHB APBBridge
PeripheralDevice Control
DMAController
ARMProcessor
Vector InterruptController
DSP ARMBridge
DSP
Ins & Data Mem(64KB / 64KB)
L2 Mem
(256KB
)
EXT INT
DSP
Ins & Data Mem(64KB / 64KB)
L2 Mem
(256KB
)
EXT INT
DSP
Ins & Data Mem(64KB / 64KB)
L2 Mem
(256KB
)
EXT INT
DSP
Ins & Data Mem(64KB / 64KB)
L2 Mem
(256KB
)
EXT INT
DSP Complex
GeneralPurpose I/O
SerialInterfaces(SPI, I2C)
ParallelStreaming
DataInterface
Prog.Timers/Gens
Clock Generation
10 – 50MHz REFREF1 REF2Ext. clks
Int. clks...
DSP Local Peripherals TAP(JTAG Port)
RF Control
Timer I/O
TX DataRX Data
Memory Interface(Synchronous and
Asynchronous)
Replicated SBTC coreLow Power design
Sandblaster Tools
SaDL
C
C++
Java
SandblasterCompiler
sb.o
BinaryTranslator
x86asm
C x86asm
compiledsimulator
dynamicsimulator
Compiler Optimizations – Dragon Book +
Loop Optimizations
Loop Invariant Code MotionStrength Reduction
Induction Variable EliminationLoop Splitting
Software Pipelining
Loop Optimizations
Loop Invariant Code MotionStrength Reduction
Induction Variable EliminationLoop Splitting
Software Pipelining
Vector Optimizations
Vector LoadsVector Stores
Vector ArithmeticVector Reduction
Saturating Vector Operations
Vector Optimizations
Vector LoadsVector Stores
Vector ArithmeticVector Reduction
Saturating Vector Operations
DSP Optimizations
Saturation ArithmeticFixed Point Semantic AnalysisBit-exact ETSI compliance
DSP Optimizations
Saturation ArithmeticFixed Point Semantic AnalysisBit-exact ETSI compliance
Multithreaded Optimizations
OpenMPAutomatic ParallelizationAutomatic Multithreading
Multithreaded Optimizations
OpenMPAutomatic ParallelizationAutomatic Multithreading
Interprocedural Opts.
Constant PropagationMemory Disambiguation
Function InliningAlias Analysis
Interprocedural Opts.
Constant PropagationMemory Disambiguation
Function InliningAlias Analysis
Java Support
Java J2ME implementationKVM 1.0 bytecode engineCLDC 1.0MIDP 1.0 support provided
MIDP 2.0 3Q04
Multiple Java threads execute on multiple H/W thread unitsFirst known hardware multithreaded KVMSandblaster tools compile KVM with Java-specific optimizationsJava is another application on the Sandblaster processorA java thread is scheduled on any available hw thread unit
– Dynamic number of hardware thread units may be usedSynchronization mechanisms fully supportedMultithreaded Garbage collection supported
Development Environment
Host Platform (Windows, Linux)
Integrated Dev.Environment
Application Software (C) SW Tool Kit
Compile
PerformanceAnalysis
Debug
Simulate
Assemble & Link
Target Platform
SandBlaster™Dev. Board
Integrated Development Environment (IDE)
Based on Java open source netbeansEnhanced with
C compilation and editing toolsSource debuggerProject managementScripting languages
Automatic Error recognitionWorks in multiple languages too!
Development Methodology
MATLAB physical layerEnd-to-end UTRAN + UEChannel modelsConfigurable via test-scriptsBER/FER measurement
Simulation level CFixed pointUE onlyFixed configurationPerformance measurement
Product level CPartitioned for real-timeUsing actual peripheralsIntegrate with L1 control + L2/L3
Physical layer testingUTRAN model validated against test equipmentmodels & test cases specifications used to test Matlab & C
DVB-T Receiver
OFDM ReceiverData Services
Audio Services
MPEG-2DecoderSystem
andDe-
Multiplexer
Video Services
DTV-T ChannelDecoder
OFDM(FFT)2k/8k
Pilot
A/D
RXRF
Front-End
UHF/VHF
MPEG-2TrasnportStream
(TS)
Viterbi-Decoder
RS decoder(204,188)
t=8
OuterDe-
Interleaver
EneregyDisperseremoval
Demodulation
Inner-De-
Interleaver
Pilot & TPSdecoder
DVB-T Rx with Spatial Diversity Input
OFDM Receiver
OFDM(FFT)2k/8k
D/A
RXRF
Front-End
UHF/VHF
Demodulation Pilot & TPSdecoder
ChannelEstimation
OFDM(FFT)2k/8k
D/A
RXRF
Front-End
UHF/VHF
Demodulation Pilot & TPSdecoder
ChannelEstimation
OFDM(FFT)2k/8k
A/D
RXRF
Front-End
UHF/VHF
Demodulation Pilot & TPSdecoder
ChannelEstimation
Data Services
Audio Services
MPEG-2DecoderSystem
andDe-
Multiplexer
Video Services
DTV-T ChannelDecoder
Pilot
MPEG-2TrasnportStream
(TS)
Viterbi-Decoder
RS decoder(204,188)
t=8
OuterDe-
Interleaver
EneregyDisperseremoval
Inner-De-
Interleaver
Combiner
OFDM Receiver Block Diagram
Sandbridge OFDM Receiver implemented in Software
A/D
VCXO
Sampling RateCorrection
Interpolationand
Decimation
DigitalI/Q Gen.
FrequencyOffset
CorrectionGuardPeriod
Removal
Initial CoarseSymbol Sync.
InitialCoarse
FrequencyOffset
estimation
OFDMDemod2k/8kFFT
ChannelCorrection
ChannelEstimation
SNREstimation
TPSDecoding
Post-FFTFreq. OffsetEstimation
Post-FFTsampling
rateEstimation
Post-FFTSymboltiming
EstimationTracking
To QAMDemod.
To ViterbiDecoder
MIMO OFDM DVB-T Rx PerformanceMultiple receivers with equal weight combining
64 QAM, Rate ½, portable Rayleigh fading,10-11 Quasi Error Free BER conforming to ETSI EN 300 744 V1.4.1 (2001-01)
0
4
8
12
16
20
1 2 3 4Number of receivers
SNR
dB
Spec Implementation