EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 1
EE247Lecture 17
ADC Converters• Sampling
– Sampling switch induced distortion• Sampling switch conductance dependence on input voltage
– Sampling switch charge injection• Complementary switch• Use of dummy device• Bottom-plate switching
– Track & hold circuit– S/H circuit incorporating gain
• ESD protection impact on converter performance
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 2
Practical Sampling
22 1
12B
BFS
C k TV
−≥
( )1 for inON o o ox DD thDD th
WVg g g C V V
V V Lµ = − = − −
( )1 1
2 ln 2 1BsR
f C
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 3
Sampling Distortion
10bit ADC & T/τ = 10VDD – Vth = 4V VFS = 1V
10bit ADC & T/τ = 10VDD – Vth = 2V VFS = 1V
• Effect of lower supply voltage on sampling distortionà HD3 increases by (VDD1/VDD2)2
àHD2 increases by (VDD1/VDD2)
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 4
Sampling Distortion
10bit ADC T/τ = 20VDD – Vth = 2V VFS = 1V
• SFDR is sensitive to sampling distortion to improve distortion
• Larger VDD • Higher sampling
bandwidth• Solutions:
• Overdesignà Larger switchesà Increased switch
charge injectionà Increased nonlinear S &D junction C
• Maximize VDD/VFSàDecreased dynamic range if VDD const.
• Complementary switch• Constant & max. VGS ?
f(Vin)
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 5
Complementary Switch
φ1φ1B
φ1
φ1Bgon
gop
goT =gon + gopgo
•Complementary n & p switch advantages:•Increases the overall conductance•Linearize the switch conductance for the range Vtp< Vin
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 7
Complementary SwitchEffect of Supply Voltage Scaling
gon
gop
goT =gon + gopgo
•As supply voltage scales down input voltage range for constant go shrinksà Complementary switch not effective when VDD becomes comparable to Vth
φ1φ1B
φ1
φ1B
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 8
Boosted & Constant VGS Sampling
• Increase gate overdrive voltage as much as possible + keep VGS constantØSwitch overdrive voltage is independent of signal levelØError from finite RON is linear (to first order)ØLower Ron achieved à lower time constant
VGS=const.
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 9
Constant VGS Sampling
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 10
Constant VGS Sampling Circuit
C11pF
C21pF
M110 / 0.35
M210 / 0.35
VDD=3V
VP1100ns
M310 / 0.35
C31pF
M1210 / 0.35
M510 / 0.35
M410 / 0.35
M810 / 0.35
10 / 0.35
M9
10 / 0.35
M610 / 0.35
M11
10 / 0.35
M11
10 / 0.3510 / 0.35
M11
10 / 0.35
VS11.5V1MHz
Chold1pF
P
P
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 11
Clock Voltage Doubler
C11pF
C21pF
M110 / 0.35
M210 / 0.35
VDD=3V
VP1100ns
P
P_N
P_Boost
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 12
Constant VGS Sampler: Φ LOW
• Sampling switch M11 is OFF
• C3 charged to VDD
Input voltagesource
Constant Vgs Switch: P is LOW
VDD
M310 / 0.35
C31pF
M1210 / 0.35
M410 / 0.35
OFF
VS11.5V1MHz
Chold1pF
~ 2 VDD
(boosted clock)VDD
VDD
VDD
OFF M11OFF
DeviceOFF
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 13
Constant VGS Sampler: Φ HIGH
• C3 previously charged to VDD
• M8 & M9 are on:C3 across G-S of M11
• M11 on with constant VGS = VDD
Constant Vgs Switch: P is HIGH
C31pF
M810 / 0.35
10 / 0.35
M9
10 / 0.35 10 / 0.3510 / 0.3510 / 0.35
M11
10 / 0.35
VS11.5V1MHz
Chold1pF
VDD
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 14
Constant VGS Sampling
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 15
Complete Circuit
Ref: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599.
Clock Multiplierfor M3
Switch
M7 & M13 for reliability
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 16
Advanced Clock Boosting
[H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 1769-1780, Dec. 2000]
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 17
Advanced Clock Boosting
• Gate tracks average of input and output, reduces effect of I·R drop at high frequencies
• Bulk also tracks signal ⇒ reduced body effect (technology used allows connecting bulk to S)
• SFDR = 76.5dB at fin=200MHz (measured)
[M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Techn. Papers, pp. 314.]
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 18
Switch Off-Mode Feedthrough Cancellation
Ref: [M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Techn. Papers, pp. 314.]
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 19
Practical Sampling
vIN vOUT
CM1
φ1
• Rsw = f(Vin) à distortion• Switch charge injection
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 20
Sampling Switch Charge Injection
VIN VO
Cs
M1
VG
• First assume VIN is a DC voltage• When switch turns off à offset voltage induced on Cs• Why?
VG
t
VH
VIN
VL
VIN -Vth
VOVIN
toff
∆V
t
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 21
SamplingSwitch Charge Injection
• Channel à distributed RC network• Channel to substrate junction capacitance à distributed & variable• Over-lap capacitance Cov = LDxWxCox associated with GS & GD overlap
MOS xtor operating in triode regionCross section view
Distributed channel resistance & gate & junction capacitances
S
G
D
B
LD
L
Cov Cov
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 22
Switch Charge InjectionSlow Clock
• Since clock fall time >> device speed à During the period (t- to toff) current in channel discharges channel charge into source
• Only source of error à Charge transfer from Cov into Cs
VG
t
VH
VIN
VL
VIN -Vth
VOVIN
toff
∆V
tt-
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 23
Switch Charge InjectionSlow Clock
VG
t
VH
VIN
VL
VIN -Vth
VOVIN
toff
∆V
t
D
Cov
VG
( )
( )
( )
( )
ovi th L
ov s
ovi th L
s
o i os
ov ovos th L
s s
CV V V V
C C
CV V V
CV V 1 V
C Cwhere ; V V V
C C
ε
ε
∆ = − + −+
≈ − + −
= + +
= − = − −
t-
Cs
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 24
Switch Charge InjectionSlow Clock- Example
( )
2ov ox th
ov
s
ovos th L
s
C 0.3 fF / C 5 fF / V 0.5V
C 12 x0.3 fF /.36% 7 bit
C 1pF
CV V V 1.8mV
C
µ µ
µ µε
= = =
= − = − = − → −
= − − = −
VG
t
VH
VIN
VL
VIN +Vth
VOVIN
toff
∆V
t
VIN VO
Cs=1pF
M1
VG 12µ/0.35µ
t-
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 25
Switch Charge InjectionFast Clock
VG
t
VH
VIN
VL
VIN +Vth
VOVIN
toff
∆V
t
VIN VO
Cs=1pF
M1
VG
• Sudden gate voltage drop à no gate voltage to establish current in channel àchannel charge has no choice but to escape out towards S & D
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 26
Switch Charge InjectionFast Clock
( )
( ) ( ) ( )( )
( )
( ) ( )
ov cho H L
ov s s
ox H i thov DH L
ov s s
o i os
ox
s
ov ox H thos H L
s s
C 1 QV V V
C C 2 C
WC V V VC 1 L 2LV V
C C 2 C
V V 1 V
1 WC Lwhere
2 C
C 1 WC L V VV V V
C 2 C
ε
ε
∆ = − − − ×+
− −−≈ − − − ×
+
= + +
= − ×
−= − − − ×
• Assumption à channel charge divided between S & D 50% & 50%• Source of error à channel charge transfer + charge transfer from Cov into Cs
VG
t
VH
VIN
VL
VIN -Vth
VOVIN
toff
∆V
t
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 27
Switch Charge InjectionFast Clock- Example
( ) ( )
2ov ox th DD
ox
s
ov ox H thos H L
s s
C 0.3 fF / C 5 fF / V 0.5V V 3V
WLC 12 x0.35x5 fF /1 / 2 2.1% 4.5 bit
C 1pF
C 1 WC L V VV V V 9mV 26.3mV 45.3mV
C 2 C
µ µ
µ µε
= = = =
= − = = − → −
−= − − − × = − − = −
VIN VO
Cs=1pF
M1
VG 12µ/0.35µ VG
t
VH
VIN
VL
VIN -Vth
VOVIN
toff
∆V
t
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 28
Switch Charge Injection
à Both errors are a function of clock fall time, input voltage level, source impedance & sampling capacitance
Clock fall time
ε VOS
Clock fall time
2.1%
.36%
45mV
1.8mV
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 29
Switch Charge InjectionError Reduction
( )
( )
( )( )
sON s
ox GS th
cho
s
ox H i thso
sox GS th
2
CR C W
C V VL
1 QV
2 C
WC L V V VC 1FOM V W 2 CC V V
L
LFOM
µ
µ
µ
τ
τ
= =−
∆ = −
− −= ∆ ≈ ×
−
≈
× ×
• How do we reduce the error?àReduce size switch?
àReducing switch size increases τ à increased distortionà not a viable solutionàSmall τ and ∆V à use minimum chanel lengthàFor a given technology τ x ∆V=conts.
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 30
Sampling Switch Charge InjectionSummary
• Extra charge injected onto sampling capacitor @ switch device turn-off– Charge sharing with Cov– Channel charge transfer
• Issues:– DC offset– Input dependant error voltage à distortion
• Solutions:– Complementary switch?– Addition of dummy switches?– Bottom-plate sampling?
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 31
Switch Charge InjectionComplementary Switch
• In slow clock case if area of devices are equal à effect of overlap capacitor for n & p devices cancel to first order (matching n & p area)
φ1φ1B
φ1
φ1B
VG
t
VH
VIN
VL
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 32
Switch Charge InjectionComplementary Switch
• In fast clock case §Offset cancelled for equal device area§Input voltage dependant error worse!
φ1
φ1B
VG
t
VH
VIN
VL
( )
( )
( )
ch n n ox n H i th n
th pch p p ox p i
ch p ch no
s s
o i os
n ox n p ox p
s
Q W C L V V V
VQ W C L V VL
Q1 QV
2 C C
V V 1 V
W C L W C L1
2 C
ε
ε
− −
−−
− −
= − −
= − −
∆ = −
= + +
+= − ×
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 33
Switch Charge InjectionDummy Switch
VIN VO
Cs
t
VH
VIN
VL
VG VGB
• Dummy switch same L and main switch but half W • Main device clock goes low, dummy device goes high à dummy switch acquires
same amount of channel charge main switch needs to lose§ Effective only if exactly half of the charge transferred to M2 and good matching
between clock fall/rise
WM2=1/2WM1VG VGB
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 34
Switch Charge InjectionDummy Switch
VIN VOM1
VG
M2
VGB
§ To guarantee half of charge goes to each sideà create the same environment on both sides§Add C equal to sampling capacitor to the other side of the switch + add fixed resistor
§ Degrades sampling bandwidth
CsCs
RWM2=1/2WM1
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 35
Dummy SwitchDummy Switch Effectiveness Test
Ref: L. A. BIENSTMAN et al, “ An Eight-Channel 8 13it Microprocessor Compatible NMOS D/A Converter withProgrammable Scaling”, IEEE JSSC, VOL. SC-15, NO. 6, DECEMBER 1980
•Dummy switch àW=1/2Wmain
•Note large Lsà good device area matching
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 36
Switch Charge InjectionBottom Plate Sampling
VI+
VO+M1A
VI-VO-
M1B •Switches M2A@ B are opened slightly earlier compared to M1A&Bà Injected charge by the opening or M2AB is constant & eliminated when used differentially
•Since bottom plate of Cs is open when M1A&B are openedà no charge injected on Cs
φ1b
φ1aM2B
M2A
φ1aVH
VL
t
φ1b
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 37
Flip-Around T/H
vIN vOUT
C
S1A
φ1D
S2
φ2
S2A
φ2
S3
φ1D
φ1 S1
vCM
φ1
φ1D
φ2
•Concept based on bottom-plate sampling
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 38
Flip-Around T/H
vIN vOUT
C
S1A
φ1D
S2
φ2
S2A
φ2
S3
φ1D
φ1 S1
vCM
Charging C
φ1
φ1D
φ2
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 39
Flip-Around T/H
vIN vOUT
C
S1A
φ1D
S2
φ2
S2A
φ2
S3
φ1D
φ1 S1
vCM
Holding
φ1
φ1D
φ2
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 40
Flip-Around T/H - Timing
vIN vOUT
C
S1A
φ1D
S2
φ2
S2A
φ2
S3
φ1D
φ1 S1
vCM
Sampling
S1 opens early tosample the input"Bottom Plate Sampling"
φ1
φ1D
φ2
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 41
Charge Injection• At the instant of sampling, some of the
charge stored in sampling switch S1 is dumped onto C
• With "Bottom Plate Sampling", charge injection comes only from S1 and is to first-order independent of vIN– Only a dc offset is added to the input signal– This dc offset can be removed with a
differential architecture
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 42
Flip-Around T/H
vIN vOUT
C
S1A
φ1D
S2
φ2
S2A
φ2
S3
φ1D
φ1 S1
vCM
Constant switch VGSto minimize distortion
φ1
φ1D
φ2
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 43
Flip-Around T/H
vIN vOUT
C
S1A
φ1D
S2
φ2
S2A
φ2
S3
φ1D
φ1 S1
vCM
Small Nch-only φ1
φ1D
φ2
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 44
Flip-Around T/H• S1 is an n-channel MOSFET• Since it always switches the same voltage, it’s on-
resistance, RS1, is signal-independent (to first order) • Choosing RS1 >> RS1A minimizes the non-linear
component of R = RS1A+ RS1– S1A is a wide (much lower resistance than S1) constant VGS
switch– In practice size of S1A is limited by the (nonlinear) S/D
capacitance that also adds distortion– If S1A’s resistance is negligible, aperture delay depends only
on S1 resistance– S1 resistance is independent of vIN; hence, aperture delay is
independent of vIN
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 45
S/H Combined with Gain Stage
Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987
• Gain=4CI/Ci=4
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 46
S/H Combined with Gain Stage
Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 47
S/H Combined with Gain Stage
Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987
• Gain=4C/C=4
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 48
ESD ProtectionADC Architectures
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 49
What is ESD?
• Electrostatic discharge• Example: Charge built up on human body
while walking on carpet...• Charged objects near or touching IC pins
can discharge through on-chip devices• Without dedicated protection circuitry, ESD
events are destructive
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 50
Model and Protection Circuit
[http://www.ce-mag.com/archive/03/ARG/dunnihoo.html]
[http://www.idt.com/docs/AN_123.pdf]
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 51
Equivalent Circuit
• Nonlinear capacitance causes distortion• Distortion increases with frequency
– Today's converters: High frequency, low distortion!
[I. E. Opris, "Bootstrapped pad protection structure,"IEEE J.Solid-State Circuits, pp. 300, Feb. 1998.]
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 52
ESD Circuit Distortion
[I. E. Opris, "Bootstrapped pad protection structure," IEEE J.Solid-State Circuits, pp. 300, Feb. 1998.]
C(Vin)= 2..4pFfor Vin=2..0V
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 53
ESD Circuit Distortion
• Analysis: Volterra Series (see handout on the web)
• Example:
R Cj CL
vi vo R=25ΩCjo=1pFCL=5pFVipeak=0.5V
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 54
ESD Circuit Distortion
1 .106 1 .107 1 .108 1 .109 1 .1010
100
80
60
Second Order Distortion [dBc]
Input frequency
50−
110−
20 log HD 2 f( )( )⋅( )
1010106 f
HD3(37.5MHz) = -92dBHD3(100MHz) = -84dB
1 .106 1 .107 1 .108 1 .109 1 .1010
120
100
80
Third Order Distortion [dBc]
Input Frequency
70−
130−
20 log HD 3 f( )( )⋅( )
1010106 f
EECS 247 Lecture 17: Data Converters © 2004 H.K. Page 55
ESD Circuit Distortion• Distortion from ESD circuits approaches state
of-the-art ADC performance!• If you are working on a new, record breaking
ADC, better think about ESD now...• Ref.: A. Wang, "Recent developments in ESD
protection for RF IC," Proc. DAC Conference, Jan. 2003
• Solutions still pre-mature• Lots of company IP