January 28th, 2011Clermont Ferrand,
Paul Scherrer Institute
Plans for the DRS5 Switched Capacitor Array
Stefan Ritt
Stefan Ritt January 28th, 2011Clermont Ferrand,
Agenda
• DRS4 chip has been developed at PSI and has been shown at this Workshop in 2009/2010
• No new chip developments since 2008, but –WaveDREAM board developed at PSI–CAEN VME board–ToF-PET Application under investigation
• New ideas for DRS5 to be designed in 2011–Increased bandwidth–Zero dead time
DRS4Chip
DRS4Chip
Evaluation BoardEvaluation Board
Stefan Ritt January 28th, 2011Clermont Ferrand,
DRS4 Chip
Stefan Ritt January 28th, 2011Clermont Ferrand,
DRS4
• Fabricated in 0.25 m 1P5M MMC process(UMC), 5 x 5 mm2, radiation hard
• 8+1 ch. each 1024 bins,4 ch. 2048, …, 1 ch. 8192
• Passive differential inputs/outputs
• Sampling speed 700 MHz … 5 GHz
• On-chip PLL stabilization• Readout speed
30 MHz, multiplexedor in parallel
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
STOP SHIFT REGISTER
READ SHIFT REGISTER
WSROUT
CONFIG REGISTER
RSRLOAD
DENABLE
WSRIN
DWRITE
DSPEED PLLOUT
DOMINO WAVE CIRCUIT
PLL
AGND
DGND
AVDD
DVDD
DTAPREFCLKPLLLCK A0 A1 A2 A3
EN
AB
LE
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8/MUXOUT
BIASO-OFS
ROFSSROUT
RESETSRCLK
SRIN
F U N C T IO N A L B L O C K D IA G R A M
MUX
WR
ITE
SH
IFT
RE
GIS
TE
R
WR
ITE
CO
NF
IG R
EG
IST
ER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
CHANNEL 8
MUX
LVDS
Stefan Ritt January 28th, 2011Clermont Ferrand,
Bandwidth
Bandwidth is determined by bond wire and internalbus resistance/capacitance:
850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip)
850 MHz (-3dB)
QFP packagefinalbus width
Measurement800 MHz (-3dB)
Evaluation board
THS4508
Stefan Ritt
ROI readout mode
January 28th, 2011Clermont Ferrand,
readout shift register
Triggerstop
normal trigger stop after latency
Delay
delayed trigger stop
Patent pending!
33 MHz
e.g. 100 samples @ 33 MHz 3 us dead time
300,000 events / sec.
e.g. 100 samples @ 33 MHz 3 us dead time
300,000 events / sec.
Stefan Ritt
Daisy-chaining of channels
January 28th, 2011Clermont Ferrand,
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Domino Wave
1
clock
0
1
0
1
0
1
0
enableinput
enableinput
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Domino Wave
1
clock
0
1
0
1
0
1
0
enableinput
enableinput
DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cellsChip daisy-chaining possible to reach virtually unlimited sampling
depth
DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cellsChip daisy-chaining possible to reach virtually unlimited sampling
depth
Stefan Ritt
Simultaneous Write/Read
January 28th, 2011Clermont Ferrand,
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
0
FPGA
0
0
0
0
0
0
0
1 Channel 0
Channel 11
Channel 0 readout
8-foldanalog multi-event
buffer
Channel 21
Channel 10
Expected crosstalk ~few mVExpected crosstalk ~few mV
Stefan Ritt January 28th, 2011Clermont Ferrand,
DRS4 around the world
Shipped (-Jan 2011):2200 Chips120 Evaluation Boards
Shipped (-Jan 2011):2200 Chips120 Evaluation Boards
Stefan Ritt
• MEG experiment @ PSI searches for e decay
• After ~10 years of chip design, DAQ setup, firmware programming, MEG runs with 3000 channels as designed
• 40 ps timing resolutions between all channels, running at 1.6 GS/s
• “Double buffer” readout mode increases life time to 99.7 % at 10 Hz event rate (3 MB/event)
• Took 400 TB in 2010
MEG Status
January 28th, 2011Clermont Ferrand,
Stefan Ritt January 28th, 2011Clermont Ferrand,
Trigger and DAQ on same board
• SCA can only sample a limited (1024-bin window) many application require a wider window, trigger capability would require continuous digitization
• Using a multiplexer in DRS4, input signals can simultaneously digitized at 120 MHz and sampled in the DRS
• FPGA can make local trigger(or global one) and stop DRSupon a trigger
• DRS readout (5 GSPS)though same 8-channel FADCs
an
alo
g fro
nt e
nd
DRSFADC12 bit
65 MHz
MU
X FPGA
trigger
LVDS
SRAM
DRS4
glo
bal tr
igger
bu
s
Stefan Ritt January 28th, 2011Clermont Ferrand,
“Slow” waveform and “Fast” window
Continuous Waveform 120 MSPS (8 ns bins)
Continuous Waveform 120 MSPS (8 ns bins)
TriggeredDRS Waveform 1 GSPS (1 ns bins)up to 5 GSPS
TriggeredDRS Waveform 1 GSPS (1 ns bins)up to 5 GSPS
Window only limited by RAM
Stefan Ritt January 28th, 2011Clermont Ferrand,
WaveDREAM Board
• Empty VME slot costs ~1kE• USB is limited in speed (2.0) and scaling• WaveDREAM board developed at PSI with GBit Ethernet• New board planned
• VGA at input (10 mV – 10 V inputs)• 16 Channels on Eurocard, MMCX connectors• Standalone or cascadable• Serial bus for data, trigger & synchronization• Plug & Play Firmware: TDC, CFD, ADC, Scaler, MCA, …
WaveDREAM(H. Friederich, PSI & ETH)
WaveDREAM(H. Friederich, PSI & ETH)
Pre-amp
Pre-amp
GBitEthernet
VG
A
DRS4
DRS4
ADC
ADC
FPGA
RAM
Eth
Seria
l lin
ks
and
trig
ger
New Board16 chn + serial bus
New Board16 chn + serial bus
Stefan Ritt January 28th, 2011Clermont Ferrand,
Digital Oscilloscope Front-end
Stefan Ritt January 28th, 2011Clermont Ferrand,
Plug & Play Firmware
• Pre-designed modules for CFD, TDC, peak sensing ADC, …• Modules can be configured by user and downloaded over
Ethernet
ChipReadout FIFO
CFD TDC
SCALER FIFO
ADC FIFO
Interface
FIFO
Data bus
Parameter bus
Stefan Ritt January 28th, 2011Clermont Ferrand,
CAEN V1742 Board
• 32+2 Channels 12 bit 5 GS/s Digitizer
• VME64X + optical link• New board design by CAEN in
line with their ADC boards• Firmware support by CAEN• “Early adopter phase” started
2010, official board announcement March 2011
• Desktop version planned
Stefan Ritt January 28th, 2011Clermont Ferrand,
Digital Pulse Processing (DPP)
C. Tintori (CAEN)V. Jordanov et al., NIM A353, 261 (1994)
Stefan Ritt January 28th, 2011Clermont Ferrand,
-n Pulse-shape Discrimination
C. Tintori (CAEN)
Stefan Ritt
DPP Workshop @ PSI
January 28th, 2011Clermont Ferrand,
Stefan Ritt January 28th, 2011Clermont Ferrand,
Time-of-Flight PET
• Conventional electronics:CFD – TDC: 500 ps RMS
• TOF needs:•100-200 ps•>1 MHz rate
• Conventional electronics:CFD – TDC: 500 ps RMS
• TOF needs:•100-200 ps•>1 MHz rate
C. Levin, Stanford University
Stefan Ritt
• Started fall 2010 after NSS/MIC in Knoxville (Siemens PET R&D home)• New project started to replace current PET electronics with DRS4 (5)• PCB ready summer 2011, firmware by Univ. Tübingen• Simulations show that SCA technique can achieve 100 ps easily
ToF-PET Project
January 28th, 2011Clermont Ferrand,
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
1
FPGA
0
0
0
0
0
0
0
Channel 0
Channel 1 ROI
20 samples(10 ns @ 2 GS/s)* 30 ns / sample
= 600 ns+ 40 ns overhead
= 640 ns 1 MHz rate
20 samples(10 ns @ 2 GS/s)* 30 ns / sample
= 600 ns+ 40 ns overhead
= 640 ns 1 MHz rate
“Ping-Pong Scheme”
Stefan Ritt January 28th, 2011Clermont Ferrand,
DRS5 Chip
Stefan Ritt January 28th, 2011Clermont Ferrand,
Plans for DRS5
• Increase analog bandwidth ~5 GHz• Smaller input capacitance
• Increase sampling speed ~10 GS/s• Switch to 180 nm technology
• Deeper sampling depth• 8 x 4096 / chip
• Minimize readout time (“dead time free”) for muSR & ToF-PET
• (minor) reduction in analogreadout speed (30 ns 20 ns)
• Implement FIFO technology
J. Milnes, J. Howoth, Photek
~MHz event rateCTA
SR
Stefan Ritt
• 250 nm process dies out: 1 MPW run / year (UMC)• Pro smaller feature size:
• Faster sampling speed• Faster readout (?)• More sampling cells / area (but: routing/capacitor limitation!)
• Con:• Smaller VDD makes analog design difficult, with 1.2V it is
almost impossible to obtain a 1V linear range• Price: 130 nm 3 x more expensive
Why 180nm ?
January 28th, 2011Clermont Ferrand,
Compromise: 180 nmCompromise: 180 nm
Stefan Ritt January 28th, 2011Clermont Ferrand,
Next Generation SCA
• Low parasitic input capacitance High bandwidth
• Large area low resistance bus, lowresistance analog switches high bandwidth
Short sampling depth
• Digitize long waveforms
• Accommodate long trigger delay
• Faster sampling speed for a given trigger latency
Deep sampling depth
How to combinebest of both worlds?
How to combinebest of both worlds?
Stefan Ritt January 28th, 2011Clermont Ferrand,
Cascaded Switched Capacitor Arrays
shift registerinput
fast sampling stage secondary sampling stage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• 32 fast sampling cells (10 GSPS/180nm CMOS)
• 100 ps sample time, 3.1 ns hold time
• Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz)
• Shift register gets clocked by inverter chain from fast sampling stage
• 32 fast sampling cells (10 GSPS/180nm CMOS)
• 100 ps sample time, 3.1 ns hold time
• Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz)
• Shift register gets clocked by inverter chain from fast sampling stage
Stefan Ritt January 28th, 2011Clermont Ferrand,
Typical Waveform
Only short segments of waveform need high speed readoutOnly short segments of waveform need high speed readout
Stefan Ritt January 28th, 2011Clermont Ferrand,
Dead-time free acquisition
• Self-trigger writing of short 32-bin segments
• Simultaneous reading ofsegments
• Quasi dead time-free• Data driven readout
• Ext. ADC runs continuously• ASIC tells FPGA when there is new data
• Coarse timing from300 MHz counter
• Fine timing by waveformdigitizing and analysis in FPGA
• 20 * 20 ns = 0.4 s readout time 2 MHz sustained event rate
• Attractive replacement for CFD+TDC
coun
ter
latc
hla
tch
latc
hwrite
pointer
readpointer
digital readout
analog readout
trigger
FPGA
Stefan Ritt January 28th, 2011Clermont Ferrand,
Conclusions
• DRS4 chip successfully used in many areas, true potential of SCA technology is just now discovered
• Planned DRS5 chip will increase BW and decrease readout dead time
• SCA technology should be able to replace most traditional electronics in particle detection