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Stefan Ritt, PSIG-APD Workshop, GSI, Traditional Front-End Electronics Time is measured with Discriminator/TDC Energy is measured with gated charge-ADC TDC Amplifier Shaper DiscriminatorMeasure Time Moving average baseline hits G-APD ADC Measure Amplitude/Charge What about pile-up?
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Front-End Electronics for G-APDs
Stefan RittPaul Scherrer Institute, Switzerland
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 2
Traditional Front-End Electronics
• Time is measured with Discriminator/TDC• Energy is measured with gated charge-ADC
TDC
AmplifierShaper DiscriminatorMeasure Time
Moving average baseline
hit
sG-APD
ADC
Measure Amplitude/Charge
What aboutpile-up?
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 3
Flash ADC Technique
60 MHz12 bit
PreamplifierG-APD Shaper
• Shaper is used to optimize signals for “slow” 60 MHz FADC• Shaping stage can only remove information from the signal• Shaping would be unnecessary if FADC would be fast enough
FADC
5 GHz12 bit
TransimpedancePreamplifierG-APD FADC
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 4
How to measure best timing?Simulation of MCP with realistic noise and different discriminators
J.-F. Genat et al., arXiv:0810.5590 (2008)
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 5
Switched Capacitor Array Principle
Shift RegisterClock
IN
Out
“Time stretcher” GHz MHz
Waveform stored
Inverter “Domino” ring chain0.2-2 ns
FADC 33 MHz
Keep Domino wave running in a circular fashion and stop by trigger Domino Ring Sampler (DRS)
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 6
Switched Capacitor Array
•Cons• No continuous acquisition• Calibration for precise timing• External (commercial) FADC needed
•Pros• High speed (~5 GHz) high resolution (~12 bit equiv.)
• High channel density (8 channels on 5x5 mm2)• Low power (30 mW / channel)• Low cost (~ 10 € / channel chip only)
t t t t t
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 7
DRS4 Chip• Fabricated in 0.25 m
1P5M MMC process(UMC), 5 x 5 mm2, radiation hard
• 8+1 ch. each 1024 cells
• Differential inputs,differential outputs
• Sampling speed 1 GSPS … 6 GSPS,PLL stabilized
• Readout speed 30 MHz, multiplexedor in parallel
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
STOP SHIFT REGISTER
READ SHIFT REGISTER
WSROUT
CONFIG REGISTER
RSRLOAD
DENABLE
W SRIN
DW RITE
DSPEED PLLOUT
DOMINO WAVE CIRCUIT
PLL
AGND
DGND
AVDD
DVDD
DTAPREFCLKPLLLCK A0 A1 A2 A3
EN
AB
LE
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8/MUXOUT
BIASO-O FS
ROFSSROUT
RESETSRCLK
SRIN
F U N C T IO N A L B L O C K D IA G R A M
MUX
WR
ITE
SH
IFT
RE
GIS
TER
WR
ITE
CO
NFI
G R
EG
ISTE
R
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
CHANNEL 8
M UX
LVDS
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 8
~12 bit resolution at 5 GSPSW
AVEF
OR
M [V
]
TIME [ns]0 20 40 60 80 100 120 140 160 180 200
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
11.5 bits effective resolution <8 bits effective resolution
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 9
Random Jitter Results• Sine curve frequency fitted
for each measurement (PLL jitter compensation (~25ps) )
• Encouraging result for DRS3:2.7 ps RMS (best channel)3.9 ps RMS (worst channel)phase error in fitting sine wave
• Differential measurement t1 – t2 adds a 2, needs to be verified by measurement
• Measurement of n points on a rising edge of a signal improves by n
Measurements for DRS4 currently going on, expected to be slightly better
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 10
Simultaneous Write/Read
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
0
FPGA
0000000
1 Channel 0
Channel 11Channel 0 readout
8-foldanalog multi-event
buffer
Channel 21Channel 10
Expected additional crosstalk ~few mV
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 11
Comparison with other chipsMATACQ D. Breton
LABRADORG. Varner
DRS4S. Ritt
Bandwidth (-3db) 300 MHz > 1000 MHz 950 MHzSampling frequency
1 or 2 GHz 10 MHz … 3.5 GHz
1 GHz … 5 GHz
Full scale range ±0.5 V +0.4 …2.1 V ±0.5 VEffective #bits 12 bit 10 bit 12 bitSample points 1 x 2520 9 x 256 8 x 1024Channel per board
4 N/A 32
Digitization 5 MHz N/A 30 MHzReadout dead time
650 s 150 s 3 s – 370 s
Integral nonlinearity
± 0.1 % ± 0.1 % ± 0.05%
Radiation hard No No Yes (chip)Commercial Board
V1729 (CAEN)
- planned (CAEN)
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 12
DRS Boards32
cha
nnel
s inp
ut
General purpose VPC board built at PSI
USB evaluation board
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 13
Experiments using DRS chipMAGIC-II 400 channels DRS2MEG 3000 channels DRS2
BPM for XFEL@PSI1000 channels DRS4 (planned)
MACE (India) 400 channels DRS4 (planned)
Waveform AnalysisWhat can we learn from acquired waveforms?
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 15
On-line waveform display
click
templatefit
pedestalhisto
848PMTs
“virtual oscilloscope”
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 16
QT Algorithm
originalwaveform
smoothed anddifferentiated (Difference Of
Samples)Threshold in DOS
Region for pedestal
evaluation
integration area
t• Inspired by H1 Fast Track Trigger (A.
Schnöning, Desy & ETH)• Difference of Samples (= 1st derivation)• Hit region defined when DOS is above
threshold• Integration of original signal in hit region• Pedestal evaluated in region before hit• Time interpolated using maximum value
and two neighbor values in LUT 100ps resolution for 1ns sampling time
Can be implemented in FPGA
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 17
Pulse shape discrimination
)tt[...]θ.. )tθ(td)/τt(te
/τ)t(te i/τ)t(teAV(t) r00
000
CsB
Leading edge Decay time AC-coupling Reflections
Example: / source in liquid xenon detector (or: /p in air shower)
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 18
-distribution
= 21 ns = 34 ns
Waveforms can be clearly
distinguished
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 19
Coherent noise
i Vi (t)All PMTs
Pedestal average
Charge integration
• Found some coherent low frequency (~MHz) noise
• Energy resolution dramatically improved by properly subtracting the sinusoidal background
• Usage of “dead” channels for baseline estimationImportant in low signal applications such as RICH
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 20
Pileup recognition
original
derivativet = 15ns
E1 E2
T 8ns
T 10ns
T 15ns
T 50ns
T 100ns
211EE
E
MC simulation
Rule of thumb: Pileup can be detected if T ~ rise-time of signals
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 21
Template Fit• Determine “standard” PMT pulse by
averaging over many events “Template”• Find hit in waveform• Shift (“TDC”) and scale (“ADC”)
template to hit• Minimize 2
• Compare fit with waveform• Repeat if above threshold
• Store ADC & TDC values
Experiment500 MHz sampling
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 22
Conclusions• Switched Capacitor Array techniques has prospects to trigger a
quantum step in data acquisition for G-APDs• The DRS chip has been designed with maximum flexibility and can
therefore be used in many applications• Collaboration on a scientific basis is very welcome, chips and
evaluation board available from PSI on a non-profit basis
http://drs.web.psi.ch
Datasheets, publications:
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 23
Backup Slides
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 25
BandwidthBandwidth is determined by bond wire and internalbus resistance/capacitance:
850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip)
finalbus width
Simulation
850 MHz (-3dB)
QFP package
Measurement
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 26
ROI readout mode
readout shift register
Triggerstop
normal trigger stop after latency
Delay
delayed trigger stop
Patent pending!
33 MHz
e.g. 100 samples @ 33 MHz 3 us dead time
(2.5 ns / sample @ 12 channels)
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 27
Daisy-chaining of channels
Channel 0 – 1024 cells
Channel 1 – 1024 cells
Channel 2 – 1024 cells
Channel 3 – 1024 cells
Channel 4 – 1024 cells
Channel 5 – 1024 cells
Channel 6 – 1024 cells
Channel 7 – 1024 cells
Domino Wave Generation
DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 28
Interleaved samplingde
lays
(200
ps/8
= 2
5ps)
G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)
5 GSPS * 8 = 40 GSPS
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 29
Trigger an DAQ on same board
• Using a multiplexer in DRS4, input signals can simultaneously digitized at 65 MHz and sampled in the DRS
• FPGA can make local trigger(or global one) and stop DRSupon a trigger
• DRS readout (5 GHz samples)though same 8-channel FADCs
analog front end
DRSFADC12 bit
65 MHzM
UX FPGA
trigger
LVDS
SRAM
DRS4
glob
al tr
igge
r bus
“Free” local trigger capability without additional hardware
Stefan Ritt, PSI G-APD Workshop, GSI, 9.2.09 30
Datasheet