Proceedings of Asia-Pacific Microwave Conference 2007

Wireless Interconnect by Slotted Ground PlaneHiroshi YAMAGUCHIt, Hiroyuki ARAIt, Kohei MORI+, Akihiko OKUBORA

tFaculty of Engineering, Yokohama National University79-5 Tokiwadai, Hodogayaku, Yokohama-shi, Kanagawa, 240-8501, Japan

Phone: +81-45-339-4270, Email: hiroshi@arailab.dnj.ynu.ac.jpSemiconductor Business Group, Sony Corporation4-14-1 Asahi-cho, Atsugi-shi 243-0014, Japan

Abstract-This paper proposes a novel method for wirelessinterconnect in three-dimensional (3D) multiple packaging of largescale integrated circuits (LSI). This interconnect consists of micro-strip-line (MSL) on a silicon substrate and slot on a ground plane.A coupling by stacked slots provides the wireless interconnect. Theproposed method provides a use of large sized ground plane whichreduces the interference from other wireless system and the effectby noise. The simulation and experiment demonstrate the novelwireless interconnect.

Index Terms-Wide bandwidth, Wireless interconnect, S-parameter, Coupling, Crosstalk, MSL, Slot

I. INTRODUCTION

The performance of LSI has mainly depends on deviceproperties. In order to enhance circuit and system performance,the major effort has been focused on improving the devicespeed through down scaling of device feature dimension andincrease of operation frequency.

Metal wiring method has been adopted for traditional in-terconnect technology. The decrease in physical dimension ofhard-wired metal interconnects degrades circuit and systemperformance seriously, especially at high operating frequencies,due to a deterioration of interconnect resistance, capacitance,inductance and bit-rate capacity. The parasitic capacitance andinductance also increase the time delay. Signal attenuation anddispersion in wire resulted from down scaling give a rise todegraded bit-error capacity. Other issues are power loss andcrosstalk between wires.

To overcome these problems in interconnect caused by down-scaling of device feature dimension, a great amount of work hasbeen focused on improving the interconnect performance byreducing the interconnect resistivity or lowering the dielectricconstant of the interlayer material. However, these approacheswill encounter the fundamental material limit sooner or later,and no solution exists currently. Therefore, to conquer theobstacle in the evolution of deep submicron ultra large scaleintegration(ULSI) technology, revolutionary approaches mustbe pursued.

It is a promising technology to use wireless interconnectsbecause they are compatible with the 3D multiple packaged LSIfor low-cost system production and low power consumption. Inorder to realize wireless interconnects in 3D multiple packagingof LSI, two methods have been demonstrated. One is an on-chipinductor which interconnects a few chips in a short distance

by using inductive coupling [1]. The other is a dipole antennawhich transmits signals to whole chips in LSI package [2].

This paper proposes the novel method to realize 3D wirelessinterconnection. In this approach, we use a coupling by slotson ground of integrated silicon chips as shown in Fig. 1.This structure has some advantages comparing to conventionalmethods described above. For instance, the use of large groundplane gives electrical shield and provides the communicationwith very small interference by signals in other communicationsystems and noise. Our goal is to realize inter-chip wirelessconnection with large bandwidth and low losses.

This paper is organized as follows. First, we investigate sev-eral parameters in the slot geometry to increase its bandwidthfor ultra wideband (UWB) inter-chip communication. Second,we verify wide band coupling characteristics between slots bya basic analysis model and measurement. Third, we investigatethe interconnect among silicon chips and show possibility ofinterconnecting several chips(260[pm] thickness) using high-resistivity(2290[Qcm]) silicon at 20[GHz] in more practicalsimulation. Finally, we conclude in Section V.

Fig. 1. Structure of 3D wireless interconnect

1-4244-0749-4/07/$20.00 w2007 IEEE.

II. FUNDAMENTAL SIMULATIONS

We calculate the transmission characteristics of the slot cou-pling with HFSS. Fig. 2 shows the geometry of a two-elementmodel. The substrate terminates with absorbing boundary toassume an infinite ground plane. The fixed parameters of thismodel are length of the MSL 20[mm], thickness of the dielectricsubstrate 0.8[mm], and relative dielectric constant 2.6, to havea resonance about 2 to 3[GHz]. We consider to use UWBcommunication, because of higher-speed signal transmissionand low power consumption. In this model, we try to increase-3dB relative bandwidth of S21 by changing a slot size "a"and "b" and the space between upper and lower substrate "h".Fig. 3 shows frequency characteristics of S-parameters. S21 is-0.06[dB] at 2.73[GHz] with relative bandwidth of 75.5[%] fora = 13[mm], b = 9[mm], and h = 0.8[mm].

Next, we discuss a four-element model as shown in Fig. 4 tosimulate large number of coupling ports. In this model, S21 isequal to S43, and S41 to S23 by the symmetry of the model.We expand the bandwidth of S21 as well as described aboveand to reduce S41. Fig. 6 shows frequency characteristics ofS-parameters. It shows that we can suppress S41 less than -30[dB] for the distance of adjoined element d being more than0.3Ag without decreasing the bandwidth of S21.

TABLE ISIMULATION ELEMENTS

Adaptive Pass 10Max delta s 0.001

Interpolating Error tolerance 0.1 [%]sweep Max solutions 40Port Lumped gap sourceDielectric Rel.permittivity 2.material Resistivity Io

(5.5)

b(9.0)

(5.5)

,20-'-

-30 -------

~.-40Sii

-50

60( 1 2 3 4Frequency [GHz]

Fig. 3. Characteristic of S-parameter

II11J. L III41111$~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~iwzi.. .llllltlllllrllllrllllrllllllg~~~~.

!i XX XX_____s X;_____;;____ ;;_____;; ;;; ;;_____;

Fig. 4. Image of four-element model

unit: [-Xg](Xg=75 [mm])

Fig. 5. Structure of four-element model

0 100

-10

fo -2

C/o -3 0

Fig. 2. Structure of two-element model-40

80

60

40 -

20m

-20

-50 0;

~

0.1 0.2 0.3 0.4 0.5 0.6Distance d;Llg

Fig. 6. Coupling and isolation dependence on distance

z

xunit: [mm]

III. MEASUREMENT

As a preparation for measurement, we first carry out sim-ulations of the effect of finite sized substrate. We change thesubstrate length in the x direction ("xg" in Fig. 5) and use amodel with infinite ground plane. Fig. 7 shows effects of thelength xg for frequency characteristics. S21 drops at 1.9[GHz](Xg = 0.8Ag), 1.4[GHz] and 2.8[GHz] (xg = l.OAg). At the samefrequencies, S41 increase by about 20[dB]. These frequenciesdepend on xg. They are assumed to be caused by a resonanceof ground plane. Fig. 7 also shows that the infinite substratemakes no losses of S21. We may assume that the losses do notoccur if the substrate length in the x direction is large enoughcomparing with the size of the slot element.We may assume no losses particularly in the pass band (about

1.7[GHz] to 2.8[GHz]) for the fabricated model. Fig. 8 showsthe four-element model design. Because a connector size islarger than the substrate thickness, connectors of port 2 and4 are attached in the other side of substrate. The other fourports are open ends, because the coupling by the slot is verystrong to neglect radiation from the open ends. Fig. 10 showsmeasurement result by vector network analyzer. There are somedifferences between the simulation result and the measurement.Frequency characteristics of permittivity and dielectric losses ofthe substrate are assumed to be the error factors. We assume theeffects of connectors increasing the cross talk of S41, however,we confirm that large coupling by slots does not cause crosstalk in this model.

0.12

0.03

0.12

0.13. 0.27 0.20 0.27 .0.13,

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0.25 0.03 0.44 0.03 0.25!

1.u

).27

unit: [ Xg](Xg=75[mm])

I ot A

pOM --

0.01j1gz 0.01$

y

x

Fig. 8. Structure of fabricated model

1 2 3 4Frequency [GHz]

- - xg=finite (0.8kg)-------- xg=finite (l.OXg)

xg=infinite

Fig. 7. S-parameter depending on length of ground plane

Fig. 9. Fabricated model

2 3 4Frequency [GHz]

Fig. 10. Measurement and Calculated S-parameter

0

-10

z -20

C -30ct,-- -40

C -50

-60 IL

0

IV. SIMULATION WITH SILICON CHIPS

Fig. 11 shows the model designed to resonate at 20[GHz]using high-resistivity silicon for the dielectric material. Thesimulation model in Fig. 12(a) has space between chips filledwith silicon, while a multilayer structure in Fig. 12(b) isa stack of same substrate of thickness 0.26[mm] with thecoupling slot. We investigate the relationship between the chipspacing h and S21 at the resonate frequency. The referencedata is the coupling between dipole embedded in the samesubstrate as shown in Fig. 13 in ref. [2]. Fig. 14 shows that thecoupling coefficient S21 between slots and between dipoles.The slot coupling provides larger coupling than that of dipolesfor the small chip spacing less than 1 [mm]. The data of thedipole antenna are given in ref. [2]. Fig. 14 shows the verticalconnection by the proposed model is very strong for thin chipspacing. On the other hand, inductor model in ref. [1] is usedbetween very thin chip spacing about 25[[pm] to 300[pm]. Theslot coupling provides larger communication distance than thatof the inductor.

TABLE IISIMULATION ELEMENTS

Dielec. material SiRel. Permittivity 12Resistivity 2.29 [kQ-cm]

4/[mm]S 11111

h .. v i

Fig. 13. Structure of the model using dipole antenna (Ref. [2])

0

-20 ------

-40 -

-60dipole

-60 _ (Ref. [2])-o--- model 1

-80 model 2-80

0 0.5 1 1.5 2 2.5 3Spacing h [mm]

Fig. 14. S21 dependence on communication distance

top: 0.39t

0.26 0.26

y ____..

0.18 0.03 0.18

x

bottom:0.39

0.07

0.12

0.07

*0.11 0.17 * 0.11.unit: [-Xg]

Fig. 11. Structure of proposed model at 20[GHz]

V. CONCLUSION

This paper proposed a novel method using coupling slotson ground of integrated silicon chips to realize 3D wirelessinterconnection. We obtained a novel model layout with largebandwidth 75.5[%], low losses -0.06[dB] and low crosstalksless than -30[dB]. Measurements verified the interconnect usingcoupling slot on ground. Simulation results on silicon chips at20[GHz] showed the possibility of wireless interconnect amongseveral silicon chips (five chips with 0.26[mm] thickness siliconchips) for 3D multiple packaging of LSI.

REFERENCES

[1] N. Miura, D. Mizoguchi, T. Sakurai, and T. Kuroda, "Analysis and Designof Inductive Coupling and Transceiver Circuit for Inductive Inter-ChipWireless Superconnect," IEEE JOURNAL OF SOLID-STATE CIRCUITS,vol.40, no. 4, pp. 829-837, April 2005.

[2] K. Kimoto, M. Nitta, N. Sasaki, and T. Kikkawa, "On-Chip WirelessSignal Transmission using Silicon Integrated Antennas," hiroshima univ.COE, pp. 140-143, January 2007.

[3] Zhi. Ming Chen, YP.Zhang, "Inter-Chip Wireless Communication Chan-nel: Measurement, Characterization, and Modeling," IEEE Trans. Anten-nas and Propagation, vol.55, no. 3, pp. 978, March 2007.

1.9[rnm] 1. 9[min](a)model I (b)rnodel 2

Fig. 12. Structure of 3D multiple stacked silicon chips