Q1
BC107BP
R11kΩ
R2
1kΩ
R31kΩ
V10.5 V
VCC5V
XMM1
1
VCC
3
0
4
0
0
2
CAD LAB (EEC-653)
EXPERIMENT NO. 1
OBJECT:- Transient analysis of BJT Inverter using step input.
APPARATUS REQUIRED:- Multisim v.10.0.
THEORY:-
A BJT inverter is a simple CE switch as shown in Figure 1 (a). When the input voltage Vi is LOW, the output voltage is VO is HIGH and
vice-versa. Its voltage transfer characteristics are such as shown in Figure 1 (b). The noise margins NM can be determined from the transfer characteristics as follows: NMH=VOH – VIH ,(Volts)
NML=VIL – VOL ,(Volts)
The higher noise margins, the higher are the immunity of the logic gate to unwanted signals(noise).
CIRCUIT DIAGRAM:-
1TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
Figure 1 : The BJT inverter and its transfer characteristics
OBSERVATIONS:-
Vin (Input Voltage in Volts)
Vout (Output Voltage in Volts)
0 V 5 V0.5 V 4.996 V1.0 V 4.616 V1.5 V 4.141 V2.0 V 3.656 V2.5 V 3.168 V3.0 V 2.679 V3.5 V 2.616 V4.0 V 2.770 V4.5 V 2.931 V5.0 V 3.094 V
RESULT:- Study of transient analysis of BJT Inverter using step input has been done.
2TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
EXPERIMENT NO.02
OBJECT:- Transient analysis of BJT Inverter using NPN Transistor.
APPARATUS REQUIRED:- Multisim v.10.0.
THEORY:-
In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. This represents perfect switching behavior, which is the defining assumption in Digital electronics. In practice, actual devices have electrical characteristics that must be carefully considered when designing inverters. In fact, the non-ideal transition region behavior of a CMOS inverter makes it useful in analog electronics as a class A amplifier (e.g., as the output stage of an operational amplifier . Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see Binary). An inverter circuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include (0, +5V) for TTL circuits.
3TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
CIRCUIT DIAGRAM:-
Q1BC107BP
Q2
BC107BP
Q3
BC107BP
Q4
BC107BP
LED1D11N4007
D21N4007
VCC5V
V10 V
R14kΩ
R21.8kΩ
R3130Ω
R4
100Ω
R51kΩ
1
2
4
3
6
70
0
8
5
0
9
10
VCC
OBSERVATIONS:-
Input (A) Output (Y)L HH L
4TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
RESULT:- Study of transient analysis of BJT Inverter using NPN Transistor has been done.
EXPERIMENT NO.03
OBJECT:- Transient Analysis of NMOS inverter using step input.
APPARATUS REQUIRED:- Multisim v.10.0
THEORY:-
For any IC technology used in digital circuit design, the basic circuit element is the logic inverter.Once the operation and characterization of an inverter circuit sare thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.
N-type metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. NMOS transistors have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called active), and velocity saturation.
The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the
5TEENA SHARMA (ECE-3rd YEAR) 0925231049
Q1
MTD4N20E
C120pF
R110kΩ
VDD10V
V13.3 V
VDD
0
0
0
2
XMM1
1
0
CAD LAB (EEC-653)
positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.
CIRCUIT DIAGRAM:-
OBSERVATIONS:-
Sr.no. Input(V1) in volts Output(Vo) in volts1. 0 V 9.99 V2. 1 V 9.991 V
6TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
3. 2 V 9.992 V4. 3 V 9.993 V5. 4 V 1.876mV6. 5 V 936.64uV
RESULT:- Study of transient Analysis of NMOS inverter using step input has been done.
EXPERIMENT NO.04
OBJECT:- Transient Analysis of NMOS inverter using pulse input.
APPARATUS REQUIRED:- Multisim v.10.0.
THEORY:-
For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. Once the operation and characterization of an inverter circuit thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.
N-type metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. NMOS transistors have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called active), and velocity saturation.
7TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.
CIRCUIT DIAGRAM:-
Q1
MTD4N20E
R110kΩ
VDD10V
VDDXSC1
A B
Ext Trig+
+
_
_ + _
0 0
0C120pF
1
0
XFG1Agilent
0
2
OBSERVATIONS:-
8TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
Result:- Study of Transient Analysis of NMOS inverter using pulse input has been done.
EXPERIMENT NO.05
OBJECT:- Transient Analysis of CMOS inverter using step input.
APPARATUS REQUIRED:- Multisim v.10.0.
THEORY:-
An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this 'resistive-drain' approach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows through the resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption and processing speed. Alternatively, inverters can be constructed using two complementary transistors in a CMOS configuration. This configuration greatly reduces power consumption since one of the transistors is always off in both
9TEENA SHARMA (ECE-3rd YEAR) 0925231049
Q1
MTD4N20E
Q2
2N6804
R11kΩ
VCC10V
V15 V
2
VCC
3
00
XMM1
10
CAD LAB (EEC-653)
logic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-only or PMOS-only type devices. Inverters can also be constructed with Bipolar Junction Transistors (BJT) in either a resistor-transistor logic (RTL) or a transistor-transistor logic (TTL) configuration.
Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see Binary). An inverter circuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include (0, +5V) for TTL circuits.
CIRCUIT DIAGRAM:-
OBSERVATIONS:-
10TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
Input (V1) in volts Output (Vo) in volts
0 V 9.99 V1 V 9.991 V2 V 9.992 V3 V 9.993 V4 V 1.876mV5 V 936.64uV
RESULT:- Study of transient Analysis of CMOS inverter using step input has been done.
EXPERIMENT NO.06
OBJECT:- Transient Analysis of CMOS inverter using pulse input.
APPARATUS REQUIRED:- Multisim v.10.0.
THEORY:-
An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this 'resistive-drain' approach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows through the resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption and processing speed. Alternatively, inverters can be constructed using two complementary
11TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
transistors in a CMOS configuration. This configuration greatly reduces power consumption since one of the transistors is always off in both logic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-only or PMOS-only type devices. Inverters can also be constructed with Bipolar Junction Transistors (BJT) in either a resistor-transistor logic (RTL) or a transistor-transistor logic (TTL) configuration.
Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see Binary). An inverter circuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include (0, +5V) for TTL circuits.
CIRCUIT DIAGRAM:-
Q1
MTD4N20E
XSC1
A B
Ext Trig+
+
_
_ + _
0 0
0
Q2
2N68041
R11kΩ
2
VCC10V
VCC
XFG1Agilent
0
3
OBSERVATIONS:-
12TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
RESULT:- Study of Transient Analysis of CMOS inverter using pulse input has been done.
EXPERIMENT NO.07
OBJECT:- Transient & D.C. Analysis of NOR gate using n-p-n transistor.
APPARATUS REQUIRED:- Multisim V.10.0.
THEORY:-
The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. NOR is a functionally complete operation—combinations of NOR gates can be combined to generate any other logical function. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not vice versa.
13TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
In most, but not all, circuit implementations, the negation comes for free—including CMOS and TTL. In such logic families, OR is the more complicated operation; it may use a NOR followed by a NOT. A significant exception is some forms of the domino logic family.
The original Apollo Guidance Computer used 4,100 ICs, each one containing only a single 3-input NOR gate.
CIRCUIT DIAGRAM:-
14TEENA SHARMA (ECE-3rd YEAR) 0925231049
Q1
BC107BPV15 V
V25 V
VCC5V
LED1
R1
4.7kΩ
R2100Ω
R3
4.7kΩ
R4
100Ω
R5100kΩ
VCC
21 0
0
0
3
4
5
0
CAD LAB (EEC-653)
OBSERVATIONS:-
INPUT (A) INPUT (B) OUTPUT (Y)L L HL H LH L LH H L
RESULT:- Study of transient & D.C. Analysis of NOR gate using n-p-n transistor has been done.
EXPERIMENT NO.08
OBJECT:- Transient &D.C. analysis of NAND Gate using NPN transistor.
APPARATUS REQUIRED:- Multisim V.10.0.
THEORY:-
The Negated AND, NOT AND or NAND gate is the opposite of the digital AND gate, and behaves in a manner that corresponds to the opposite of AND gate, as shown in the truth table on the right. A LOW (0) output results only if both the inputs to the gate are HIGH (1); if one or both inputs are LOW (0), a HIGH (1) output results.
The NAND gate is significant because any boolean function can be implemented by using a combination of NAND gates. This property is called functional completeness.
15TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
Digital systems employing certain logic circuits take advantage of NAND's functional completeness. In complicated logical expressions, normally written in terms of other logic functions such as AND, OR, and NOT, writing these in terms of NAND saves on cost, because implementing such circuits using NAND gate yields a more compact result than the alternatives[1] .
NAND gates can also be made with more than two inputs, yielding an output of LOW if all of the inputs are HIGH, and an output of HIGH if any of the inputs is LOW. These kinds of gates therefore operate as n-ary operators instead of a simple binary operator. Algebraically, these can be expressed as the function NAND(a, b, ..., n), which is logically equivalent to NOT(a AND b AND ... AND n).
CIRCUIT DIAGRAM:-
Q1
BC107BP
Q2
BC107BP
R1
10kΩ
R2
10kΩ
R34.7Ω
R4
600Ω
VCC5V
V15 V
V20 V
LED1
1
2
3
0
VCC
45
0
6
7
0
0
16TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
OBSERVATIONS:-
Input (A) Input (B) Output (Y)L L HL H HH L HH H L
RESULT:- Study of Transient &D.C. analysis of NAND Gate using n-p-n transistor has been done.
EXPERIMENT NO.09
OBJECT:- To implement FULL ADDER using VHDL.
APPARATUS REQUIRED:- VHDL Software.
BLOCK DIAGRAM:-
17TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
TRUTH TABLE:-
a b Cin S(sum) Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
VHDL CODE:-
LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY full_adder ISPORT(x: IN std_logic ;y: IN std_logic ;cin: IN std_logic ;cout: OUT std_logic ;sum: OUT std_logic) ;
18TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
END full_adder ;ARCHITECTURE equations OF full_adder ISBEGINsum <= x XOR y XOR cin ;cout <= (x AND y) OR (x AND cin) OR (y AND cin) ;END ;
RTL SCHEMATIC:-
SIMULATION WAVEFORMS:-
19TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
RESULT:- Implementation of FULL ADDER using VHDL has been done.
EXPERIMENT NO.10
20TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
OBJECT:- To implement FULL SUBTRACTOR using VHDL.
APPARATUS REQUIRED:- VHDL Software.
BLOCK DIAGRAM:-
TRUTH TABLE:-
a b Cin diff bout0 0 0 0 00 0 1 1 10 1 0 1 10 1 1 0 11 0 0 1 01 0 1 0 01 1 0 0 01 1 1 1 1
VHDL CODE:-
21TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
library IEEE; library IEEE.STD_LOGIC_1164.ALL; entity FULL SUBTRACTOR is port ( a: in STD_LOGIC, b: in STD_LOGIC, bin: in STD_LOGIC; bout: out STD_LOGIC, diff: out STD_LOGIC); end FULL SUBTRACTOR; architecture behavior of FULL SUBTRACTOR is begin P9: process (a, b, bin) variable temp1, temp2, temp3, temp4, temp5: STD_LOGIC;
begin
temp1 := not a; temp2 := a xor b; temp3 := temp1 and b; temp4 := temp1 and bin; temp5 := b and bin; bout <= temp3 or temp4 or temp5; diff <= temp2 xor bin; end process P9; end behaviour;
22TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
RTL SCHEMATIC:-
SIMULATION WAVEFORMS:-
RESULT:- Implementation of FULL SUBTRACTOR using VHDL has been done.
EXPERIMENT NO.11
23TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
OBJECT:- To implement 8*1 MULTIPLEXER using VHDL.
APPARATUS REQUIRED:- VHDL Software.
BLOCK DIAGRAM:-
TRUTH TABLE:-
S2 S1 S0 Z
0 0 0 70 0 1 60 1 0 50 1 1 41 0 0 31 0 1 21 1 0 11 1 1 0
VHDL CODE:-
24TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux8x1 isPort (i : in std_logic_vector(7 downto 0);s : in std_logic_vector (2 downto 0);y : out std_logic);end mux8x1;architecture Behavioral of mux8x1 isbeginprocess (i,s)beginif (s = "000") then y <= i(0);elsif (s = "001") then y <= i(1);elsif (s = "010") then y <= i(2);elsif (s = "011") then y <= i(3);elsif (s = "100") then y <= i(4);elsif (s = "101") then y <= i(5);elsif (s = "110") then y <= i(6);else y <= i(7);end if;end process;end Behavioral;
25TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
RTL SCHEMATIC:-
SIMULATION WAVEFORMS:-
RESULT:- Implementation of 8*1 MULTIPLEXER using VHDL has been done.
26TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
EXPERIMENT NO.12
OBJECT:- To implement 2*4 DECODER using VHDL.
APPARATUS REQUIRED:- VHDL Software.
BLOCK DIAGRAM:-
TRUTH TABLE:-
A(1) A(0) D(3) D(2) D(1) D(0)0 0 0 0 0 10 1 0 0 1 01 0 0 1 0 01 1 1 0 0 0
27TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
VHDL CODE:-
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity decoder2x4 is
port (sel: in std_logic_vector (1 downto 0);e: in std_logic;y: out std_logic_vector (3 downto 0));end decoder2x4;architecture Behavioral of decoder2x4 isbeginprocess(e,sel)beginif(e='0') thenif(sel = "00") theny <= "0111" ;elsif(sel = "01") theny <= "1011" ;elsif(sel = "10") theny <= "1101" ;elsey <= "1110" ;end if;elsey <= "1111";end if;end process;end Behavioral;
28TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
RTL SCHEMATIC:-
29TEENA SHARMA (ECE-3rd YEAR) 0925231049
CAD LAB (EEC-653)
SIMULATION WAVEFORMS:-
RESULT:- Implementation of 2*4 DECODER using VHDL has been done.
30TEENA SHARMA (ECE-3rd YEAR) 0925231049
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