Cad File of Teena

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CAD LAB (EEC-653)

EXPERIMENT NO. 1

OBJECT:- Transient analysis of BJT Inverter using step input. APPARATUS REQUIRED:- Multisim v.10.0. THEORY:A BJT inverter is a simple CE switch as shown in Figure 1 (a). When the input voltage Vi is LOW, the output voltage is VO is HIGH and vice-versa. Its voltage transfer characteristics are such as shown in Figure 1 (b). The noise margins NM can be determined from the transfer characteristics as follows: NMH=VOH VIH ,(Volts) NML=VIL VOL ,(Volts) The higher noise margins, the higher are the immunity of the logic gate to unwanted signals(noise).

CIRCUIT DIAGRAM:VCC 5V VCC R1 1k XMM1

2 Q1 4 R2 1 BC107BP 3 R3 1k 0 V1 1k 0.5 V 0 0

Figure 1 : The BJT inverter and its transfer characteristics1

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

OBSERVATIONS:Vin (Input Voltage in Volts) 0V 0.5 V 1.0 V 1.5 V 2.0 V 2.5 V 3.0 V 3.5 V 4.0 V 4.5 V 5.0 V Vout (Output Voltage in Volts) 5V 4.996 V 4.616 V 4.141 V 3.656 V 3.168 V 2.679 V 2.616 V 2.770 V 2.931 V 3.094 V

RESULT:- Study of transient analysis of BJT Inverter using step inputhas been done.

2

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

EXPERIMENT NO.02

OBJECT:- Transient analysis of BJT Inverter using NPN Transistor. APPARATUS REQUIRED:- Multisim v.10.0. THEORY:In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. This represents perfect switching behavior, which is the defining assumption in Digital electronics. In practice, actual devices have electrical characteristics that must be carefully considered when designing inverters. In fact, the non-ideal transition region behavior of a CMOS inverter makes it useful in analog electronics as a class A amplifier (e.g., as the output stage of an operational amplifier . Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see Binary). An inverter circuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include (0, +5V) for TTL circuits.

3

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

CIRCUIT DIAGRAM:VCC VCC 5V R3 130 R1 4k 2 9 Q1 BC107BP V1 0V 0 D2 1N4007 8 R5 1k 10 0 BC107BP 1 BC107BP 5 Q4 R2 1.8k 3 Q2 BC107BP 6 D1 1N4007 R4 100 7 0 LED1 4 Q3

OBSERVATIONS:Input (A) L H Output (Y) H L

RESULT:- Study of transient analysis of BJT Inverter using NPNTransistor has been done.

4

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

EXPERIMENT NO.03

OBJECT:- Transient Analysis of NMOS inverter using step input. APPARATUS REQUIRED:- Multisim v.10.0 THEORY:For any IC technology used in digital circuit design, the basic circuit element is the logic inverter.Once the operation and characterization of an inverter circuit sare thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits. N-type metal-oxide-semiconductor logic uses n-type metal-oxidesemiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. NMOS transistors have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called active), and velocity saturation. The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.

5

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

CIRCUIT DIAGRAM:VDD 10V VDD R1 10k 0 1 Q1 2 V1 3.3 V 0 MTD4N20E 0 0 C1 20pF XMM1

OBSERVATIONS:Sr.no. 1. 2. 3. 4. 5. 6. Input(V1) in volts 0V 1V 2V 3V 4V 5V Output(Vo) in volts 9.99 V 9.991 V 9.992 V 9.993 V 1.876mV 936.64uV

RESULT:- Study of transient Analysis of NMOS inverter using stepinput has been done.

6

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

EXPERIMENT NO.04

OBJECT:-

Transient Analysis of NMOS inverter using pulse input.

APPARATUS REQUIRED:- Multisim v.10.0. THEORY:For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. Once the operation and characterization of an inverter circuit thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits. N-type metal-oxide-semiconductor logic uses n-type metal-oxidesemiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. NMOS transistors have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called active), and velocity saturation. The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.

7

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

CIRCUIT DIAGRAM:VDD 10V VDD XFG1Agilent

XSC1Ext Trig + _ A + _ + B _

R1 10k 1 0 Q1 2 MTD4N20E 0 0 C1 20pF

0

0

OBSERVATIONS:-

Result:- Study of Transient Analysis of NMOS inverter using pulseinput has been done.8

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

EXPERIMENT NO.05

OBJECT:- Transient Analysis of CMOS inverter using step input. APPARATUS REQUIRED:- Multisim v.10.0. THEORY:An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this 'resistive-drain' approach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows through the resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption and processing speed. Alternatively, inverters can be constructed using two complementary transistors in a CMOS configuration. This configuration greatly reduces power consumption since one of the transistors is always off in both logic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-only or PMOS-only type devices. Inverters can also be constructed with Bipolar Junction Transistors (BJT) in either a resistor-transistor logic (RTL) or a transistor-transistor logic (TTL) configuration. Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see Binary). An inverter circuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include (0, +5V) for TTL circuits.

9

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

CIRCUIT DIAGRAM:VCC 10V VCC R1 1k 2 Q2 XMM1

3

2N6804 0 1 Q1

V1 5 V 0

MTD4N20E 0

OBSERVATIONS:Input (V1) in volts 0V 1V 2V 3V 4V 5V Output (Vo) in volts 9.99 V 9.991 V 9.992 V 9.993 V 1.876mV 936.64uV

RESULT:-

Study of transient Analysis of CMOS inverter using step input has been done.

10

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

EXPERIMENT NO.06

OBJECT:- Transient Analysis of CMOS inverter using pulse input. APPARATUS REQUIRED:- Multisim v.10.0. THEORY:An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this 'resistive-drain' approach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows through the resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption and processing speed. Alternatively, inverters can be constructed using two complementary transistors in a CMOS configuration. This configuration greatly reduces power consumption since one of the transistors is always off in both logic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-only or PMOS-only type devices. Inverters can also be constructed with Bipolar Junction Transistors (BJT) in either a resistor-transistor logic (RTL) or a transistor-transistor logic (TTL) configuration. Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see Binary). An inverter circuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include (0, +5V) for TTL circuits.

11

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

CIRCUIT DIAGRAM:VCC 10V VCC R1 1k 2 Q2 XFG1Agilent

XSC1Ext T rig +

3 0

2N6804 1+

_ A _ + B _

0 Q1

0

MTD4N20E 0

OBSERVATIONS:-

RESULT:- Study of Transient Analysis of CMOS inverter using pulseinput has been done.12

TEENA SHARMA (ECE-3 YEAR) 0925231049

rd

CAD LAB (EEC-653)

EXPERIMENT NO.07

OBJECT:- Transient & D.C. Analysis of NOR gate using n-p-n transistor. APPARATUS REQUIRED:- Multisim V.10.0. THEORY:The NOR

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