EX.NO.1 CHARACTERISTICS OF PN DIODE AND ZENER DIODEA. Characteristics of PN Diode
Objective To obtain the V-I characteristics of a PN Diode.
Equipments
S.NO APPARATUS RANGE QUANTITY
1 Regulated Power supply (0-30)V,2A 1
2 Voltmeter (0-1)V /(0- 30)V 1
3 Ammeter (0-50) mA,
(0-500)µA
1
4 Diode IN4007 1
5 Resistor 1 K ohm, ½ W 1
6 Breadboard, Connecting Wires - -
Theory
Forward Bias In PN junction diode, electrons are the majority carrier in n- region; holes are the
majority carrier in p- region. When voltage is applied to a forward biased pn diode, electrons
diffuse from the n region to the p region and are captured by holes in the p region. These
captured electrons are attracted towards the positive terminal of the voltage source. In the
forward biased condition, majority carrier moves across the junction and leaves less
immobile ions in the depletion region. So the width of the depletion region is very small and
the resulting current is large. It is measured in terms of mA. The forward cut in voltage is
generally 0.6 V.
Reverse Bias
During the reverse bias condition, the majority carrier moves away from the junction
and leaves many immobile ions in the depletion region. So the width of the depletion region
increases which results in very little current. It is measured in terms of µA.
Circuit Diagram
Model Graph
Observation
Forward Characteristics
S.NO FORWARD VOLTAGE - Vf( VOLTS) FORWARD CURRENT - If(mA)
Reverse Characteristics
S.NO REVERSE VOLTAGE – Vr ( VOLTS) REVERSE CURRENT - Ir (µA)
Procedure
Connections are made as shown in Fig 1.1 and Fig 1.2. By adjusting the RPS, voltage
and current are measured from the voltmeter and ammeter respectively. Then the readings are
tabulated. V-I characteristics of the pn junction diode is drawn on the graph by taking voltage
on the X- axis and current on the Y – axis.
ResultThus the V-I characteristics of a pn junction diode is obtained and plotted on the
graph.
B. Characteristics of Zener Diode
Objective
To obtain the V-I characteristics of a Zener diode.
Equipments
S.NO APPARATUS RANGE QUANTITY
1 Regulated Power supply (0-30)V,2A 1
2 Voltmeter (0-1)V ,(0- 10)V 1
3 Ammeter (0-50) mA 1
4 Zener Diode 6.2 V, 250mW 1
5 Resistor 1 K ohm, ½ W 1
6 Breadboard, Connecting Wires - -
Circuit Diagram
Model Graph
Observation
Forward Characteristics
S.NO FORWARD VOLTAGE – Vf( VOLTS) FORWARD CURRENT - If(mA)
Reverse Characteristics
S.NO REVERSE VOLTAGE – Vr( VOLTS) REVERSE CURRENT - Ir(mA)
Theory
Diodes, which are designed to operate in the breakdown region, are called Zener
diode. In zener diode, direct rupture of covalent bonds takes place because of the strong
electric field at the junction. The new electron hole pair so created increase the reverse
current. Thus large change in the diode current by variation in load current or supply voltage
results small change in diode voltage. In forward bias condition, Zener Diode acts as an
ordinary pn diode and in the reverse bias breakdown occur at 6.2 V. At this voltage, the
current increases very rapidly and limited by Rs only.
Procedure
The Forward Bias and Reverse Bias connections are made as shown in Fig 1.3 and
Fig 1.4. By varying the RPS, Vr and Ir, Vf and If readings are noted and tabulated. The V-I
characteristics are plotted on the graph.
Result
Thus the V- I characteristics of Zener Diode is obtained and the graph is plotted.
EX.NO.2 CHARACTERISTICS OF PHOTODIODE
Objective
To obtain the V-I characteristics of the Photodiode.
Equipments
S.NO APPARATUS RANGE QUANTITY
1 Regulated Power supply (0-30)V,2A 1
2 Digital Voltmeter (0-10)V 1
3 Ammeter (0-500) A 1
4 Photo Diode TIL81 1
5 Resistor 100 K ohm, 1/4 W 1
6 Breadboard, Connecting Wires - 1
Circuit Diagram
Fig 2.1 CHARACTERISTICS OF PHOTODIODE
Model Graph
Observation
Light with high intensity Light with medium
intensity
Light with low intensity
Vd (volts) Id( A) Vd (volts) Id( A) Vd (volts) Id( A)
Theory
Photodiode is a reverse biased PN junction semiconductor device. It converts light
energy into electrical energy (current). It permits light to fall on one side of the device across
the junction, keeping the remaining sides unilluminated. When light falls on the junction,
carriers are generated which contribute photocurrent. This current is proportional to the
incident light.
Procedure
Connections are made as shown in Fig 2.1. First, keep the photodiode at some fixed
distance from the light then vary the RPS and note down the voltmeter and ammeter readings
in the light 1 column. Next decrease the distance between the light and the photodiode and
repeat the above procedure. Depending upon the incident light, current flows through the
device. Plot the voltage on the X-axis and current on the Y-axis on the graph.
Result
Thus the V_I characteristics of a photodiode is obtained and plotted on the graph.
EX.NO.3 CHARACTERISTICS OF BJT
Objective
To obtain the input and output characteristics of a transistor under common emitter configuration.
Apparatus
S.NO APPARATUS RANGE QUANTITY
1 Regulated Power supply (0-30) V,2A 2
2 Digital Voltmeter (0-1)V 1
3 DC Voltmeter (0-30) V 1
4 DC Ammeter (0-500) A &
(0-50)mA
1
5 Resistor 1 K ohm,100 Kohm 1
6 Transistor BC107/SL100 1
7 Breadboard and Connecting Wires
Circuit Diagram
Fig 3.1 CE Configuration
Model Graph
Input Characteristic
Output Characteristic
Tabulation:
Input CharacteristicsS.No VCE=0V VCE=5V
VBE(V) IB(µA) VBE(V) IB(µA)
Output characteristics S.No IB=20µA IB=80µA
VCE(V) Ic(mA) VCE(V) Ic(mA)
Theory
Transistor can be made to work in any of the three configurations
1. Common base (CB) configuration
2. Common emitter (CE) configuration
3. Common collector (CC) configuration
In CE configuration, input signal is fed between the base and emitter. The output is
developed between the emitter and collector.
Input characteristics:
This characteristic relates the input current with the input voltage, for a given value of
output voltage VCE. The curve is just like the diode characteristic in forward bias region.
Output characteristics
This characteristic relates the output current with the output voltage for a given value
of input current IB. The curve indicates the way in which the collector current varies with the
change in collector to emitter voltage with the base current IB kept constant.
Procedure
Connections are given as per Fig 3.1. By keeping the collector-emitter voltage at
different constant levels, readings are tabulated for the input characteristics. Again by
keeping the base current at different constant levels, readings are tabulated for the output
characteristics. Finally, the tabulated readings are plotted on the graph.
Result
Thus the input and output characteristics of a transistor under CE configuration are
obtained and plotted on the graph.
EX.NO.4 CHARACTERISTICS OF JFET
Objective
To obtain the drain characteristics of JFET.
Equipments
S.NO APPARATUS RANGE QUANTITY
1 Regulated Power supply (0-30)V,2A 2
2 Voltmeter (0-10)V / (0-30)V 1
3 Ammeter (0-50) mA 1
4 JFET BFW10 1
5 Resistor 1 K ohm,1/2 W 1
6 Breadboard - 1
Circuit Diagram
Model Graph
Observation
S.No Vds(volts) Vgs = 0V Vgs = - 1V Vgs = - 2V
Id(mA) Id(mA) Id(mA)
Theory
FET consists of three terminals namely source, drain and gate. Source is the terminal
through which the majority carriers enter the substrate. Drain is the terminal through which
the majority carriers leave the substrate. Gate is nothing but a heavily doped p-region. Space
between two p-region is called channel. Reverse bias is applied to the gate terminal. When
Vgs = 0, width of the channel is large. So it conduct large amount of carriers, which results in
large Id current. When Vgs is increased from “0”, i.e., when the channel reverse bias is
increased, the conducting portion of the channel begins to constrict. So it results in fewer I ds
current.
Procedure
Connections are made as shown in the Fig.4.1. By adjusting RPS I, Vgs is fixed to a
value. Then by varying RPS II, Vds and Id values are noted. Taking Vds on the X-axis and Id on
the Y-axis graph is plotted
Result
Thus the drain characteristics of a JFET is obtained and plotted on the graph.
EX.NO.5 CHARACTERISTICS OF UJT
Objective
To obtain the characteristics of a UJT.
Equipments
S.NO APPARATUS RANGE QUANTITY
1 Regulated Power supply (0-30)V,2A 1
2 Digital Multimeter/Voltmeter (0-10)V /(0- 30)V 1
3 Ammeter (0-10) mA 1
4 UJT 2N2646 1
5 Resistor 4.7 KΩ,1 KΩ 1/4W 1
6 Breadboard - -
Circuit Diagram
Model Graph
Observations
VB1B2 = 0 V VB1B2 = 5V VB1B2 = 10 V
VB1E (volt) IE (mA) VB1E (volt) IE (mA) VB1E (volt) IE (mA)
Description
UJT has a unijunction. It consists of three terminals namely emitter, base1 and base2.
UJT is also called double base diode. UJT operates when the emitter is forward biased.
Voltage Vb1b2 is applied between base1 and base2. If an external voltage is applied at
terminal E, no current will flow into the emitter as long as this applied voltage is less than VE.
When this applied voltage exceeds VE, current flows into the emitter and holes get injected
from emitter to base1 and are repelled by base2. This results in increase in the region between
the junction and the base1. The increase in conductivity results in drop in voltage VE and
increased forward bias of the junction. So IE also increases, then it exhibits a negative
resistance.
Procedure
The connections are made as shown in Fig 5.1. By adjusting the RPS II, VB1B2 is kept
at some fixed value. The input voltage is varied in steps by varying the RPS I and the
corresponding value of IE is noted. Then the readings are plotted on the graph.
Result
Thus the characteristics of UJT is obtained and plotted on the graph.
EX.NO.6: V-I CHARACTERISTICS OF SILICON CONTROLLED RECTIFIER AND TRIAC
AimTo Draw the V-I characteristics of a Silicon Controlled Rectifier and Triac for both forward and Reverse bias condition.
Apparatus Required
S. No Name of the Apparatus Range Quantity 1 SCR TYN 616 1 2 TRIAC BT136 13 RPS (0-30)v 2 4 Voltmeter (0-30)v 1 5 Ammeter (0-10) mA 1 6 Ammeter (0-100)mA 1 7 Resistor 4.7 kΩ,5W 1 8 Resistor 470Ω 19 Resistor 2.2KΩ10 Connecting wires -- 1set 11 potentiometer 5KΩ 112 Fixed power supply 12V 1
SCR:
Circuit Diagram
Fig 6.1 Characteristics of SCR
CONNECTION DIAGRAM
Model Graph
TabulationS. No Anode-Cathode
Voltage VAK (Volts)
Gate CurrentIG (mA)
AnodeCurrentIA (mA)
Anode – Cathodevolt when SCR isON (volts)
TRIAC:
CIRCUIT DIAGRAM:
Fig 7.1 Characteristics of TRIAC
Model Graph
Tabulation
S.NoWith Positive Biasing IG= With Negative Biasing IG=
TRIAC VOLTAGE (Va)
TRIAC CURRENT (Ia)
TRIAC VOLTAGE (-Va)
TRIAC CURRENT (-Ia)
Theory
SCR Silicon controlled Rectifier is an ac power control device in which the current
through the load can be controlled by the gate pulse applied to this device. The anode and
cathode are connected to main source through the load. The gate and cathode are fed from a
source Es which provides positive gate current from gate to cathode. An SCR consists of four
layers of alternating P and N type semiconductor materials. Silicon is used as the intrinsic
semiconductor, to which the proper dopants are added. The junctions are either diffused or
alloyed. The planar construction is used for low power SCRs (and all the junctions are
diffused). The mesa type construction is used for high power SCRs. In this case, junction J2
is obtained by the diffusion method and then the outer two layers are alloyed to it, since the
PNPN pellet is required to handle large currents. It is properly braced
with tungsten ormolybdenum plates to provide greater mechanical strength. One of these
plates is hard soldered to a copper stud, which is threaded for attachment of heat sink. The
doping of PNPN will depend on the application of SCR, since its characteristics are similar to
those of thethyratron. Today, the term thyristor applies to the larger family of multilayer
devices that exhibit bistable state-change behaviour, that is, switching either ON or OFF.
The operation of a SCR and other thyristors can be understood in terms of a pair of tightly
coupled bipolar junction transistors, arranged to cause the self-latching action:
TRIAC The triac is another three terminal ac switch that is triggered into conduction
when a low energy signal is applied to its gate terminal. Unlike the SCR, the triac conducts in
either direction when turned on. The triac also differs from the SCR in that either a positive
or negative gate signal triggers it into conduction. Thus the triac is a three terminal, four layer
bidirectional semiconductor device that controls ac power whereas controls dc power or
forward biased half cycle of ac in a load. Because of its bidirectional conduction property, the
triac is widely used in the the field of power electronics for control purposes. Though the
triac can be turned on without any gate current provided the supply voltage becomes equal to
the breakover voltage of the triac but the normal way to turn on the triac is by applying
a proper gate current. As in case of SCR, here too, the larger the gate current, the
smaller the supply voltage at which the triac is turned on. Triac can conduct current
irrespective of the voltage polarity of terminals MT1 and MT2.
TRIAC controls are more often seen in simple, low-power circuits than complex,
high-power circuits. In large power control circuit, multiple SCRs tend to be favored. Main
terminals on 1 and 2 on a TRIAC are not interchangeable. To successfully trigger a TRIAC,
gate terminal must come from the main terminal 2 (MT2) side of the circuit.
PROCEDURE:1. The connection are made as per in the circuit diagram.2. First by varying potentiometer gate current (IG) is kept constant.3. The voltage between MT1 and MT2 is increased in step by varying the varying
the RPS 1.4. The corresponding current (I MT1) is noted.5. The process is repeated for two more constant values of IG, the readings are
tabulated.
RESULT:Thus the forward and reverse characteristics of SCR and TRIAC is drawn and verified.
Ex.No.7 VERIFICATION OF THEVENIN’S THEOREMObjective
(a) To verify the Thevenin’s theorem and to determine the current flowing through
the load resistance of the given DC circuit.
(b) To verify the Thevenin’s theorem using PSPICE
Equipments
DesignLab Eval 8 software.
Description
Definition
Thevenin’s Theorem
Any circuit having voltage sources, resistors and open output terminals can be
replaced by a single current source in series with single resistance (impedances),where the
value of the voltage source is equal to the open circuit output terminals and the value of
resistance (impedance) is equal to the resistance seen into the network across the putput
terminals.
Procedure
1. Open the Schematics in DesignLab Eval 8
2. From “GET NEW PART” get the required circuit elements by clicking on it
and draw the given circuit.
3. Use VIEWPOINT and IPROBE to read the voltages and currents respectively,
in the circuit.
4. Use GND_ANALOG to ground the circuit.
5. Save the file with *.sch
6. Simulate the circuit by clicking on the “Simulate” icon
7. Click on the “Analysis” menu and then click “Examine Output”.
8. Read the simulated results from the “MicroSim Text Editor”
Circuit Diagram
Manual Calculation
Step 1
To measure the Thevenin’s voltage
Thevenin’s voltage is equal to the voltage across the terminals AB
VAB=V3+V6+10
Here the current passing through 3 resistor is zero
Hence V3 =0
By applying Kirchoff’s voltage Law for the loop,
50-10I1-6I1-10=0
6I1 = 40
I1
=4016 =2.5 A
The voltage across 6 is V6,
10 Ω 3 Ω
10 Ω6 Ω
10 Ω 3 Ω6 Ω
V6 =6 x 2.5=15V
The voltage across the terminals AB is
=Vth=VAB =0+15+10=25V
Step 2
To measure the Thevenin’s resistance
The resistance as seen in to the terminals AB,
Rth=RAB
=10 x 610+6 +3
Rth=6.75
Also Rn=6.75
10Ω 3Ω
6Ω
Step 3
To draw the Thevenin’s equivalent circuit
Step 4
To measure the current flowing in the load resistance 10 is
I L
=V TH
RTH+RL =25
6 .75+10 =25
16 . 75 =1.49 A
Simulation
Step 1
Measurement of Thevenin’s voltage
6.75Ω
10Ω
10Ω 3Ω
6Ω
1000MΩ
Simulated Results
* Schematics Netlist *V_V1 $N_0001 0 DC 50V R_R1 $N_0001 $N_0002 10 V_V2 $N_0003 0 DC 10V R_R3 $N_0003 $N_0002 6 R_R2 $N_0002 1 3 R_Rload 0 1 1000meg
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( 1) 25.0000 ($N_0001) 50.0000 ($N_0002) 25.0000
($N_0003) 10.0000
VOLTAGE SOURCE CURRENTS NAME CURRENT
V_V1 -2.500E+00 V_V2 2.500E+00
Step 3
Measurement of Thevenin’s equivalent resistance
RTH = RN = VOC/ISC = VTH/IN
= 25/3.704=6.75
Step 4
Thevenin’s equivalent cicuit
Simulation Result* Schematics Netlist *
V_Vth $N_0001 0 DC 25V R_Rth $N_0001 $N_0002 6.75 R_Rload $N_0002 $N_0003 10 V_V3 $N_0003 0 0
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
($N_0001) 25.0000 ($N_0002) 14.9250
($N_0003) 0.0000
VOLTAGE SOURCE CURRENTS NAME CURRENT
V_Vth -1.493E+00 V_V3 1.493E+00
6.75Ω
10Ω
Result
Thus the Thevenin equivalent circuit drawn for the given circuit and the equivalent
voltage and the current through the load resistance are calculated using PSPICE software.
Ex.No.8 VERIFICATION OF KIRCHOFF CURRENT LAW
Objective
To verify Kirchoff’s current law in the given circuit using PSPICE .
Equipments
DesignLab Eval 8 software.
Circuit Diagram For KCL
Description
Definition
Kirchoff’s Current Law
The algebraic sum of the current entering any node is zero.
i=0
Procedure
1.Open the Schematics in DesignLab Eval 8
2.From “GET NEW PART” get the required circuit elements by clicking on it
and draw the given circuit.
3.Use VIEWPOINT and IPROBE to read the voltages and currents respectively,
in the circuit.
4.Use GND_ANALOG to ground the circuit.
5.Save the file with *.sch
6.Simulate the circuit by clicking on the “Simulate” icon
7.Click on the “Analysis” menu and then click “Examine Output”.
A A
8.Read the simulated results from the “MicroSim Text Editor”
Manual Calculation
According to KCL,
I1+I2+I3+I4+5=10A
At node A,
I1+I2+I3+I4 =5A
I1=V/R1=V/5
I2= V/R2=V/10
I3= V/R3=V/2
I4= V/R2=V/1
V/5+V/10+V/2+V/1=5
V[0.2+0.1+0.5+1]=5
V=2.78 V
Current passing through 5 is V/5=2.78/5=0.556 A
Current passing through 10 is V/10=2.78/10=0.278 A
Current passing through 2 is V/2=2.78/2=1.39 A
Current passing through 1 is V/1=2.78/1=2.78 A
Circuit Simulation
AA
Simulated Results
* Schematics Netlist *
I_I2 $N_0001 0 DC 5
I_I1 0 $N_0001 DC 10
R_R1 $N_0002 $N_0001 5
R_R2 $N_0003 $N_0001 10
R_R3 $N_0004 $N_0001 2
R_R4 $N_0005 $N_0001 1
v_V1 $N_0002 0 0
v_V2 $N_0003 0 0
v_V3 $N_0004 0 0
v_V4 $N_0005 0 0
NODE VOLTAGE
($N_0001) 2.7778
VOLTAGE SOURCE CURRENTS
NAME CURRENT
v_V1 5.556E-01
v_V2 2.778E-01
v_V3 1.389E+00
v_V4 2.778E+00
Result:
Thus for the given circuit Kirchoff’s current was verified in both by calculation and
with simulated results.
Ex.No.9 VERIFICATION OF KIRCHOFF VOLTAGE LAW
Objective
To verify Kirchoff’s voltage law in the given circuit using PSPICE .
Equipments
DesignLab Eval 8 software.
Circuit diagram for KVL
Description
Definition
Kirchoff’s Voltage Law
The algebraic sum of voltages around any closed path in a circuit is zero.
V=0
Procedure
1.Open the Schematics in DesignLab Eval 8
2.From “GET NEW PART” get the required circuit elements by clicking on it
and draw the given circuit.
3.Use VIEWPOINT and IPROBE to read the voltages and currents respectively,
in the circuit.
4.Use GND_ANALOG to ground the circuit.
5.Save the file with *.sch
6.Simulate the circuit by clicking on the “Simulate” icon
7.Click on the “Analysis” menu and then click “Examine Output”.
8.Read the simulated results from the “MicroSim Text Editor”
Manual Calculation
According to KVL,
8I+50+30I +2I =100
8I+2I+30I=50
40I=50
I=1.25A
V= I* R
Voltage across 8 is 8I= 8*1.25=10A
Voltage across 2 is 2I=2*1.25=2.5A
Voltage across 30 is 30I=30*1.25=37.5 A
Circuit Simulation
Simulated Results
* Schematics Netlist *
V_V1 1 0 50V
R_R3 3 4 2
R_R2 0 $N_0001 30
R_R1 1 2 8
V_V3 2 3 100V
V_V4 $N_0001 4 0
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE
VOLTAGE
( 1) 50.0000 ( 2) 60.0000 ( 3) -40.0000 ( 4) -37.5000
($N_0001) -37.5000
VOLTAGE SOURCE CURRENTS
NAME CURRENT
V_V1 1.250E+00
V_V3 -1.250E+00
V_V4 1.250E+00
Result:
Thus for the given circuit Kirchoff’s voltage law was verified in both by calculation
and with simulated results.
Ex.No.10 VERIFICATION OF SUPERPOSITION THEOREM
Objective
To verify the superposition theorem using PSPICE and to determine the current
flowing through 1 resistance of the given circuit.
Equipments
DesignLab Eval 8 software.
Circuit diagram:
Description
Definition
Superposition Theorem
The superposition theorem states that “in any linear network containing two or more
sources ,the response in any element is equal to the algebraic sum of the response by
individual sources acting alone ,while the other sources are non-operative”.
Procedure
1.Open the Schematics in DesignLab Eval 8
2.From “GET NEW PART” get the required circuit elements by clicking on it
and draw the given circuit.
3.Use VIEWPOINT and IPROBE to read the voltages and currents respectively,
in the circuit.
4.Use GND_ANALOG to ground the circuit.
5.Save the file with *.sch
6.Simulate the circuit by clicking on the “Simulate” icon
7.Click on the “Analysis” menu and then click “Examine Output”.
8.Read the simulated results from the “MicroSim Text Editor”
Calculation:
Step 1:
To find the current through 1 resistance due to 10V source the circuit can be redrawn as
Using Mesh method
[25 −5−5 18 ][ I 1
I 2 ]= [100 ]
20I1+(I1-I2)5=1020I1+5I1-5I2=1025I2-5I2=10
I 2 =
[25 10−5 0 ]
[25 −5−5 18 ]
= 0.117A
Current flowing through 1 resistance =0.117A
Step 2: To find the current flowing through 1 resistance due to 5A source, the circuit can be redrawn as
Using current division rule,
Input current flowing through 1 resistance
=5×12
12+(1+20×520+5 )
=5×12
12+1+4
= 3.52A
Current flowing through 1 resistance = -3.52 A(Negative current direction)
Step 3:To find the current flowing through 1 resistance due to 50V source, the circuit can be redrawn as
Using Mesh method
[25 −5−5 18 ][ I 1
I 2 ]= [0
−50]
I 2 =
[25 0−5 −50 ][25 −5−5 18 ]
= -2.941A
Current flowing through 1 resistance = -2.941 A
Step 4: The algebraic sum of these currents gives the total current flowing through 1 resistance
In step I Current flowing through 1 resistance =0.117A
In step II Current flowing through 1 resistance = -3.52 A
In step III Current flowing through 1 resistance = -2.941 ATotal current flowing through 1 resistance = 0.117-3.52 -2.941 I1 = -6.34A
Step 1:Circuit Simulation :
Simulated Results :
* Schematics Netlist *
R_R1 $N_0002 $N_0001 20 R_R2 0 $N_0001 5 V_V1 $N_0002 0 DC 10V R_R3 $N_0001 $N_0003 1 R_R5 0 $N_0004 12 V_V2 $N_0003 $N_0004 0NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
($N_0001) 1.5294 ($N_0002) 10.0000
($N_0003) 1.4118 ($N_0004) 1.4118
VOLTAGE SOURCE CURRENTS NAME CURRENT
V_V1 -4.235E-01 V_V2 1.176E-01
Step 2:
Circuit Simulation :
* Schematics Netlist *
R_R3 $N_0002 $N_0001 1 R_R5 0 $N_0003 12 R_R1 0 $N_0002 20 R_R4 $N_0004 $N_0003 70 I_I1 0 $N_0004 DC 5A R_R2 0 $N_0002 5 V_V2 $N_0001 $N_0003 0
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
($N_0001) 17.6470 ($N_0002) 14.1180 ($N_0003) 17.6470 ($N_0004) 367.6500
VOLTAGE SOURCE CURRENTS NAME CURRENT
V_V2 -3.529E+00
Step 3:Circuit Simulation :
* Schematics Netlist *
R_R3 $N_0002 $N_0001 1 R_R5 $N_0004 $N_0003 12 R_R1 0 $N_0002 20 R_R2 0 $N_0002 5 V_V2 $N_0003 0 DC 50V V_V3 $N_0001 $N_0004 0
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
($N_0001) 14.7060 ($N_0002) 11.7650
($N_0003) 50.0000 ($N_0004) 14.7060
VOLTAGE SOURCE CURRENTS NAME CURRENT
V_V2 -2.941E+00 V_V3 -2.941E+00
Step 4:
The algebraic sum of these currents gives the total current flowing through 1 resistance
In step I Current flowing through 1 resistance =0.117A
In step II Current flowing through 1 resistance = -3.52 A
In step III Current flowing through 1 resistance = -2.941 A
Total current flowing through 1 resistance = 0.117-3.52 -2.941
I1 = -6.34A
Result :
Thus the superposition theorem is verified and simulated using the PSPICE software
and the current flowing through 1 resistance of the given circuit was determined