Processors

Chapter 5

Processor Types And Instruction Sets

CS250 -- Part II

1D

r.Rajesh Subram

anyan, 2005

Topics

•Introduction

•M

athematical pow

er,convenience, and cost

•Instruction set and representation

•O

pcodes, Operands and results

•Typical instruction form

at

•V

ariable-length vs fixed-length instructions

•G

eneral-purpose registers

•Floating point registers and register identification

•Program

ming w

ith registers

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Topics

•R

egister banks

•C

omplex

and reduced instructions sets

•R

ISC design and the execution popeline

•Pipelines and instruction stalls

•O

ther causes of pipeline stalls

•C

onsequence for programm

ers

•Types of operations

•A

nexam

ple instruction set

•M

inimalistic instruction set

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Topics

•T

he principle of orthogonality

•Program

ming using conditional branching

•Sum

mary

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Introduction

•In

this chapter we discuss

−the set of operations a processor can perform

−the different architect approaches to instruction sets andtradeoffs

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What O

perations Should A P

rocessor Offer A

ndT

he Tradeoffs

•W

hat operations should a processor offer? At least three

views based on

−m

athematical pow

er: powerful instructions

−convenience: easy to program

−cost: less hardw

are

•Should a processor offer m

any, ora

few basic operations

−A

rchitect wants a sm

all operation set to reduce hardware

−Program

mer w

ants more for convenience

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What O

perations Should A P

rocessor Offer A

ndT

he Tradeoffs

•T

he set of operations a processor provides represents atradeoffam

ong the cost of the hardware, the convenience for

apro gram

mer,and engineering considerations such

aspow

erconsum

ption.

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Instruction Set And R

epresentation

•A

narchitect of a program

mable processor decides

−the set of operations supported by the hardw

are(instruction set)

−the operation representation (instruction form

at)

•A

ninstruction defi

nition includes

−an

exact definition (opcode)

−values (operands) and corresponding result

−exceptions

•Instruction form

at

−binary representation

−defi

nes hardware-softw

are boundaryC

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ajesh Subramanyan, 2005

Opcodes and O

perands

•O

pcode

−U

nique number assigned to denote the operation.

•O

perand

−V

alues on which operation is perform

ed.

−T

he number and type of operand is specifi

ed for eachoperation.

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Typical Instruction F

ormat

•Instruction

−represented as a binary string

•Instruction fi

elds

−O

pcode, followed by operand(s)

op

cod

eo

peran

d 1

op

erand

2.

..

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Hardw

arevs

Software

battle continues ..

•V

ariable-length vs. fixed-length instructions

•Should one instruction be shorter than another ?

−Program

mer says variable-length optim

izes mem

ory

−A

rchitect says hardware is less com

plexfor fi

xed-lengthinstruction

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Variable-length vs. fixed-length instructions ..

•H

ardware cam

p wins

•Fixed-length instruction set

−E

xtra fields are left unused

−U

nused bits are ignored

−L

eaving bits unused is needed for hardware optim

ization

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General purpose registers

•H

igh-speed hardware device w

ith fixed size

•Tem

porary storage device

•Supports fetch and store operations

•Sem

antics same as m

emory

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Floating point registers and register identification

•Separate registers to hold floating point values

•N

umbering sam

e as GP register.

•So

which register is #X

?

−Processor interprets from

opcode if it needs to fetchoperand from

GP or FP register

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Program

ming w

ith registers

•M

ove operands to register

•E

xecute instruction

•R

esults may be stored in register

•R

egisters are few: optim

ize allocation.

•D

ouble precision result. Storage?

−H

ardware: registers are consecutive;use 2

−Program

mers: plan accordingly.

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Register B

anks

•N

ew com

plication to register allocation- register banks !

•W

hat are they?

−R

egister group with separate physical access

•W

hy dow

eneed them

?

−A

llows sim

ultaneous access, e.g. one cycle to obtain bothoperands

•So

what is the problem

!

−Program

mers can’tperm

anently assign data to registers

−C

onflict occurs (both operands end up on the same bank);

solution,

*R

eassign registers

*Insert copy

instructionC

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ajesh Subramanyan, 2005

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Register B

anks

•A

re banks absolutely necessary ?

−Y

es, performance !!

•L

ast word on registers

−R

egistersare expensive.U

se judiciously for improving

performance

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Com

plex and reduced instruction sets

•Instruction set categories

−C

ISC

−R

ISC

•C

ISC

−Instruction set large

−Instructions m

ay do complex

computation

•R

ISC

−Instruction set m

inimized

−B

asic computations

−Instruction execution constant: 1 clock cycle

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Execution pipeline in R

ISC

•R

ISC designed to com

plete instruction/cycle.

•H

ow?

−Processor divides fetch-execute cycle into m

ultiples steps

−H

ardware a m

ultistage pipeline

−E

ach stage completes one step/cycle, throughput 1

ins/cycle.

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Pipelines &

instruction stalls

•A

dvantage

−Pipeline transparent to program

mers

•D

isadvantage

−program

mer can inadvertently introduce ineffi

ciencies

−e.g. Pipeline stalls

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Causes of pipelines stalls

•W

aiting for operands

•T

he processor

−A

ccesses external storage

−Inv okes

acoprocessor

−B

ranches to newlocation

−C

alls a subroutine

•H

ardware solution

−D

uplicate copies in pipeline for a branch, compute both

results, discard one.

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Consequences for program

mers

•A

void

−B

ranch instructions

−A

fter result is computed, delay reference to the result

register

•Separate references from

computation

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Types of operations

•A

rithmetic

•L

ogical

•D

ata access and transfer

•B

ranch (conditional and unconditional)

•Floating point

•Processor control

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MIP

S processor instruction set

Instru

ction

M

eanin

g

Ar ithm

eticad

din

teg er

add

ition

sub

tract in

teger su

btractio

nad

dim

med

iate in

teger ad

ditio

n (reg

ister + con

stant)

add

un

sign

ed

un

sign

edin

teg er

add

ition

sub

tract un

sign

edu

nsig

ned

integ

er sub

traction

add

imm

ediate u

nsig

ned

un

sign

ed ad

ditio

n w

ith a co

nstan

tm

ove from

cop

rocesso

r access

cop

rocesso

r register

mu

ltiply

integ

erm

ultip

lication

mu

ltiply

un

sign

ed

un

sign

edin

teg er

mu

ltiplicatio

nd

ivide

integ

er divisio

nd

ivide u

nsig

ned

un

sign

ed in

teger d

ivision

move fro

m H

iaccess h

igh

-ord

er register

move fro

m L

oaccess lo

w-o

rder reg

isterLogical (B

oolean)an

d

log

icalAN

D (tw

oreg

isters)o

r lo

gicalO

R (tw

oreg

isters)an

d im

med

iateA

ND

of reg

ister and

con

stant

or im

med

iateO

R o

f register an

d co

nstan

tsh

ift left log

icalS

hift reg

ister left N b

itssh

ift righ

t log

icalS

hift reg

ister righ

t N b

itsC

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Dr.R

ajesh Subramanyan, 2005

Data Transferlo

ad w

ord

load

register fro

m m

emo

rysto

re wo

rdsto

re register in

to m

emo

rylo

ad u

pp

er imm

ediate

place co

nstan

t in u

pp

er sixteenb

its of reg

isterm

ove from

cop

roc. reg

istero

btain

a value fro

m a co

pro

cessor

Conditional B

ranchb

ranch

equ

al b

ranch

iftw

o registers

equ

alb

ranch

no

t equ

alb

ranch

iftw

o registers

un

equ

alset o

n less th

anco

mp

are two

registers

set less than

imm

ediate

com

pare reg

ister and

con

stant

set less than

un

sign

edco

mp

are un

sign

ed reg

istersset less th

an im

med

iateco

mp

are un

sign

ed reg

ister and

con

stant

Unconditional B

ranchju

mp

g

oto

target

add

ressju

mp

register

go

to ad

dress in

register

jum

p an

d lin

kp

roced

ure call

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Floating point instructions defined by M

IPS architecture

Instru

ction

M

eanin

g

Ar ithm

etic

FP

add

flo

ating

po

int ad

ditio

nF

P su

btract

flo

ating

po

int su

btractio

nF

P m

ultip

lyfl

oatin

g p

oin

t mu

ltiplicatio

nF

P d

ivide

flo

ating

po

int d

ivision

FP

add

do

ub

le d

ou

ble-p

recision

add

ition

FP

sub

tract do

ub

le d

ou

ble-p

recision

sub

traction

FP

mu

ltiply

do

ub

le d

ou

ble-p

recision

mu

ltiplicatio

nF

P d

ivide d

ou

ble

do

ub

le-precisio

n d

ivision

Data Transfer

load

wo

rdco

pro

cessor

load

value in

to F

P reg

istersto

re wo

rdco

pro

cessor

store

FP

register to

mem

ory

Conditional B

ranch

bran

chF

Ptru

e b

ranch

ifF

Pco

nd

ition

is true

bran

chF

Pfalse

bran

chif

FP

con

ditio

n is false

FP

com

pare sin

gle

com

pare tw

oF

Preg

istersF

P co

mp

are do

ub

le co

mp

aretw

od

ou

ble p

recision

values

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Minim

alistic instruction set

•D

esign objective

−Speed (1 ins/cycle)

−M

inimalistic (few

est # of instructions)

•E

xample of speed: fast access to 0. D

esign?

−R

eserveregister 0 to contain 0 alw

ays

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r.Rajesh Subram

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Principle of O

rthogonality

•E

ach instruction should perform a unique task w

ithoutduplicating or overlapping the functionality of otherinstructions

•A

dvantages

−U

nderstanding ease

−E

legance

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r.Rajesh Subram

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Conditional B

ranching

•A

nalogous to if-then-else

if (A >

B) {

Q;

}else {

R;

}

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Conditional code m

echanism to im

plement branching

sub A B

#com

pute A - B

and set condition code

bnz Label1

#branch to L

abel1 if condition

jmp L

abel2#

jump to L

abel2

Label1:...code for R

#instructions that im

plement R

gohere

Label2:...

#program

continues at this point

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Wrapup

•E

ach processor defines an instruction set it supports

•R

egister help improve perform

ance

•Instructions

−R

ISC

*Speed, sim

ple, minim

al instructions

−C

ISC

*M

any, complex

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CS250 -- Part II

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