X-Compaction

Itamar Feldman

Before we begin…

Let’s talk about some DFT history:

Design For Testability (DFT) has been around since the 1960s. The technology was developed to reduce the cost of creating a successful test for an IC.

Scan Technology• memory elements (flip-flops) of the design are put into a shift

register. • These memory elements could be set to a logic 1 or logic 0, and the

values captured in them could be observed.

Numerous refinements were developed on this technology - • Partial scan, boundary scan and wrappers all use the fundamental

scan technology, BIST , ATPG algorithm and more.

Where is DFT heading?

New Challenges and Trends:• The scaling of process technology -> significant changes.

• New test challenges have appeared, requiring new solutions in DFT.

• Industry has redirected its focus to optimizing test-data-volume and test-application-time.

• Scan chains, the very technology that enables DFT, now pose a new challenge.

• Scan chains become very long, and the time required to process the scan chains has increased.

Scan Chains

processing a scan test pattern

Typical sequence in processing a single scan test pattern:

1. Set up the scan chain configuration. 2. Shift values into the active scan chains. 3. Exit the scan configuration. 4. Apply stimulus to the test circuit inputs and measure the outputs. 5. Pulse clocks to capture the test circuit response in flip-flops. 6. Set up the scan chain configuration. 7. Shift values out of the active scan chains. 8. Exit the scan configuration.

The shift operations use as many clock periods as the longest scan chain!.

The Solutions

• creative ways to treat the randomly filled bits.

• minimize the amount of intrusion in the design

• optimize the test-data-volume and test-application-time

• test process can be streamlined and compacted.

Solution info

Outline

• Introduction

• Overview of X-Compact

• Coverage of errors in the presence of X’s

• DPM impact for Actual designs

• Conclusions

INTRODUCTION

Outline:

Introduction

Overview of X-Compact

Coverage of errors in the presence of X’s

DPM impact for Actual designs

Conclusions

X-Compaction Introduction

• We present a technique to compact test response data using combinational logic circuits.

• Compact the Output results whilst retaining the

DFT capabilities of the chip • reducing the time needed to analyze the results

exponentially

• guarantee detection of defective chips even in the presence of unknown logic values.

X-Compaction advantages

1. Improving test quality2. Non-intrusive 3. Very little hardware overhead 4. No special configure is needed5. X-tolerance 6. Reduce Number of scanout pins almost

exponentially. 7. Reduce Number of scan channels 8. Reduce Scan test data volume Shorten

scan test time

OVERVIEW

Outline:

Introduction

Overview of X-Compact

Coverage of errors in the presence of X’s

DPM impact for Actual designs

Conclusions

X-Compaction approach

Basic idea

• The X-Compactor circuit block is a combinational circuit made up of XOR gates.

• Let us suppose that we have a design with n scan chains.

• Suppose that the X-Compactor has m outputs.

• The X-Compactor circuit can be represented as a binary matrix with n rows and m columns

• This matrix is called the X-Compact matrix

Example of X-Compactor circuit

In this Example the first output is obtained by XORing the outputs of 1,2,3,4,5 and 6 according to the X-Compact Matrix, As you can see in the above circuit

m

n

X-Compaction matrix

• Each row of the matrix corresponds to a scan chain.

• Each column corresponds to a compactor output.

The entry in row i and column j of the X-Compact matrix is 1 iff the jth compactor output depends on the output ofthe ith scan chain; otherwise, the entry is 0.

Error detection capabilities

Error detection capability of X-Compact circuits:

• The X-Compactor HW will detect 1,2,3 and any odd number of errors without any X values present.

• The X-Compactor HW will detect one error in the present of a single X value generated simultaneously.

The above properties of X-Compactor circuits were proved in [Mitra 02a].

X-Values, the problem.

• Xor-ing with a X-value gives a X-value,

and an error can be undetected.

• Xor-ing while compacting can cause data signature corruption

• Several solutions: well managed X-compact matrices, higher m ratio, and X-Tolerance.

Output pins Reduction

The fallowing table shows the number of X-Compact output pins in compared to the original Scan Chain number.

Scan Chain

Inputs#

X-Compact outputs#

105

206

217

358

569

12610

25211

46212

79213

171614

343215(x240 reduction>- )

Exponential reduction!

Error detection in a presence of X-values

Outline:

Introduction

Overview of X-Compact

Coverage of errors in the presence of X’s

DPM impact for Actual designs

Conclusions

Error detection in a presence of X-values

• The X-Compactor design guarantee detection of an error when a scan chain produces error and another produces X.

• This doesn’t necessarily mean when a scan chain produces error and two or three scan chains produce X’s that the error will not be detected!

• It really depends on which scan chain produced the error and which scan chains produced 2 or 3 X’s.

• What is the probability that an error will not be detected when 2 or 3 (or more) scan chains produce X’s?

Analysis of X-compaction

• The probability that an error produced by a scan will not be detected when k other scan chains produce Xs simultaneously is denoted by p(n, k, i).

• Where n is the number of uncompacted ouputs and i is the number of 1’s in the matrix rows for the practical use of the analysis we’ll use 2 & 3

Percentage of undetected errors in the Presence of X values

Tables 3.1-3.2 show the values of p(n, k,2) and p(n, k, 3) for various values of n and k.

DPM impact

Outline:

Introduction

Overview of X-Compact

Coverage of errors in the presence of X’s

DPM impact for Actual designs

Conclusions

X-Compaction impact on DPM

• Let Y be the yield of the part. (1-Y) is the proportion of parts that are defective.

• If C is the proportion of defective chips detected by the regular scan test, the number of defective chips that will escape is (1-Y)*(1-C) and the resulting customer DPM is

Impact on DPM cont.

If z is the proportion of detected defective chips cannot be detected due to the presence of the X-Compactor, then the resulting DPM is:

For 80% yield and a test quality of 100 DPM without X-Compactor, the DPM is:

For all practical reasons Z<<1

X-distribution effect on DPM in Actual designs

Outline:

Introduction

Overview of X-Compact

Coverage of errors in the presence of X’s

DPM impact for Actual designs

Conclusions

Actual designs

Actual Design for X-Compact implementation differ in several issues:

1. X-management – What % of X-values are we expecting to have

2. Ratio of n/m (Uncompacted/compacted outputs)

3. X-Compact Matrices (will be covered in X-tolerance)

Measurement Analysis

Design for X-Compact are measured in:

1. Percentage of detected error.

2. DPM impact on production.

3. Number of cycles for Test.

4. X-tolerance.

Actual Designs

We will look at 3 designs

1. Moderate X-Management (86% without X values)

2. Well-Managed X (98% without X values)

3. ILL-Managed X (74% without X values)

For each case will look into several values for m and it’s effect on DPM.

Design1 Moderate X-Management

86% of all scan-out cycle don’t produce X-values

• Desing1 with n=400,m=31 (Type1) ~98.5% of defective chip detection for no or a single X tolerant, impact on DPM < 0.02

• m=20 impact on DPM < 0.13 (Type2)• m=11 Serial scan only 1X Tolerance allowed per

scan, (37 cycles), 24 time reduction in test time!, no impact on DPM!

Design2 Well-Managed X

98% of all scan-out cycle don’t produce X-values

• Desing2 with n=400,m=31 (Type1) ~99.36% of defective chip detection for no or a single X tolerant, impact on DPM < 0.16

• m=20 impact on DPM < 0.3 (Type2)• m=11 Serial scan only 1X Tolerance allowed per

scan, (37 cycles), 14.7 time reduction in test time!, no impact on DPM!

Design3 ILL-Managed X

74% of all scan-out cycle don’t produce X-values

• Desing3 with n=400,m=31 (Type1) ~95.8% of defective chip detection for no or a single X tolerant, impact on DPM < 0.77

• m=20 impact on DPM < 1 (Type2)• m=11 Serial scan only 1X Tolerance allowed per

scan, (37 cycles), 30 time reduction in test time!, no impact on DPM!

One Assumption

• This analysis assumes that there is no correlation between how X’s and errors appear in the two scan-out cycles.

• In case there is The DPM impact due to the correlation is could be much higher (up to x4 in ILL-Managed!) and unacceptable

• In this case the user can use the technique with serial scan support.

Conclusion

Outline:

Introduction

Overview of X-Compact

Coverage of errors in the presence of X’s

DPM impact for Actual designs

Conclusions

Conclusion

• We can clearly see the usefulness of the X-Compact technique for response compaction purposes.

• This technique can save time, space and has little overhead for it’s HW.

• It is also shown that X-Compactor designs with none, or few X values has little or no effect on DPM and will save time.

Q&A

Thanks for listening!

Based on an article by

Subhasish Mitra*, Kee Sup Kim and Shyam Kallepalli / 15-Oct-2002

“Analysis of Practical X-Compact Designs”