Testability: Lecture 23 Design for Testability (DFT)ce.sharif.edu/courses/88-89/1/ce753-1/resources/root/Slides/lec23.pdf · Design for Testability (DFT) Test generation algorithms

Testability: Lecture 23Design for Testability (DFT)

Sh hi H biSh hi H biShaahin HessabiShaahin Hessabi

Department of Computer EngineeringDepartment of Computer Engineering

Sharif University of TechnologySharif University of Technology

Adapted, with modifications, from lecture notes prepared by the Adapted, with modifications, from lecture notes prepared by the p , , p p yp , , p p y

book authors book authors

Slide 1 of 43

Outline

Iterative Logic ArraysIterative Logic Arrays

AdAd--hoc DFT methodshoc DFT methods

Scan designScan designggDesign rulesDesign rules

Scan registerScan registerScan registerScan register

Scan flipScan flip--flopsflops

Scan test sequencesScan test sequences

OverheadsOverheads

Scan design systemScan design system

Slide 2 of 43Sharif University of Technology Testability: Lecture 23

Iterative Logic Arrays (ILAs)Some circuits are easy to test, for example, ILAsDefinition: An ILA is a k-dimensional array-like circuit composed e o s a d e s o a a ay e c cu co posedof identical cells with uniform interconnectionsArray circuits can be tested for powerful fault models using relatively few testsrelatively few testsExamples:

Arithmetic circuitsArithmetic circuits

Ripple-carry adders

Array multipliersArray multipliers

Bit-sliced processors

Random-access memories: RAMs, ROMsRandom access memories: RAMs, ROMs

ILA models of sequential circuits


Example 1: Ripple-Carry Adder

1D array composed of full-adder cells


Example 1: Ripple-Carry Adder (cont’d)

Assume the cell fault (CF) model, which implies that all i l l i f lt i ll li ti ill b d t t d

We must apply eight

single logic faults in all realizations will be detected.

patterns to every cell and observe the responses.

Six of the 8 patterns can be applied simultaneously to all cells; e.g., AiBiCi = 000

Faults in FAi can be observed via Si or Ci+1i i i+1

Two of the 8 patterns cannot be applied simultaneously to all cells, namely AiBiCi = 001 and 110, because Cin ≠ Cout


y i i i in out

Example 1: Ripple-Carry Adder (cont’d)p pp y ( )

The patterns AiBiCi = 001 and 110 b li d i l lcan be applied simultaneously to

alternating cellsAll CF f lt i bit RC ddAll CF faults in an n-bit RC adder can be detected by 8 tests, independent of the array size n.

The property of an n-cell ILA that all (cell) faults can be d d b b f i ll d

independent of the array size n.

detected by a constant number test patterns for any n is called C-testability


Example 2: Gate Array

This is an ILA realization of a kThis is an ILA realization of a k--input AND function, input AND function,

k k = = 11,,22,,33,,……

Question 1: Is an AND array C: Is an AND array C--testable?testable?

QuestionQuestion22: What if the AND function is replaced by : What if the AND function is replaced by XOR?XOR?


Design for Testability (DFT)Test generation algorithms for logic circuits are complex Test generation algorithms for logic circuits are complex (NP complete)(NP complete)(NP complete)(NP complete)

Circuits containing, say, Circuits containing, say, 101066 gates or gates or 101022 flipflip--flops, may flops, may be too large for ATPG toolsbe too large for ATPG toolsbe too large for ATPG toolsbe too large for ATPG tools

Heuristic methods are used for testing complex circuits Heuristic methods are used for testing complex circuits such as microprocessors RAMs etcsuch as microprocessors RAMs etcsuch as microprocessors, RAMs, etc.such as microprocessors, RAMs, etc.

Fault coverage of such methods can be low and hard to Fault coverage of such methods can be low and hard to dete minedete minedeterminedetermine

To ensure high levels of testability, design for testability To ensure high levels of testability, design for testability (DFT) i ft ti l(DFT) i ft ti l(DFT) is often essential(DFT) is often essential


Testability Goals1.1. Maximize fault coverageMaximize fault coverage

22 Minimize test application timeMinimize test application time2.2. Minimize test application timeMinimize test application time

3.3. Minimize test data sizeMinimize test data size

4.4. Minimize test generation effortMinimize test generation effort


DefinitionDesign for testabilityDesign for testability (DFT) refers to those design (DFT) refers to those design techniques that make test generation and testtechniques that make test generation and testtechniques that make test generation and test techniques that make test generation and test application costapplication cost--effective.effective.

DFT methods for digital circuits:DFT methods for digital circuits:DFT methods for digital circuits:DFT methods for digital circuits:

AdAd--hoc methodshoc methods

Structured methods:Structured methods:

ScanScanP i l SP i l SPartial ScanPartial ScanBuiltBuilt--in selfin self--testtest (BIST)(BIST)Boundary scanBoundary scanBoundary scanBoundary scan


DFTIn general, DFT deals with ways for improving In general, DFT deals with ways for improving controllability and observabilitycontrollability and observabilitycontrollability and observabilitycontrollability and observability

Costs associated with DFT:Costs associated with DFT:

Pins

Area/YieldArea/Yield

Performance

Design time


Objections to DFTj

Short-sighted view of management (schedule and costs)g g ( )

Life-cycle cost ignored by development management/contractors/buyersg / / y

Area/functionality/performance myths

Lack of knowledge by design engineersLack of knowledge by design engineers

Testing is someone else’s problem

L k f t l t t DFT (thi i i i )Lack of tools to support DFT (this is improving….)


Ad-Hoc DFT MethodsGood design practices learnt through experience are Good design practices learnt through experience are used as guidelines:used as guidelines:used as guidelines:used as guidelines:

Avoid asynchronous (Avoid asynchronous (unclockedunclocked) feedback. ) feedback. ((⇒⇒oscillation)oscillation)

Make flipMake flip--flops flops initializableinitializable. (. (clearclear or or presetpreset))

Avoid redundant gates. Avoid large fanAvoid redundant gates. Avoid large fan--in gates. in gates.

(controllability, observability)(controllability, observability)

Provide test control for difficultProvide test control for difficult--toto--control signals.control signals.Provide test control for difficultProvide test control for difficult toto control signals.control signals.

Avoid gated clocks.Avoid gated clocks.

C id ATE i t (C id ATE i t (t i t tt i t t t )t )Consider ATE requirements (Consider ATE requirements (tristatestristates, etc.), etc.)

Design reviews conducted by experts or design Design reviews conducted by experts or design diti t lditi t l


auditing tools.auditing tools.

Disadvantages of Ad-Hoc DFT Methods

Circuits are too large for manual inspection.Circuits are too large for manual inspection.

Experts and tools not always available.Experts and tools not always available.

Test generation is often manual with no guarantee of Test generation is often manual with no guarantee of g a o o a ua o gua a og a o o a ua o gua a ohigh fault coverage.high fault coverage.

Design iterations may be necessary.Design iterations may be necessary.Design iterations may be necessary.Design iterations may be necessary.

UUse of adse of ad--hoc DFT is usually discouraged for large hoc DFT is usually discouraged for large circuits.circuits.circuits.circuits.


Ad Hoc Design RulesPartitioningPartitioning

Insert control/observation points (Insert control/observation points (test pointstest points), e.g., a ), e.g., a reset line for initializationreset line for initialization

Avoid redundancyAvoid redundancy

Improve circuit structure, e.g., break global feedback Improve circuit structure, e.g., break global feedback during testingduring testing

Provide clock access during testingProvide clock access during testing


Partitioning (Divide and Conquer)

Physically divide the system into multiple chips or boards.Physically divide the system into multiple chips or boards.y y y p py y y p p

On boardOn board--level systems, use jumper wires to divide level systems, use jumper wires to divide subunits.subunits.subunits.subunits.

Has major performance penalties.Has major performance penalties.


Partitioning using Degating

Degating: another technique for separating modules on Degating: another technique for separating modules on ffchip/board with lower performance penalties.chip/board with lower performance penalties.

clock degating module partitioning


Test Point InsertionMake hardMake hard--toto--control internal signals controllable via extra control internal signals controllable via extra primary inputs and logic (CP = control points)primary inputs and logic (CP = control points)primary inputs and logic (CP = control points)primary inputs and logic (CP = control points)

Make hardMake hard--toto--observe internal signals observable via extra observe internal signals observable via extra primary outputs and logic (OP = observation points)primary outputs and logic (OP = observation points)primary outputs and logic (OP = observation points)primary outputs and logic (OP = observation points)


Test Point Insertion (cont’d)ControlControl--Point SitesPoint Sites

Clock linesClock linesClock linesClock linesGlobal reset linesGlobal reset linesInputs of stateInputs of state--control devicescontrol devicesLines of high fanLines of high fan--out (fanout (fan--out stems)out stems)Control (especially Control (especially tristatetristate control) lines of busescontrol) lines of busesAll bus lines in busAll bus lines in bus structured designsstructured designsAll bus lines in busAll bus lines in bus--structured designsstructured designsControl inputs to (embedded) RAMS and ROMsControl inputs to (embedded) RAMS and ROMsSome enable/hold/select control linesSome enable/hold/select control linesLines identified by testability measuring programs as having low Lines identified by testability measuring programs as having low controllabilitycontrollability


Test Point Insertion (cont’d)ObservationObservation--Point SitesPoint Sites

““BuriedBuried”” (not directly accessible) control/status lines(not directly accessible) control/status linesO t t f t tO t t f t t t l d it l d iOutputs of stateOutputs of state--control devicescontrol devicesLines of high fanLines of high fan--out (fanout (fan--out stems)out stems)Outputs of Outputs of high fanhigh fan--inin circuits, e.g. parity generatorscircuits, e.g. parity generatorspp gg , g p y g, g p y gLogically redundant nodesLogically redundant nodesGlobal feedback pathsGlobal feedback pathsOutput lines in busOutput lines in bus--structured designsstructured designsOutput lines in busOutput lines in bus--structured designsstructured designsLines identified by testability measuring programs as having low Lines identified by testability measuring programs as having low observabilityobservability

M i Li it tiM i Li it tiMain LimitationMain LimitationAvailability of (spare) input/output terminalsAvailability of (spare) input/output terminals

Add MUX’s to reduce number of I/O pinsAdd MUX s to reduce number of I/O pinsSerially shifts control point values

• Long testing time


Test Point Insertion (cont’d)Memory Control/ObservationMemory Control/Observation


DFT: Circuit Restructuring

Example: Counter DesignExample: Counter Design


DFT: Timing Control

Avoid asynchronous timingAvoid asynchronous timing

Make clocks observable and controllable during testingMake clocks observable and controllable during testing


Design Rule SummaryPartition large hardPartition large hard--toto--test circuits into small testable test circuits into small testable componentscomponentsDesign controllable (e.g. Design controllable (e.g. initializableinitializable) and observable units ) and observable units with careful selection of control/test pointswith careful selection of control/test pointsAllow global feedback paths to be opened/closedAllow global feedback paths to be opened/closedAllow global feedback paths to be opened/closedAllow global feedback paths to be opened/closedAvoid redundancy, or allow it to be overridden during Avoid redundancy, or allow it to be overridden during testingtestingggAvoid asynchronous circuits, provide access to clock signalsAvoid asynchronous circuits, provide access to clock signals

ConclusionsConclusionsOften ad hoc design modification is too late to significantly Often ad hoc design modification is too late to significantly improve a circuit's testabilityimprove a circuit's testabilityD l i l h f h d iD l i l h f h d iDevelop a systematic test plan at the start of the design Develop a systematic test plan at the start of the design processprocess


Scan DesignCircuit is designed using preCircuit is designed using pre--specified design rules.specified design rules.

Test structure (hardware) is added to the verified design:Test structure (hardware) is added to the verified design:

Add a Add a test controltest control (TC) primary input.(TC) primary input.

Replace flipReplace flip--flops by flops by scan flipscan flip--flopsflops (SFF) and connect to form one or (SFF) and connect to form one or

more shift registers in the test mode.more shift registers in the test mode.gg

Make input/output of each scan shift register controllable/observable Make input/output of each scan shift register controllable/observable

from PI/POfrom PI/POfrom PI/PO.from PI/PO.

Use combinational ATPG to obtain tests for all testable Use combinational ATPG to obtain tests for all testable faults in the combinational logicfaults in the combinational logicfaults in the combinational logic.faults in the combinational logic.

Add shift register tests and convert ATPG tests into scan Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing testsequences for use in manufacturing test


sequences for use in manufacturing test. sequences for use in manufacturing test.

Scan Design Rules1.1. Use only clocked DUse only clocked D--type of fliptype of flip--flops for all state variables.flops for all state variables.

At l t PI i (t t t l) t b il bl fAt l t PI i (t t t l) t b il bl f2.2. At least one PI pin (test control) must be available for At least one PI pin (test control) must be available for test; more pins, if available, can be used.test; more pins, if available, can be used.

All l k t b t ll d f PIAll l k t b t ll d f PI3.3. All clocks must be controlled from PIs.All clocks must be controlled from PIs.

4.4. Clocks must not feed data inputs of flipClocks must not feed data inputs of flip--flops.flops.


Correcting a Rule ViolationCorrecting a Rule ViolationAll clocks must be controlled from PIs.All clocks must be controlled from PIs.

Comb.logic

Comb.logic

D1

D2

Q

FFlogic

CK

Q

Comb.logic

Comb.logic

D1D2

CK

Q

FF


C

The Scan Concept


Scan Flip-Flop (SFF)

D Master latch Slave latch

TCQLogic

overhead

SD QMUX

CK D flip-flop

CK Master open Slave opent

TC (Test Control) Normal mode, D selected Scan mode, SD selectedt


Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)

Master latch Slave latch

DQ

Master latch Slave latch

MCK Q

SD

D flip-flopSCK

l

MCK

TCK

No

rma

lm

od

e

Logic

overhead

TCK MCK

TCK Sc

an

mo

de

Slide 30 of 43Sharif University of Technology Testability: Lecture 23tSCK

Adding Scan Structure

PI PO

SFF

SFF

Combinational

logic

SCANOUT

SFF

SFF

logic

SCANINTC or TCK Not shown: CK or

MCK/SCK feed all


SCANIN MCK/SCK feed allSFFs.

Tests for Full-Scan CircuitsTest generation for combinational logic only

Separate the test vectors and response data, based on PI, PO and state (F) variables: ti = tiI, tiF i = 1, 2, n

ri = riO, ri

F

Test application:1. Scan-in tiF by setting the circuit in test modei y g2. Apply tiI3. Observe ri

O

4. Set the circuit in functional mode and capture the response riF

into scan register5 Scan-out ri

F while scanning-in ti+1F by setting the circuit in test5. Scan out ri while scanning in ti+1 by setting the circuit in test

mode6. i i + 1. Go to 2


Combinational Test Vectors

I2I1 O1 O2PI PO

Combinational

logic

SCANINTC

SCANOUT

S2S1 N2N1Presentstate

Nextstate


Combinational Test Vectors (cont’d)Don’t careor random

I2I1PI bits

SCANIN S1 S2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0TC

O1 O2PO

SCANOUT N1 N2

Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectors


nsff = number of scan flip-flops

Testing StepsScan register must be tested prior to application of scan Scan register must be tested prior to application of scan test sequencestest sequencestest sequences.test sequences.

A shift sequence A shift sequence 00110011 00110011 . . . of length . . . of length nnsffsff++44 in scan mode in scan mode

(TC(TC 00) d) d 0000 0101 1111 dd 1010 i i i ll flii i i ll fli fl dfl d(TC=(TC=00) produces ) produces 0000, , 0101, , 11 11 and and 10 10 transitions in all fliptransitions in all flip--flops and flops and

observes the result at SCANOUT output.observes the result at SCANOUT output.

Covers most, if not all, single stuckCovers most, if not all, single stuck--at faults in FFs, andat faults in FFs, andverifies the correctness of the shift operation of the scan register.verifies the correctness of the shift operation of the scan register.

AddAdd nn ++44 to sequence length obtained in previous slide;to sequence length obtained in previous slide;Add Add nnsffsff++4 4 to sequence length obtained in previous slide;to sequence length obtained in previous slide;

Total scan test length: Total scan test length: ((nncombcomb + + 22) ) nnsffsff + + nncombcomb + + 4 4 clock periodsclock periods..

Example: Example: 22,,000 000 scan flipscan flip--flops, flops, 500 500 comb. vectors, total comb. vectors, total scan test length ~ scan test length ~ 101066 clocks.clocks.


Multiple scan registers reduce test length.Multiple scan registers reduce test length.

Multiple Scan RegistersMultiple scan registers reduce test length.Multiple scan registers reduce test length.

Scan flipScan flip--flops can be distributed among any number of shiftflops can be distributed among any number of shiftScan flipScan flip flops can be distributed among any number of shift flops can be distributed among any number of shift registers, each having a separate registers, each having a separate scaninscanin and and scanoutscanout pin.pin.

Sequence length is determined by the longest scan shiftSequence length is determined by the longest scan shiftSequence length is determined by the longest scan shift Sequence length is determined by the longest scan shift register.register.

OneOne test controltest control (TC) pin is essential (scanin and scanout for(TC) pin is essential (scanin and scanout forOne One test controltest control (TC) pin is essential (scanin and scanout for (TC) pin is essential (scanin and scanout for each chain can share PI and PO pins, respectively).each chain can share PI and PO pins, respectively).

SFF

Combinationallogic

PI/SCANIN PO/SCANOUT

MUX

SFFSFF

TC

Slide 36 of 43Sharif University of Technology Testability: Lecture 23CK

Scan Design Advantages/DisadvantagesAdvantages:Advantages:

1.1. By adding controllability/By adding controllability/observabilityobservability to the state variables, scan to the state variables, scan

design also eases functional testing.design also eases functional testing.

2.2. The testing problem is transformed from one of sequential circuit The testing problem is transformed from one of sequential circuit

testing to one of combinational circuit testing.testing to one of combinational circuit testing.

Disadvantages:Disadvantages:1.1. IO pins: One pin necessary.IO pins: One pin necessary.

2.2. Additional area for latches/FFs (Additional area for latches/FFs (area overheadarea overhead))

Gate overheadGate overhead = [= [4 4 nnsffsff/(/(nngg++1010nnffff)] x )] x 100100%%, where , where nngg = = comb. comb.

gatesgates; ; nnffff = = flipflip--flopsflops;;ffff

Example: Example: nngg = = 100100k gatesk gates, , nnffff = = 22k k flipflip--flopsflops, overhead = , overhead = 66..77%.%.

More accurate estimate must consider scan wiring and layout area.More accurate estimate must consider scan wiring and layout area.


o e accu ate est ate ust co s de sca g a d ayout a eao e accu ate est ate ust co s de sca g a d ayout a ea

Scan Design Advantages/Disadvantages

3.3. Additional time required to latch the next state into the Additional time required to latch the next state into the

i (i ( d h dd h d))resisters (resisters (speed overheadspeed overhead))

Multiplexer delay added in combinational path; approx. two Multiplexer delay added in combinational path; approx. two

gategate--delays.delays.

FlipFlip--flop output loading due to one additional fanflop output loading due to one additional fan--out; out;

approx. approx. 55--66%.%.

44 Additional time required to scan in/out test vectors andAdditional time required to scan in/out test vectors and4.4. Additional time required to scan in/out test vectors and Additional time required to scan in/out test vectors and

responses (responses (testing overhead)testing overhead)

Cl k ti d di t ib ti i diffi ltCl k ti d di t ib ti i diffi lt5.5. Clock generation and distribution is more difficult.Clock generation and distribution is more difficult.


ATPG Example: S5378

Original

2 781

Full-scan

2 781Number of combinational gates 2,781179

00 0%

2,7810

17915 66%

Number of combinational gatesNumber of non-scan flip-flops (10 gates each)Number of scan flip-flops (14 gates each)Gate overhead 0.0%

4,60335/49

70 0%

15.66%4,603

214/22899 1%

Gate overheadNumber of faultsPI/PO for ATPGFault coverage 70.0%

70.9%5,533 s

414

99.1%100.0%

5 s585

Fault coverageFault efficiencyCPU time on SUN Ultra II, 200MHz processorNumber of ATPG vectors 414

414585

105,662Scan sequence length


Automated Scan Design

Behavior, RTL, and logicBehavior, RTL, and logicDesign and verification

Scan designrule audits

Ruleviolations

Gate-levelnetlist

rule audits

Combinational Scan hard areCombinationalATPG

Scan hardwareinsertion

Scannetlist

Combinationalvectors

Chip layout: Scan-chain optimization,timing verification

Scan sequenceand test program

generation

netlistvectors

Scan chain order

timing verificationgeneration

Design and testdata for

manufacturing Mask dataTest program


manufacturing Mask dataTest program

Timing and Power

Small delays in scan path and clock skew can cause race Small delays in scan path and clock skew can cause race condition.condition.

Large delays in scan path require slower scan clock.Large delays in scan path require slower scan clock.

Dynamic multiplexers: Skew between TC and TC signals Dynamic multiplexers: Skew between TC and TC signals can cause momentary shorting of D and SD inputs.can cause momentary shorting of D and SD inputs.

Random signal activity in combinational circuit during Random signal activity in combinational circuit during scan can cause excessive power dissipation.scan can cause excessive power dissipation.


Summary

Scan is the most popular DFT technique:Scan is the most popular DFT technique:

RuleRule--based designbased design

Automated DFT hardware insertionAutomated DFT hardware insertion

Combinational ATPGCombinational ATPG

Advantages:Advantages:Advantages:Advantages:

Design automationDesign automation

h f l h l f l dh f l h l f l dHigh fault coverage; helpful in diagnosisHigh fault coverage; helpful in diagnosis

Hierarchical: scanHierarchical: scan--testable modules are easily combined into testable modules are easily combined into

large scanlarge scan--testable systemstestable systems

Moderate area (~Moderate area (~1010%) and speed (~%) and speed (~55%) overheads%) overheads


SummaryDisadvantages:Disadvantages:

Area overhead

Due to larger flip-flopsDue to extra routing

Possible performance degradation

Extra gate delay due to the multiplexerE i i l di d l d i i h fli flExtra capacitive loading delay due to scan wiring at the flip-flop output

Large test data volume and long test timeLarge test data volume and long test time

Basically a slow speed (DC) testBasically a slow speed (DC) test

Not applicable to all designs (e.g. asynchronous designs, designs

violating scan design rules)

High power dissipation during testing


High power dissipation during testing

Documents

Testability: Lecture 23 Design for Testability (DFT)ce.sharif.edu/courses/88-89/1/ce753-1/resources/root/Slides/lec23.pdf · Design for Testability (DFT) Test generation algorithms