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Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 1
Lecture 23Design for Testability (DFT):
Full-Scan (chapter14)
Lecture 23Design for Testability (DFT):
Full-Scan (chapter14) Definition Ad-hoc methods Scan design
Design rules Scan register Scan flip-flops Scan test sequences Overheads Scan design system
Summary
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 2
DefinitionDefinition
Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective.
DFT methods for digital circuits: Ad-hoc methods Structured methods:
Scan Partial Scan Built-in self-test (BIST) Boundary scan
DFT method for mixed-signal circuits: Analog test bus
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 3
Ad-Hoc DFT MethodsAd-Hoc DFT Methods Good design practices learnt through experience are
used as guidelines: Avoid asynchronous (unclocked) feedback. Make flip-flops initializable. Avoid redundant gates. Avoid large fanin gates. Provide test control for difficult-to-control signals. Avoid gated clocks. Consider ATE requirements (tristates, etc.)
Design reviews conducted by experts or design auditing tools.
Disadvantages of ad-hoc DFT methods: Experts and tools not always available. Test generation is often manual with no guarantee of
high fault coverage. Design iterations may be necessary.
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 4
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 5
TM=0 Normal operationTM=1 CONTROL OPERATION
Control PointInsertion
ObservationPointInsertion
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 6
Scan DesignScan Design Circuit is designed using pre-specified design
rules. Test structure (hardware) is added to the
verified design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect
to form one or more shift registers in the test mode. Make input/output of each scan shift register
controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all
testable faults in the combinational logic. Add shift register tests and convert ATPG tests
into scan sequences for use in manufacturing test.
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 7
Scan Design RulesScan Design Rules Use only clocked D-type of flip-flops for all
state variables.
At least one PI pin must be available for test; more pins, if available, can be used.
All clocks must be controlled from PIs.
Clocks must not feed data inputs of flip-flops.
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 8
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 9
Correcing a Rule ViolationCorrecing a Rule Violation All clocks must be controlled from PIs.
Comb.logic
Comb.logic
D1
D2CK
Q
FF
Comb.logic
D1D2
CK
Q
FF
Comb.logic
Q* = DC + CQ
Q* = D1D2Ck + (D2Ck )’Q= D1D2Ck + D2’Q +Ck’Q
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 10
Fixing BUS Conection
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 11
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 12
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 13
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 14
Scan Flip-Flop (SFF)Scan Flip-Flop (SFF)D
TC
SD
CK
Q
QMUX
D flip-flop
Master latch Slave latch
CK
TC Normal mode, D selected Scan mode, SD selected
Master open Slave opent
t
Logicoverhead
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 15
Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)
Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)D
SD
MCK
Q
Q
D flip-flop
Master latch Slave latch
t
SCK
TCK
SCK
MCK
TCK
Nor
mal
mod
e
MCK
TCK Sca
nm
ode
Logicoverhead
SCK
SCK
t
t
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 16
Adding Scan StructureAdding Scan Structure
SFF
SFF
SFF
Combinational
logic
PI PO
SCANOUT
SCANINTC or TCK Not shown: CK or
MCK/SCK feed allSFFs.
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 17
Comb. Test VectorsComb. Test Vectors
I2I1 O1 O2
S2S1 N2N1
Combinational
logic
PI
Present
state
PO
Nextstate
SCANINTC SCANOUT
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 18
Comb. Test VectorsComb. Test Vectors
I2I1
O1 O2
PI
PO
SCANIN
SCANOUT
S1 S2
N1 N2
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0TC
Don’t careor random
bits
Sequence length = (nsff + 1) ncomb + nsff + 4 + nsff clock periods= (ncomb + 2) nsff + ncomb + 4 clock perodncomb = number of combinational vectors
nsff = number of scan flip-flops
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 19
Testing Scan RegisterTesting Scan Register Scan register must be tested prior to
application of scan test sequences. A shift sequence 00110011 . . . of length
nsff+4 in scan mode (TC=0) produces 0 0, 0 1, 1 1 and 1 0 transitions in all flip-flops and observes the result at SCANOUToutput.
Total scan test length: (ncomb + 2) nsff + 4 + ncomb clock periods.
Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocks.
Multiple scan registers reduce test length.
A modulo-3 circuit with scan design and test generation ( Exm.14.1)
A modulo-3 circuit with scan design and test generation ( Exm.14.1)
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 20
Normal INPUTSR and C
OUTPUTR =1Q1Q2 = 00
C=1 , R=000 01 10 00 Z 0 0 1 0
C=R=0Q1
+ = Q1 , Q2+ =Q2
ATPG Program produces 12 Test vectors forCombinational part , with 4 inputs C,R,P1,P2 andThree outputs ,Z, Q1, Q2
Scan Circuit : test sequence = (12+2)2+4+12 =44
Fault simulation shows: all faults are detectedincluding 6 undetectable faults in original circuit
and Those in multiplexers
Non –Scan circuit [ 72] has42 Faults ;34 test vectors
detect 36 out of 42 Faults
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 21
Multiple Scan RegistersMultiple Scan Registers Scan flip-flops can be distributed among
any number of shift registers, each having a separate scanin and scanout pin.
Test sequence length is determined by the longest scan shift register.
Just one test control (TC) pin is essential.
SFFSFF
SFF
Combinationallogic
PI/SCANIN PO/SCANOUTM
UX
CK
TC
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 22
Scan OverheadsScan Overheads IO pins: One pin necessary. Area overhead: Gate overhead = [4 nsff/(ng)] x 100%, where
ng = comb. gates; nff = flip-flops; Example –ng = 100k gates, nff = 2k flip-flops, overhead = 8%.
More accurate estimate must consider scan wiring and layout area.
Performance overhead: Multiplexer delay added in combinational
path; approx. two gate-delays. Flip-flop output loading due to one additional
fan-out; approx. 5-6%.
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 23
Hierarchical ScanHierarchical Scan Scan flip-flops are chained within
subnetworks before chaining subnetworks. Advantages:
Automatic scan insertion in netlist Circuit hierarchy preserved – helps in
debugging and design changes Disadvantage: Non-optimum chip layout.
SFF1
SFF2 SFF3
SFF4SFF3SFF1
SFF2SFF4
Scanin Scanout
ScaninScanout
Hierarchical netlist Flat layout
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 24
Optimum Scan LayoutOptimum Scan Layout
IOpad
Flip-flopcell
Interconnects
Routingchannels
SFFcell
TC
SCANIN
SCANOUT
Y
X X’
Y’
Active areas: XY and X’Y’
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 25
Scan Area OverheadScan Area OverheadLinear dimensions of active area:
X = (C + S) / rX’ = (C + S + S) / rY’ = Y + ry = Y + Y(1--) / T
Area overheadX’Y’--XY
= -------------- x 100%XY
1--= [(1+s)(1+ -------) – 1] x 100%
T
1--= (s + ------- ) x 100%
T
y = track dimension, wirewidth+separation
C = total comb. cell widthS = total non-scan FF cell
widths = fractional FF cell area
= S/(C+S) = SFF cell width fractional
increaser = number of cell rows
or routing channels = routing fraction in active
areaT = cell height in track
dimension y
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 26
Example: Scan LayoutExample: Scan Layout 2,000-gate CMOS chip Fractional area under flip-flop cells, s = 0.478 Scan flip-flop (SFF) cell width increase, = 0.25 Routing area fraction, = 0.471 Cell height in routing tracks, T = 10 Calculated overhead = 17.24% Actual measured data:
Scan implementation Area overhead Normalized clock rate______________________________________________________________________
None 0.0 1.00
Hierarchical 16.93% 0.87
Optimum layout 11.90% 0.91
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 27
ATPG Example: S5378ATPG Example: S5378
Original
2,781179
00.0%
4,60335/49
70.0%70.9%
5,533 s414414
Full-scan
2,7810
17915.66%4,603
214/22899.1%
100.0%5 s
585105,662
Number of combinational gatesNumber of non-scan flip-flops (10 gates each)Number of scan flip-flops (14 gates each)Gate overheadNumber of faultsPI/PO for ATPGFault coverageFault efficiencyCPU time on SUN Ultra II, 200MHz processorNumber of ATPG vectorsScan sequence length
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 28
Automated Scan DesignAutomated Scan DesignBehavior, RTL, and logicDesign and verification
Gate-levelnetlist
Scan designrule audits
CombinationalATPG
Scan hardwareinsertion
Chip layout: Scan-chain optimization,timing verification
Scan sequenceand test program
generation
Design and testdata for
manufacturing
Ruleviolations
Scannetlist
Combinationalvectors
Scan chain order
Mask dataTest program
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 29
Timing and PowerTiming and Power
Small delays in scan path and clock skew can cause race condition.
Large delays in scan path require slower scan clock.
Dynamic multiplexers: Skew between Ck and TC signals can cause momentary shorting of D and SD inputs.
Random signal activity in combinational circuit during scan can cause excessive power dissipation.
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 23 30
SummarySummary Scan is the most popular DFT technique:
Rule-based design Automated DFT hardware insertion Combinational ATPG
Advantages: Design automation High fault coverage; helpful in diagnosis Hierarchical – scan-testable modules are easily
combined into large scan-testable systems Moderate area (~10%) and speed (~5%) overheads
Disadvantages: Large test data volume and long test time Basically a slow speed (DC) test