What is SOI

8/10/2019 What is SOI

1/12

IC TECHNOLOGY

TERM PAPER

SILICON-ON-INSULATOR

BY: AKSHAT SINGH

B.TECH ECE

11004367


2/12

What is SOI?

With Silicon-On-Insulator (SOI) wafers, transistors are formed in thin layers of siliconthat are isolated from the main body of the wafer by a layer of electrical insulator,usually silicon dioxide. The silicon layer thickness ranges from several microns for

electrical power switching devices to less than 500 for high-performancemicroprocessors.Isolating the active transistor from the rest of the silicon substrate reduces the electricalcurrent leakage that would otherwise degrade the performance of the transistor. Sincethe area of electrically active silicon is limited to the immediate region around thetransistor, switching speeds are increased and sensitivity to "soft errors", a majorconcern for large-scale data storage and high-volume servers, is greatly reduced.

SOI Fundamentals

Silicon-On-Insulator (SOI) is a new way of starting the chip making process, by

replacing the bulk silicon wafers (approximately 0.75 mm thick) with wafers which havethree layers; a thin surface layer of silicon (from a few hundred Angstrom to severalmicrons thick) where the transistors are formed, an underlying layer of insulatingmaterial and a support or "handle" silicon wafer. The insulating layer usually made ofsilicon dioxide and referred to as the "buried oxide" or "BOX", is usually a few thousand

Angstroms thick. When transistors are built within the thin top silicon layer, they switchsignals faster, run a lower voltages and much less vulnerable to signal noise frombackground cosmic ray particles. Since on an SOI wafer each transistor is isolated fromits neighbor by a complete layer of silicon dioxide, they an immune to "latch-up"problems and can spaced closer together than transistors built on bulk silicon wafers.Building circuits on SOI allows for more compact chip designs, resulting in smaller IC

devices (with higher production yield) and more chips per wafer (increasing fabproductivity).

Why is SOI important?

SOI enables increased chip functionality without the cost of major process equipmentchanges (such as higher resolution lithography tools). The advantages of IC devicesbuilt on SOI wafers (mainly faster circuit operation and lower operating voltages) haveproduced a powerful surge in the performance of high-speed network servers and newdesigns for hand-held computing and communication devices with longer battery life.

Advanced circuits, using multiple layers if SOI-type device silicon, can led the way to a

coupling of electrical and optical signal processing into a single chip resulting in adramatic broadening of communication bandwidth with new applications such as globalranging, direct-link entertainment and communication to hand-held devices. Some typesof SOI devices, using radiation-resistant buried insulators, will increase the reliabilityand functionality of communication satellites and other orbiting and deep-spacesystems. SOI devices also extend the operating range of silicon devices to hightemperature environments such as built in diagnostics and controls for automotive andother combustion engines.


3/12


4/12

processing and allows operation at lower drive voltages. The core circuit of CMOS ICsis an inverter, consisting of a linked pair of complementary transistors. On a bulk siliconwafer, the transistors are formed in a pair of doped "wells". On an SOI wafer, thetransistors are formed in a thin silicon layer insulated by a thick buried oxide (or "BOX").Because of the increased efficiency of the SOI device isolation the surface area of the

circuit can reduce, allowing for smaller die size and increased device count per wafer.

Figure 2:CMOS inverter transistors on bulk silicon and SOI wafers sketched with thesame gate size (critical dimensions). The smaller size of the SOI inverter is due to the

more efficient isolation of SOI transistors.


5/12

The principal advantages of electrical devices fabricated in SOI wafers are:

A 20% to 50% increase in switching speed compared to similar circuits built onconventional "bulk" silicon wafers.

The ability to operate at lower voltages (less battery power drain and chipheating). Events from cosmic ray particle showers (reducing the need for error correction

operations in high-speed data flow servers and memory arrays). Increased circuit packing due to simplification of the lateral and vertical isolation

structures, increasing chip yield and die count per wafer.

Even though the widespread use of SOI materials is relatively recent, the range ofapplications and types of SOI wafers is extensive. The thickness of the top Si layerranges from several microns for MEMS (Micro Mechanical- Electrical Systems) andsensors to a few hundred Angstroms for fully-depleted CMOS transistors. BOX

thickness range from 500 Angstroms to several microns. The thickness of the SOIlayers is determined by voltage isolation and device scale requirements.

Figure 3: SOI layer thickness for various applications.


6/12

Types of SOI-CMOS transistors are characterized by the thickness of the Si-SOI layer.For partially-depleted SOICMOS, the device Si layer is thicker than the depletion layerunder the channel, in the range of 100 to 200 nm. As CMOS gates are scaled to 5-65nm and smaller, CMOS devices will be formed in thin Si layers which are fully depletedin the channel region between the sources and drain junctions. For fully-depleted

CMOS, the Si device layer is of the order of 50 nm and shrinking towards 10 nm, or the"nano-SOI" regime. Fully-depleted CMOS devices will take advantage of the ability ofadvanced SOI fabrication processes (such as NanoCleave) to provide wafers capableof forming dual-gate transistors, with control gates both above and below the thinchannel.

On a more fundamental level, SOI wafers provide the most viable path for extension of

CMOS-VLSI transistor circuits beyond the "end of the roadmap" barriers detailed in theITRS99 (International Technology Roadmap for Semiconductors-1999) for planarCMOS on bulk silicon wafers. The large numbers of basic problems with continuingscaling of conventional CMOS on bulk wafers are expected to become limiting factorsfor gate sizes less than 65 nm, zanticipated to be the scale of leading product by 2006.By using thin (less than 500 A) silicon SOI layers, research


7/12

CMOS transistors have already been fabricated with excellent performance with 25 nmgates. According to the ITRS schedule, CMOS gates of 25 nm are expected to becharacteristic of advanced technology circuits by 2014.

Figure 5: The International Technology Roadmap for Semiconductors (ITRS99)projects a steady decrease in gate size and CMOS junction depths with time. The

limitations of planar CMOS transistors are projected to reach crisis proportions at andbelow a gate size of 65 nm in 2006-2008. After this time (and transistor scale), most

advanced transistors are expected to use fully-depleted, dual-gate architectures on SOIwafers.

The principal technology advances needed for the migration of CMOS devices to SOIwafers are:

Fabrication techniques for high quality SOI wafers; and Modification of transistor designs to take account of the special characteristics of

SOI layers.

The requirements for circuit modification for SOI are minimized by using a "partiallydepleted" SOI transistor on relatively thick (1000 to 2000 A) device silicon, such as theproduction conditions used by IBM. Many circuit development groups are working on"fully depleted" CMOS, where the full circuit advantages of SOI are realized, withproduction introductions scheduled in 2001 through 2005. After the "end of roadmap"


8/12

scaling to sub-65 nm gates, the majority of advanced technology CMOS transistors willbe fully depleted SOI. The successful fabrication of high quality SOI wafers depends ondevelopment of second-generation technologies, such as SiGen's NanoCleave process.Full adoption of SOI technologies will follow with the expansion of SOI wafer fabricationcapacity and the resulting reductions in wafer cost and increased range of available SOI

wafer types.

Advantages of SOI technology

Ionizing mediums Insulation Elimination of parasitic thyristor Reduction of drain /source junction Operating in high temperature Three-dimensional integration Reduction of short channel effects Saturation current is high than MOS/Si Transistor Reduction of carriers effects Reduction of substrate polarization effect.

II. Fabrication of SOI wafers

Many techniques have been developed for producing a film of single-crystal silicon ontop of insulator. Some of them are based on the epitaxial growth of silicon on either a

silicon wafer covered with an insulator (homo-epitaxial techniques) or on a crystallineinsulator (hetroepitaxial techniques). Other techniques are based on recrystallization ofthin silicon layer from the melt (laser recrystallization, e beam recrystallization and zone-melting recrystallization). Silicon-on-insulator can also be produced from a bulk siliconwafer by isolating a thin silicon layer from the substrate through the formation andoxidation of porous silicon (FIPOS) or through the ion beam synthesis of a buriedinsulator layer(SIMOX, SIMNI and SIMON). Finally, SOI material can be obtained bythinning a silicon wafer boned to an insulator and mechanical substrate (wafer bondingBESOI). Every approach has its advantages and its pitfall, and the type of application towhich the SOI materials is destined, dictates the material to be used in each particularcase. SIMOX and UNIBOND are seems to be the ideal candidates for VLSI CMOS

application, while wafer bonding is more adapted to bipolar and power applications.Now well review some of the techniques have been used in producing the SOImaterials.

Hetro-epitaxial Techniques:Hetro-epitaxial Silicon-on-insulator films are obtained byepitaxially growing a silicon layer on a single crystal insulator (see figure 6). The filmsare grown using silane or dichlorosilane at temperatures around 10000C. All theinsulating substrates have thermal coefficients which are 2- 3 times higher than that of


9/12

silicon which generated lot of stresses at interface. Therefore, thermal mismatch is thesingle most important factor determining the physical and electrical properties of siliconfilms grown on bulk insulators. Silicon-on-sapphire (SOS) is one of single most matureof all Hetro-epitaxial materials used. SOS is fabricated by epitaxial growth of a Si film on

Al2O3. The electrical properties may suffer from lateral stress, in-depth in homogeneity

of the film, and defective transition layer at the interface. Good quality 100 nm thickfilms, on 6 in. SOS wafers are now available.

Homo-epitaxial techniques: Epitaxial lateral overgrowth, method consists of growing asingle crystal Si film, from the substrate (i.e. the seed) through and above the SiO2layer. ELO process requires a post-epitaxy thinning of the Si film, which can for examplebe achieved by using a patterned oxide, the silicon film in excess is removed leaving anisolated Si island (dotted line) in the BOX. The main application of ELO technique is theintegration of 3-D stacked circuits.

Figure 6:ELO technique. A) Growth from seeding window B) Coalescence of adjacentcrystals C) Self-planarization of the surface.

Recrystallization Techniques: MOS transistor can be fabricated on large grainedpolysilicon deposited on oxidized silicon substrate. But the presence of grain boundariesbrings about low surface mobility and high thershould voltages. Mobility and thershouldvoltages values can be improved by passivating the dandling silicon bond via hydrogen


10/12

plasma treatment. High performance ICs however require much better deviceproperties, and grain boundaries must be eliminated from the deposited silicon film. Thisis the goal of all recrystallization techniques such as Laser beam, E-Beam, zone meltrecrystallization. Laser and e-beam both are relatively slow processes (uses a pointedenergy source) compared to zone melting method in which incoherent light or near IR

source is used.

FIPOS:In Full isolation by oxidized porous silicon anodic reaction is used to convert aparticular region (predefined by p-type doping) of the Si wafer into porous silicon. Duringsubsequent oxidation, the porous Si transforms very rapidly and selectively in a BOX.FIPOS may be able, in the future, to combine SOI circuits with electroluminescentporous Si devices.

SIMOX: In the last decade, the dominant SOI technology was SIMOX, which issynthesized by internal oxidation during the deep implantation of oxygen ions into a Siwafer. Annealing at high temperature restores the crystalline quality of the film. SIMOX

8 in. wafers have good thickness uniformity, low defect density (except threadingdislocations: 104106 cm-2), sharp SiSiO2 interface, robust BOX, and high carriermobility. Some basic processes of SIMOX are described in figure 7 and figure 8.

Figure 7:The principal of SIMOX: a heavy dose oxygen implantation into siliconfollowed by an annealing step produces a buried layer of silicon dioxide below a thin

single crystal silicon overlayer.


11/12

Figure 8:Evolution of the structure of the SIMOX structure as function of post-

annealing temperature (implant dose= 1.5 1018 cm-2, energy = 200 keV). A) Asimplanted, B) 2-hr. annealing at 11500C, C) 6 hour annealing at 11850C, D) 6 Hr.

Annealing 13000.

Wafer bonding (WB): Wafer bonding and etch back is another mature SOI technology.An oxidized Si wafer is mated to a second Si wafer. When two flat, hydrophilic surfacessuch as oxidized surfaces are placed against one another, bonding naturally occurs,even at room temperature, which forms the hydrogen bonds across the gap betweentwo surfaces. After bonding, upper wafer is thinned down from 600microns to fewmicrons to reach the target thickness of the silicon film. The thinning is usually donegrinding followed by chemical polishing or grinding followed by etch-back process(preferred). In etch-back process a P+ layer is formed at the surface near the oxidewhere the etching is required and using proper etchant the bare Si surface above thebonded SiO2 is obtained with approximately 12nm surface tolerance.

UNIBOND:This material again belongs to the family of wafer bonding structures. Butunlike the wafer bonding method, in UNIBOND, the etch back process is avoided. Therevolutionary Smart- Cut mechanism uses the deep implantation of hydrogen (dottedline in figure 9) to generate micro cavities. After bonding and annealing, the wafersseparate naturally at a depth defined by the location of hydrogen micro cavities whichhave eventually coalesced. The UNIBOND wafer is finished by touch polishing. Thesmart-cut approach has several outstanding advantages: no etch-back step, with muchbetter uniformity of surface (0.15nm) the prime-quality wafer A is fully recyclable andUNIBOND reduces to a single wafer process, only conventional equipment is neededfor mass production, relatively inexpensive wafers are manufacturable, and unlimitedcombinations of BOX and film thicknesses can be achieved in order to match mostdevice configurations (ultra-thin CMOS or thick-film power transistors and sensors). Thedefect density in the film is very low, the electrical properties are excellent, and the BOXquality is comparable with that of the original thermal oxide. It is worth noting that thetwo interfaces of the BOX are ideally organized: the top interface (filmBOX) has the


12/12

high quality expected from thermal oxidation whereas the bonded interface, of poorerquality, is located underneath the BOX and has little influence on the SOI deviceperformance. A fascinating aspect is that the smart-cut process is adaptable to a varietyof materials: SiC or IIIV compounds on insulator, silicon on diamond or glass, etc. Thepossibility to enroll, in the SOI-based microelectronics, these materials with large band

gap, photonic, or high-temperature capabilities opens exciting prospects for theintegration of totally new types of devices.

Figure 9:UNIBOND Process flow, created by 'Michel BRUEL from LETI

Documents

What is SOI