Implementation of SOI MOSFET using Silvaco TCAD … · Implementation of SOI MOSFET using Silvaco TCAD Reduction of KINK Effect and Frequency Response ... is that in PD SOI devices,

International Journal of IT, Engineering and Applied Sciences Research (IJIEASR) ISSN: 2319-4413 Volume 4, No. 6, June 2015

i-Explore International Research Journal Consortium www.irjcjournals.org

72

Implementation of SOI MOSFET using Silvaco TCAD

Reduction of KINK Effect and Frequency Response

Er. Harisharan Aggarwal (C.I Engg.) HOD ECE, Guru Kashi Univeristy, Talwandi Sabo

Er. Jaspreet Singh, Student, Guru Kashi Univeristy, Talwandi Sabo

ABSTRACT

With the Emergence of Advancement of mobile computing,

Industrial automation, low power device design and

Implementation have got a significant role to go through

Embedded design.

Silicon-On-Insulator (SOI) technology is one such

alternative which can offer the performance as may be

expected from next generation Si technology. In spite of

advantages of SOI devices several limitations like “Kink”

in the output current-voltage characteristics, self-heating

effect exhibits improved static & Dynamic & thermal

behavior etc,

The device is found to have reduced parasitic

capacitances which lead to an enhancement in the

frequency response and eliminate the kink effect SELBOX

method has been designed. In this method, back oxide for

the device is introduced at selected regions below the

source and drain. Selective back oxide structure with

different gap lengths and thicknesses has been studied.

Simulation of SELBOX structure using Silvaco Atlas has

been performed. It is found that the kink in the output

characteristics for a 0.4 μm thick partially depleted SOI

MOSFET can be virtually eliminated with a very narrow

gap of (0.001-0.2) μm in back oxide. The effect of gap

length and SELBOX thickness has been investigated.

Results obtained the effeteness of the structure for the

minimization of the self heating effect observed in SOI

structure.

Keywords: SOI MOSFET, Kink effect, SELBOX, Self Heating

Effect, Thermal Circuit

I INTRODUCTION

As the device count in an IC is running into billions per

chip, the issue of power dissipation in the chip is

becoming one of the two most important issues (other

being the speed). The ever decreasing device dimensions

have reached a state where the performance of the bulk Si

MOSFETs is limited by the fundamental physical limits

such as reduction in carrier mobility due to impurities,

increasing gate tunneling effect as the gate oxide thickness

decreases and increasing p-n junction leakage current as

the junctions become more and more shallow. A low

operating voltage is a necessity as reduced power

consumption is aimed at. These requirements have led to

development of alternative technologies. SOI technology

is one such alternative which can offer a performance as

expected from next generation Si technology.

According to the Moore law which states that the

performances of processors are doubled every 18 month.

Increasing the number of device count means decreasing

the space and hence increasing the switching speed of the

device. Two most important criteria used for measuring

the performance of a circuit is speed and area. However

due to increased transistor density and the need of portable

devices most important cost measure in VLSI design is

power consumption. SOI technology utilizes the low

power technique. Most of the early SOI devices were

fabricated with SOS (Silicon On Sapphire) wafers. The

unique feature of today’s SOI wafer is that they have a

buried silicon oxide or BOX layer extending across the

entire wafer. Introducing a BOX structure in traditional

MOS structure brings a lot of improved characteristic such

as excellent isolation, reduced short channel effects,

reduced leakage current, improved latch up free operation,

radiation hardness, and improved switching speed due to

reduction in the drain body capacitance. SOI CMOS

technology is likely to be an alternative for deep sub-

micron CMOS [1]. It appears to be the best option for low-

power electronics.

Silicon on insulator (SOI) wafers is precisely engineered

multilayer semiconductor/dielectric structures which

provide superior functionality for various applications.

II PROBLEM DEFINITION

Reduction in carrier mobility due to impurity.

Increasing gate tunneling effect as the gate oxide

thickness decreases.

Increasing p-n junction leakage current as the

junction become more and more shallow.

III CRITICAL ANALYSIS

The worth noting point over all the above literature survey

is that in PD SOI devices, the thickness of top Si layer is

around 300 nm. The fabrication process for such devices is

totally compatible with that of the bulk silicon technology.

As a result, the design for bulk silicon devices can be

easily transferred to PD SOI technology. Fabrication of

FD SOI devices involves development of ultrathin body



73

and, therefore, needs more sophisticated technology. The

threshold voltage in PD SOI devices is relatively less

sensitive to the uniformity in the silicon film thickness. In

FD SOI device, the threshold voltage depends on the Si

film thickness. It is difficult to control the thickness of the

ultra thin film body in FD SOIMOSFETS, and as a result,

the film thickness becomes nonuniform across the wafer.

For these reasons, there has been a growing interest in PD

SOI MOSFETs.

In spite of these benefits, PD-SOI MOSFET devices are

accompanied with certain undesirable effects such as kink

in the output current-voltage characteristics. In these

devices, the electric field near the drain region will be high

due to relatively higher drain voltages. Consequently, the

channel electrons in the high electric field acquire high

energy and create electron-hole pairs by impact ionization

mechanism. The generated electrons are collected by the

drain and the holes accumulate in the floating body. The

accumulation of the holes in the floating body leads to an

increase in the body potential, and the associated drop in

the threshold voltage leads to a sharp increase in the drain

current. The increase in drain current further leads to an

increase in the number of holes generated. This cumulative

process will continue until the body source junction is

forward biased, allowing the holes to exit the device.

Consequently, the device will not be suitable for linear

applications due to the nonlinearity created by the kink

effect.

The second observation is that SOI devices are thermally

insulated from the substrate by the buried insulator with

very low thermal conductivity. As a result, removal of

excess heat generated within the device is less efficient

than in bulk devices. This leads to a substantial elevation

of device temperature and a reduction in the channel

mobility.

IV OPERATION OF AN SOI MOSFET

The structure of an SOI MOSFET, as shown in figure 1.1

is similar to the conventional bulk MOSFET with the

exception that the active silicon layer is separated from the

bulk silicon substrate by a thick buried oxide layer.

Figure: 1.1 Structure of an SOI MOSFET

Depending on the silicon film thickness and the channel

doping concentration, two types of SOI MOSFETs can be

distinguished

a) Thick film SOI

b) Thin film SOI

In a thick-film SOI device the silicon film thickness is

larger than twice the maximum depletion width,

xdmax = 4∈si ɸF

q NA ..(1.1)

Where,

ΦF is the fermi potential as given below:

ɸ𝐹 = 𝑘𝑇

𝑞 ln

𝑁𝐴

𝑛𝑖 ..(1.2)

As a result, there is no interaction between the depletion

zones arising from the back and front interfaces, and a

neutral body of silicon piece exists beneath the front

depletion zone. If we connected it to ground through a

body contact, the device operations will same as of a bulk

device. When the body is left electrically floating, it will

behave as a bulk device, excepting the floating body

effects.

Figure: 1.2 Band Diagram in a bulk (A), a thick-film

SOI (B), and a thin-film SOI Device (C)

In a thin-film SOI device the silicon film thickness is

smaller than X d max. The silicon film is fully depleted at

threshold, irrespective of the back-gate bias (with the

exception of a possible presence of thin accumulation or

inversion layers at back interface, if a large negative or

positive bias is applied at the back gate, respectively).

Among all SOI MOSFETs, fully depleted SOI devices

having back interface depleted, which exhibit the most

attractive properties, such as low electric fields, excellent

short channel behavior, a quasi-ideal subthreshold slope

and high trans-conductance.

Medium thickness SOI device is an intermediate case

between thin and thick film device, and is obtained when

Xdmax < tsi < 2Xdmax being the film thickness. If the back

gate bias causes the front and back depletion zones to



74

coalesce, the device behaves like a thin film device;

otherwise it behaves as a thick-film device.

In PD MOSFET, a part of the body region remains

undepleted or neutral while in FD MOSFET, whole of the

body, the depletion region extends right up-to the body

and BOX interface. Thus in FD SOI MOSFET, the

complete body region is depleted off majority carriers.

Figure: 1.3 Structures of (a) Partially-Depleted and

Fully-Depleted SOI MOSFET

In PD MOSFET, a part of the body region remains

undepleted or neutral while in FD MOSFET, whole of the

body, the depletion region extends right up-to the body

and BOX interface. Thus in FD SOI MOSFET, the

complete body region is depleted off majority carriers.

V OBJECTIVES

The objective of this thesis is to verify the Kink effect in

the output characteristics of a SOI MOSFET using Silvaco

TCAD simulator. Reduction of the kink effect has been

carried out by using the SELBOX structure. MOSFET,

SOI MOSFET & SELBOX structure have been

implemented in the present work. SELBOX structure is

needed to be optimized in order to get the gap length

which can eliminate the kink as well as retains the

characteristics of the SOI MOSFET. For increase in the

gap lengths to large values the device remains kink free

but tends to behave more like a bulk MOSFET and thus

less likely to have other advantages associated with SOI.

VI RESEARCH METHODOLOGY

For the modeling and simulations of the Silicon-on-

insulator device, we use three of the main Silvaco TCAD

programs:

1. The first is Deck build, which is the software that

runs the code, and provided the interface for

changing and altering the code.

2. Another is TONYPLOT, which is used for graphing

the data extracted from the simulation.

3. The main program used in the simulation is Atlas,

which is use to actually simulate the SOI device and

to extract the data.

ATLAS is a physically-based two and three dimensional

device simulator. It predicts the electrical behavior of

specified semiconductor structures and provides insight

into the internal physical mechanisms associated with

device operation.

Figure : 1.4 ATLAS Graphical Structural View [39]

To run the Silvaco TCAD first it need the local server.

After getting the local server one can open the Deckbuild

for writing the command for making a structure, process

simulation and numerical calculation. The window version

TCAD is used here for the process simulation which

utilizes the ATLAS Device Simulator.

Figure 1.5: Server status

The order in which statements occur in an ATLAS input

file is important. There are five groups of statements that

must occur in the correct order. Failure to do so usually

causes an error message to appear, which could lead to



75

incorrect operation or termination of the program. For

example, if the material parameters or models are set in

the wrong order, then they may not be used in the

calculations.

Figure 1.6 Deckbuild Environment

The order of statements within the mesh definition,

structural definition, and solution groups is also important.

Failure to place these statements in proper order may also

cause incorrect operation or termination of the program.

Table: 1.1 ATLAS Design Flow

Group Statements

1. Structure

Specification

Mesh, Region,

Electrode, Doping

2. Material Models

Specification

Materials, Models,

Contacts, Interface

3. Numerical Method

Selection

Method

4. Solution Specification Log, Solve, Load,

Save

5. Result Analysis Extract Tonyplot

VII STRUCTURE SPECIFICATION

To define a device through the ATLAS command

language, we must first define a mesh. This mesh or grid

covers the physical simulation domain. The mesh is

defined by a series of horizontal and vertical lines and the

spacing between them. Then, regions within this mesh are

allocated to different materials as required to construct the

device. For example, the specification of a MOS device

requires the specification of silicon and silicon dioxide

regions. After the regions are defined, the location of

electrodes is specified. The final step is to specify the

doping in each region.

VIII SPECIFYING THE INITIAL MESH

The mesh is a series of horizontal and vertical lines that

form a grid, or mesh, which defines the area where the

device will be built. Each spot where the lines cross is a

point where the program will analyze the structure, so the

lines should cross frequently in areas of interest, and less

frequently in areas where the structure is less active. The

first statement must be:

MESH SPACE.MULT=<VALUE>

This is followed by a series of X.MESH and Y.MESH

statements.

X.MESH LOCATION=<VALUE>

SPACING=<VALUE>

Y.MESH LOCATION=<VALUE>

SPACING=<VALUE>

The SPACE.MULT parameter value is used as a scaling

factor for the mesh created by the X.MESH and Y.MESH

statements. The default value is 1. Values greater than 1

will create a globally coarser mesh for fast simulation.

Values less than 1 will create a globally finer mesh for

increased accuracy. The X.MESH and Y.MESH

statements are used to specify the locations in microns of

vertical and horizontal lines, respectively, together with

the vertical or horizontal spacing associated with that line.

For MOSFET, SOI & SELBOX structure same grid has

been specified:

X = 0 to 3 micron with proper spacing &

Y = -0.017 to 0.7 micron, where at -0.017 micron gate has

been structured.

Figure 1.7 Grid View



76

IX SPECIFYING REGIONS Once the mesh is specified, every part of it must be

assigned a material type. This is done with REGION

statements.

REGION number=<integer> <material_type>

<position parameters>

Region numbers must start at 1 and are increased for each

subsequent region statement.

The position parameters are specified in microns using the

X.MIN, X.MAX, Y.MIN, and Y.MAX parameters.

Defining the Region

1. For MOSFET structure two regions are defined one

is for the oxide layer & another one for the

substrate layer

Region 1(Oxide): From -0.017 to 0 micron mesh

location in y direction

Region 2 (Silicon): From 0 to 0.7 micron mesh


2. For SOI structure three regions are defined

Region 1 (Oxide): From -0.017 to 0 micron mesh


Region 2 (silicon): From 0 to 0.7 micron mesh


Region 3 (Oxide): From 0.2 to 0.4 micron mesh


3. For SELBOX structure

Region 1 (Oxide): From -0.017 to 0 micron mesh


Region 2 (Silicon): From 0 to 0.7 micron mesh



location in y direction & From 0 to 1.5

micron mesh location in x direction


location in y direction & From 1.6 to 3

micron mesh location in x direction.

X SPECIFYING ELECTRODES

Once we have specified the regions and materials, define

at least one electrode that contacts a semiconductor

material. This is done with the ELECTRODE statement.

ELECTRODE NAME=<electrode name>

<position_parameters>

We can specify up to 50 electrodes. The position

parameters are specified in microns using the X.MIN,

X.MAX, Y.MIN, and Y.MAX parameters. Multiple

electrode statements may have the same electrode name.

Nodes that are associated with the same electrode name

are treated as being electrically connected.

Defining the electrode:

For all structure the electrode location and its definition is

kept constant

Electrode 1 (Gate): x= 1 to 2 micron location & y=

-0.017 to -0.017

Electrode 2 (Source): x= 0 to 0.5 micron location &

y= 0 to 0

Electrode 3 (Drain): x= 2.5 to 3 micron location &

y= 0 to 0

XI MATERIAL MODELS

SPECIFICATION

Setting Parameters

The MATERIAL statement allows you to specify your

own values for these basic parameters. Your values can

apply to a specified material or a specified region. For

example, the statement:

MATERIAL MATERIAL=Silicon EG300=1.12

MUN=1100

Sets the band gap and low field electron mobility in all

silicon regions in the device. If the material properties are

defined by region, the region is specified using the

REGION or NAME parameters in the MATERIAL

statement.

MATERIAL REGION=2 TAUN0=2e-7 TAUP0=1e-5

Sets the electron and hole Shockley-Read-Hall

recombination lifetimes for region number two.

XII OBTAINING SPECIFICATION

Obtaining solutions is rather analogous to setting up

parametric test equipment for device tests. We define the

voltages on each of the electrodes in the device. ATLAS

then calculates the current through each electrode. ATLAS

also calculates internal quantities, such as carrier

concentrations and electric fields throughout the device.

This is information that is difficult or impossible to

measure.

In all simulations, the device starts with zero bias on all

electrodes. Solutions are obtained by stepping the biases

on electrodes from this initial equilibrium condition.

ATLAS due to the initial guess strategy, voltage step sizes

are limited.

Transient Solutions

Transient solutions can be obtained for piecewise-linear,

exponential, and sinusoidal bias functions. Transient

solutions are used when a time dependent test or response

is required. To obtain transient solutions for a linear ramp,



77

the TSTART, TSTOP, TSTEP, and RAMPTIME

parameters should be specified.

Figure the syntax of the transient voltage ramp. The

TSTART parameter specifies the time that the linear ramp

should start. The RAMPTIME specifies the time that the

linear ramp should obtain its final value. TSTOP specifies

the time that solutions will stop. TSTEP specifies the

initial step size.

Subsequent time steps are calculated automatically by

ATLAS. For example, the statement:

SOLVE VGATE=1.0 RAMPTIME=1E-9 TSTOP=10e-

9 TSTEP=1e-11

Specifies that the voltage on the gate electrode will be

ramped in the time domain from its present value to 1.0V

over a period of 1 nanoseconds.

XIII RESULTS

The focus of results and discussion of SOI MOSFET

implementation, kink effect verification and its

optimization for reducing the kink effect. The important

issues like thickness of the BOX layer, gap between the

buried oxide layer, adopted model & the numerical

method used for simulation has been discussed. Stepwise

approach for constructing the structure, its fabrication &

circuit simulations are discussed. The sensitivity and

selectivity of the gap length, doping concentration &

potential variation has been highlighted.

SIMULATION ANALYSIS OF SOI STRUCTURE

When a layer of silicon dioxide is introduced in the silicon

in MOSFET structure, the physical limitation of MOSFET

such as reduction in carrier mobility due to impurities,

increasing gate tunneling effect as the gate oxide thickness

decreases and increasing p-n junction leakage current as

the junctions become more and more shallow has been

eliminated.

SOI technology offers significant advantages in design,

fabrication and performance for many semiconductor

circuits such as excellent isolation, improved latch up free

operation, radiation hardness, reduced leakage current,

reduced short channel effects and improved switching

speeds due to reduction in the drain-body capacitance. The

reduction in the parasitic capacitances leads to improved

switching speed and superior performance.

In spite of these advantages the SOI devices experience

several limitations like “Kink” in the output current-

voltage characteristics, self-heating etc. which are not

present in bulk devices. SOI structure has been simulated

and its ID-VD characteristic graph is obtained which

confirms the kink effect.

Figure: 1.8 SOI MOSFET ID - VDS for VG =1v, 2v& 3v

SIMULATION ANALYSIS SELBOX STRUCTURE

To reduce the kink effect it is needed to be optimize the

SOI structure. For the optimization we introduced

different gap thickness between the oxide layer. When we

provide the gap between the oxide, the impact ionization

arised due to BOX is reduced because of the bypassing the

carriers in the substrate region.

In this research work SOI structure has been modified for

the gap length of 0.1micron, 0.01 micron, 0.001 micron, 1

micron & 0.2 micron between the BOX layer.

SELBOX structure with gap length of 0.001

micron

At 0.001 micron gap length SELBOX structure does not

reduces the kink. It is similar to SOI device and the gap

length does not give any impact.

With increased gap length, the number of holes getting

drained to the substrate increases, which results in an

increased kink voltage. Simulation results indicate that the

kink voltage increases with increase in the gap length and

completely vanishes for higher gap lengths.

Introduction of high quality BOX layer below the source

and drain regions with narrow gaps under a single

MOSFET will require additional process steps. With

higher process complexity, there will be an associated

increase in the cost as well.



78

Figure: 1.9 SELBOX structure ID-VDS graph for 0.001

micron gap length

At V = 1v, 2v, 3v


micron

At 0.01 micron gap length SELBOX structure partially

reduces the kink but not able to eliminate it. The device

structure and its ID-VDS graph has been shown below.


micron gap length

At VG = 1v, 2v, 3v


micron

At 0.1 micron gap length SELBOX structure reduces the

kink effect effectively and the SOI got the characteristic

graph equivalent to MOSFET but retain its capability

which is beyond the physical limitation of MOSFET

structure.

The device has been optimized for gap length 0.1 micron

and its ID-VDS graph has been obtained.


micron gap length

At VG = 1v, 2v, 3v

For increased gap lengths, the kink occurs at a higher drain

voltage because an increase in the gap length leads to a

decrease in the gap resistance. Consequently, the body

voltage can rise to the level required for the occurrence of

kink for a larger hole current only, and this is possible at a

higher drain voltage. Eventually, for larger values of gap

lengths, the kink will completely disappear.

For narrow gap lengths, the device still behaves like an

SOI device because the narrow gap is inadequate to drain

the holes to the substrate. Therefore, the accumulation of

holes in the body

region will continue till the body source p-n junction gets

forward biased.


micron

At 0.2 micron gap length SELBOX structure completely

reduces the kink. The device structure and its ID-VDS graph

has been shown below.



79

Figure:1.12 SELBOX structure ID-VDS graph for 0.2

micron gap length

At VG = 1v, 2v, 3v

SELBOX structure with gap length of 1

micron

At 1 micron gap length SELBOX structure completely

reduces the kink but device become very close to bulk

MOSFET. Bulk MOSFET having its own physical

limitation due to which it lacks various characteristics and

fail for the further scaling of device.

Radiation hardness property of the SOI device will be

affected by increasing the gap length and the device will

be very sensitive for the radioactive element at this gap

length just like bulk MOSFET. It may be the reason of

degradation or damage of the device.

Further increments in the gap length will not bring

effective changes and device will be more similar as bulk

device. So it is needed to optimize the device so that it can

remove the kink as well as it can keep the characteristic of

SOI.

Figure: 1.13 SELBOX structure ID-VDS graph for 1

micron gap length

At VG = 1v, 2v, 3v

ANALYZING THE KINK EFFECT AT DIFFERENT

GAP LENGTH

From the simulation analysis we can state that kink has

been removed for the SELBOX thickness 0.1 micron

onwards. Although at higher gap length kink is not present

but the device starts behave like bulk MOSFET. At narrow

gap length it is required to investigate the effect of gap

length with the drain to source voltage at particular gate

voltage.

The result simulated above is shown in tabular for and it is

graphically represented below:

Table 1.2 Effect of gap length variation as a kink

Figure: 1.14 kink effect Vs Gap length

Figure 1.14 depicted kink occurred at different voltage at

varying gap length. From the Table 1.2 we can analyze the

result very well. It describes the drain to source voltage at

different gate voltage for different gap length.

BEHAVIOR OF FREQUENCY RESPONSE FOR SOI

MOSFET

The frequency behavior of semiconductor devices depend

on the internal capacitances of the device. The limiting

factor for the transistor response at high frequency end is

usually expressed in terms of the transition frequency fT.

This is the frequency at which the short circuit common

source current gain of the device falls to unity. fT is

characteristic of the intrinsic device and provides an

0

0.5

1

1.5

2

0 0.05 0.1 0.15

Kin

k Ef

fect

vo

ltag

e

BOX-Gap length um

1v

2v

3v

Gap

Length

(um)

Kink effect

occurred at

Voltage

Vg = 1V

Kink effect

occurred at

Voltage

Vg = 2V

Kink effect

occurred at

Voltage

Vg = 3V

0 0.7 1.3 1.5

0.0001 0.7 1.3 1.56

0.01 0.7 1.3 1.65

0.1 0.7 1.3 1.7



80

indication on the maximum useful frequency of the

transistor The presence of the buried oxide in SOI devices

minimizes the gate to body capacitance (Cgb). The

capacitance between gate and Substrate, Cgb seen in case

of bulk devices will have two capacitor components

connected in series for SOI devices. Here it will be a series

combination of capacitance between gate and the body

region and the Cbox which is the capacitance between body

of the SOI device and substrate at the bottom end where

buried oxide is the dielectric. With the introduction of

Cbox, the capacitance Cgb will be reduced to an extremely

low value and the transition frequency for SOI devices is

reduced to For SELBOX structure the device is obtained

by modifying the layout of the buried oxide.

The buried oxide does not cover the entire area below the

source and drain as in the case of SOI devices. For

SELBOX structure the gate to substrate capacitance Cgb

depends on the gap of the buried oxide. Consequently in

the SELBOX structure the capacitance Cgb will not be

negligibly small as compared to the SOI devices but will

assume a value much less than that for bulk devices.

Consequently the transition frequency fT for SELBOX

structures is expected to be higher than that for a simple

bulk devices.

CONCLUSION

MOSFET, SOI MOSFET & SELBOX structure has been

implemented using the Silvaco TCAD tools. The

performance of the MOSFET structure is limited by the

fundamental physical limits such as reduction in carrier

mobility due to impurities, increasing gate tunneling effect

as the gate oxide thickness decreases and increasing p-n

junction leakage current as the junctions become more and

more shallow.

In order to avoid these physical limitations SOI

technology came into existence. SOI technology offers

significant advantages in design, fabrication and

performance for many semiconductor circuits such as

excellent isolation, improved latch up free operation,

radiation hardness, reduced leakage current, reduced short

channel effects and improved switching speeds due to

reduction in the drain-body capacitance. In spite of these

SOI suffers with several limitations like “Kink” in the

output current-voltage characteristics, self-heating etc.

which are not present in bulk devices.

In order to reduce the kink effect SELBOX structure has

been proposed. By optimization of the SELBOX structure

kink can be eliminated effectively.

1. From the optimization of SOI MOSFET structure it

has been observed that at 0.1 micron the device

eliminates the kink while preserving the basic

merits of SOI structure. Below than 0.1 micron of

gap length between the oxide the kink is partially

reduce at low ramp voltage. Hence it should not be

used in specific application otherwise due to the

kink the device will suffer with self heating and it

can be the reason of damage of the device.

2. At 0.2 micron the device give the same response as

at 0.1 micron and it is needed to select anyone

among these. But for pertaining the basic merit of

SOI we prefer 0.1 micron while o.2 micron can also

be chosen.

3. SELBOX structure with higher gap length like 1

micron will behave like MOSFET. There is no kink

but the device will suffer with the same limitation

as of MOSFET. The device will not be more

REFERENCES

[1] William T. Lynch. “The SOI Option - The SRC

research portfolio and its relationship to the SIA

roadmap”, Electrochemical Society Proceedings,

Vol. 96, pp. 351-363,1996.

[2] A. P. Chandrakasan and R. W. Brodersen, "Low

power digital CMOS design", Kluwer Academic

Publishers, Boston, 1995.

[3] M. Watanabe and A. Tooi, “Formation of SiO2

Films by Oxygen-Ion Bombardment”, Japan J.

Appl. Phys., Vol. 5, pp. 737-738, 1966.

[4] Silicon Genesis, SiGen Corp, “what is SOI”,

http://www.sigen.com/whatissoi.html

[5] Takayasu Sakurai, Akira Matsuzawa and Takakuni

Douseki, “Fullt-Depleted SOI CMOS Circuits and

Technology for Ultralow-Power Applications”,

Springer, 2006.

[6] C. Jaussaud, J. Margail, J. Stoemenos and M.

Bruel, “High Temperature Annealing of SIMOX

Layers, Physical Mechanism of Oxygen

Segregation”, Proceedings of Mat. Res. Soc.

Symp, Vol. 107, pp. 17, 1988.

[7] S. Nakashima and K. Izumi, “Practical Reduction

of Dislocation Density in SIMOX wafers”,

Electron Lett., Vol. 26, No 20, pp. 1647-1649,

1990.

[8] S. Nakashima, T. Katayama, Y. Miyamura, A.

Matsuzawa, M. Imai, K. Izumi and N. Ohwada,

“Thickness Increment of Buried Oxide in a

SIMOX wafer by High-Temperature Oxidation”,

Proceedings IEEE International SOI Conference,

pp. 71-72, 1994.

[9] B.Y. Tsaur, “Zone-melting-recrystallization

silicon-on-insulator technology,” IEEE Circuits

Devices, vol. 3, p. 13, 1987.

[10] G. Bomchil, A. Halimaoui, and R. Herino, “Porous

Silicon: The Material and Its Applications to SOI

technologies,” Microelectron. Eng., vol. 8, p. 293,

1988.

[11] K. Mitani and U.M. Gosele, “Wafer Bonding

Technology for Silicon-On-Insulator applications:



81

A Review,” J. Electron. Materials, vol. 21, p. 669,

1992.

[12] George Celler & Michael Wolf “ Smart Cut A

guide to the technology, the process, the products”

SOITEC July 2003

[13] S. Cristoloveanu, “Silicon films on sapphire,” Rep.

Prog. in Phys., vol. 50, p. 327, 1987.

[14] P.B. Mumola, G.J. Gardopee, P.J. Clapis, C.B.

Zarowin, L. D. Bollinger and A.M. Ledger,

“Plasma Thinned SOI Bonded Wafers”,

Proceedings IEEE International SOI Conference,

pp. 152-153, 1992.

[15] T. Yonehara, K. Sakaguchi and N. Sato, “Epitaxial

Layer Transfer by Bond and Etch Back of Porous

Si”, Appl. Phys. Lett., Vol. 64, pp. 2108-2110,

1994.

[16] S. Veeraraghavan, and J.G. Fossum, “Short

channel effects in SOI MOSFET’s,” IEEE Trans.

on Electron Devices, vol. 45, p. 522-528, 1999.

[17] A. J. Auberton-Herve, "SIMOX-SOI technologies

for high speed and radiation hard technologies:

status and trends in VLSI and ULSI applications"

Proc. of the 4th International Symposium on SOI

technology and Devices, Ed. by O. Schmidt,

Electrocliemical Society, Vol. 90, pp. 455 - 478.

1990

[18] J.-Y. Choi, and J.G. Fossum, “Analysis and

Control of Floating-body Bipolar Effects in Fully

Depleted Submicrometer SOI MOSFET’s,” IEEE

Trans. Electron Devices, vol. 38, p. 1384-1391,

1991.

[19] B. Cheng, V. Ramgopal Rao, and J.C.S. Woo, “Sub

0.18 um SOI MOSFETs Using Lateral

Asymmetric Channel Profile and Ge Pre-

amorphization Salicide Technology,” Proceedings

of the IEEE SOI Conference, October 5-8, Stuart,

Florida, USA, 1998.

[20] M.R.Narayanan, Dr.Hasan Al-Nashash,

Dr.Dipankar Pal & Dr.Mahesh Chandra,

“Frequency Response of MOS Devices with

SELBOX Structure.” IEEE 2012

[21] C. E. D. Chen. M. Matloubian, B. Y. Mao, C. C.

Wei and G. P. Pollack, "Single transistor latch in

SOI MOSFETs" IEEE Electron Device Letters,

vol. 9, pp. 636 - 638, 1988.

[22] M. Haond and J. P. Colinge, Analysis of drain

breakdown voltage in SOI n-channel MOSFETs",

Electronics Letters, Vol. 25, pp. 1640 - 164 1,

1989.

[23] S.M. Sze, “Physics of Semiconductor Devices,”

2nd Ed., New York, J. Wiley & Sons, 1981.

[24] Shockley W. and Read W.T., “Statistics of the

Recombination of Holes and Electrons”, Phys.

Rev., 87, 952, p. 835-842.

[25] Hall, R.N., “Electron Hole Recombination in

Germanium”, Phys. Rev., 87, p. 387, 1952.

[26] J.W. Slotboom, “The PN Product in Silicon”, Solid

State Electronics 20, p. 279-283. 1977.

[27] A. Mercha, J. M. Rafí, E. Simoen, E. Augendre,

and C. Claeys ““Linear Kink Effect” Induced by

Electron Valence Band Tunneling in Ultrathin

Gate Oxide Bulk and SOI MOSFETs” IEEE

TRANSACTIONS ON ELECTRON DEVICES,

VOL. 50, NO. 7, JULY 2003

[28] B. G. Vasallo, J. Mateos, D. Pardo and T.

Gonzalez “ Monte Carlo study of kink effect in

short-channel InAlAs/ InGaAs high electron

mobility transistors” JOURNAL OF APPLIED

PHYSICS, VOLUME 94, NUMBER 6, 2003

[29] Bennamane Kamal, Benfdila Arezki, Achour

Hakim and Lakhlef Ahcene “On Silicon on

Insulator Technology and Devices”, African

Physical Revie 2 Special Issue (Microelectronics):

0003, 2008.

[30] Rahul Kr. Singh, Amit Saxena, Mayur Rastogi

“SILICON ON INSULATOR TECHNOLOGY

REVIEW” International Journal of Engineering

Sciences & Emerging Technologies, Volume 1,

Issue 1, May 2011.

[31] Sapna & Bijender Mehandia “Study of Electrical

Characteristics of SOI MOSFET Using Silvaco

TCAD Simulator” , Current Trends in Technology

and Sciences Volume : 1, Issue : 1 ,July-2012

[32] H. Morris, E. Cumberbatch, V. Tyree, H. Abebe

“Analytical Results for the I-V Characteristics of a

Fully Depleted SOI-MOSFET” research work

submitted for the publish

[33] Tarun Kumar Agarwal, Amit R. Trivedi,

Vaidyanathan Subramanian, and M. Jagadesh

Kumar, “Compact Modeling of Partially Depleted

Silicon-on-Insulator Drain-Extended MOSFET

(DEMOS) including High-voltage and Floating

Body Effects”, proceeding of IBM Faculty award.

[34] Benjamin iniguez, jean pierre raskin, pascal simon,

denis flandre & jaume segura “A review of

leakage current in SOI CMOS ICs: impact on

parametric testing techniques”, Solid-State

Electronics 47 2003.

[35] Ling Wang, Tor A. Fjeldly, Benjamin Iniguez,

Holly C. Slade & Michael Shur “Self-Heating and

Kink Effects in a-Si: H Thin Film Transistors”,

IEEE TRANSACTIONS ON ELECTRON

DEVICES, VOL. 47, NO. 2, FEBRUARY 2000.

[36] Sanjoy Deb, C. J. Clement Singh, Subir Kumar

Sarkar, N Basanta Singh & P C Pradhan, “Design

and Performance Comparison of SOI and

Conventional MOSFET based CMOS Inverter”,

published by International Journal of Computer

Applications, 2011.

[37] Dewill Chung, Byong-Deok Choi, Sang-Gyu Park,

“A New Model for Kink-Effect in Poly-Silicon

Thin-Film Transistors”, Proc. of ASID, 8-12 Oct,

2006.



82

[38] M. Youssef Hammad and Dieter K. Schroder,

“Analytical Modeling of the Partially-Depleted

SOI MOSFET”, IEEE TRANSACTIONS ON

ELECTRON DEVICES, VOL. 48, NO. 2,

FEBRUARY 2001.

[39] ATLAS User’s Manual Device Simulation

Software, Silvaco International, 4701 Patrik Henry

Drive, Santa Clara, CA 95054, September 2004.

[40] Kidong Kim, Ohseob Kwon, Jihyun Seo and

Taeyoung Won, "Two-Dimensional Quantum-

Mechanical Modeling for Strained Silicon Channel

of Double-Gate MOSFET," Journal of the Korean

Physical Society, vol. 45, pp. 79-85, Dec 2004.

[41] Tarun Vir Singh, M. Jagadesh Kumar, "Effect of

the Ge mole fraction on the formation of a

conduction path in cylindrical strained-silicon-on-

SiGe MOSFETs," Superlattices and

Microstructures, vol. 44, pp. 79-85, March 2008.

[42] F M Bufler, A Schenk and W Fichtner, "Strained-Si

single-gate versus unstrained-Si double-gate

MOSFETs," Semicond. Sci. Technol, vol. 19, p.

S122–S124, March 2004.

Documents

Implementation of SOI MOSFET using Silvaco TCAD … · Implementation of SOI MOSFET using Silvaco TCAD Reduction of KINK Effect and Frequency Response ... is that in PD SOI devices,