VERILOG SYNTHESISABLE RTL CODE

Simple AND Gate:

module and2(a,b,c); input a,b; output c; wire c; assign c= a&b;endmoduleAND gate test bench:

module and_tb; reg a,b; wire c; and2 U (a,b,c); initial begin a=0; b=0; #5 a=0; b=1; #5 a=1; b=1; endendmodule

HALF ADDER

Half Adder using DATA FLOW METHOD (assign statement)

module ha(a,b,s,c); input a,b; output s,c; assign s= a^b; assign c= a&b;endmodule

Half Adder using BEHAVIROL METHOD (always statement)

module ha_always(a,b,s,c); input a,b; output s,c; reg s,c; always@(a,b) begin s<=a^b; c<=a&b; endendmodule

Half Adder Test bench

module ha_tb; reg a,b;

wire s,c; ha U(a,b,s,c); initial begin a=0; b=0; #100 a=1; b=1; #100 a=0; b=1; endendmodule

FULL ADDER

module fa(a,b,c,s,co); input a,b,c; output s,co; wire s,co; assign s=a^b^c; assign co= a&b|b&c|c&a;endmodule

FULL ADDER TEST BENCH

module fa_tb(); reg a,b,c; wire s,co; fa u1(a,b,c,s,co); initial begin a=0; b=0; c=0; #10 a=1; #10 b=0; #10 c=1; end endmodule

DECODER 2:4

module decoder24(a,b,d0,d1,d2,d3); input a,b; output d0,d1,d2,d3; assign d0= ~a&~b; assign d1= ~a&b; assign d2= a&~b; assign d3= a&b;endmodule

Decoder using IF statement

module decoder24_if(a,b,d); input a,b; output [3:0]d;

reg [3:0]d; always@(a,b) begin if(a=0;b=0) begin d[0] = {1,0,0,0};end else if(a=0; b=1) begin d[1] ={0,1,0,0};end else if(a=1; b=0) begin d[2] = {0,0,1,0};end else a=1;b=1 d[3] ={0,0,0,1}; /* case(a) 00: d[0]=4'b1000; 01: d[1]=4'b0100; 10: d[2]=4'b0010; 11: d[3]=4'b0001; endcase*/ end endmodule

DECODER TEST BENCH

module decoder24_tb; reg a,b; wire d0,d1,d2,d3; decoder24 U(a,b,d0,d1,d2,d3); initial begin a=0;b=0; #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; endendmodule

module decoder24_tb(); reg a; wire y; decoder24 u(a,y); initial begin a[0]=0; a[1]=0; #10 a[0]=0; a[1]=1; #10 a[0]=1; a[1]=0; #10 a[0]=1; a[1]=1; endendmodule

MULTIPLEXER 2X1

module mux21(a,b,s,y); input a,b; input s; output y; assign y= ~s&a|s&b;endmodule----------------------------------

module mux21(a,b,s,y); input a,b; input s; output y; //assign y= ~s&a|s&b; //data flow

reg y;always@(*)/*begin if(s==1) y=b; // using if else statement else y=a; end*/ case (s) 1: y=b; 0: y=a;endcaseendendmodule

module mux(a,b,s,y); input a,b,s; output y; // wire y; //assign y = ~s&a|s&b;//endmodule

reg y;always@(s)begin if (s==0) y = a; else y=b; end endmodule

MUX 2X1 TEST BENCH

module mux21_tb; reg a,b,s; wire y;

mux21 U(a,b,s,y); initial begin s=1;a=0; b=1;#100 a=1; b=0;#100 s=0;#100 a=0;b=1;endinitial begin $display(" $time s a a y");$monitor("time=%d s=%b a=%b a=%b y=%b",$time,s,a,b,y);endendmodule

COMPARATOR

module comp(a,b,g,e,l); input a,b; output g,e,l; reg g,e,l; always @(a,b) begin if(a==0 && b==0)

begin g=0; e=1; l=0; end else if(a==0 && b==1) begin g=0; e=0; l=1; end else if(a==1 && b==0) begin g=1; e=0; l=0; end else begin g=1; e=0; l=0; end end endmodule

COMPARATOR TEST BENCH

module comp_tb; reg a,b; wire g,e,l; comp u1(a,b,g,e,l); initial begin a=0; b =0; #10 a=0; b=1; #10 a=1; b=0; #10a=1; b=1; #10a=1; b=1; #10a=1; b=1; #10a=1; b=0; end initial begin $monitor($time, "%b %b %b %b %b",a,b,g,e,l); $display("reuts r successful"); end endmodule

SIMPLE NORML COUNTER

module simplecounter(clk, rst, count);input clk, rst;output [31:0] count;reg [31:0]count;

always@(posedge clk) begin if (rst) count <= 32'b0; else count <= count+1; end endmodule NORMAL COUNTER TEST BENCH

module simplecount_tb; reg clk, rst; wire [31:0]count; simplecounter u1(clk, rst, count); initial begin // clock generation clk=0; //forever #5 clk = ~clk; end always #5 clk=~clk; initialbegin rst = 0; #5 rst = 1; #5 rst = 0; #50 rst = 1; End endmodule

MOD5 COUNTER

module cnt(rst,clk,q); input rst, clk; output q; reg q; always @(posedge clk) begin if(rst) q<=0; else if (q==4) q<=0; else q= q+1; end endmodule

MOD5 COUNTER TEST BENCH

module cnt_tb; reg rst,clk; wire q; cnt U1(rst,clk,q); initial begin clk=0; end always #5 clk=~clk; initial begin rst=0; #10 rst=1; #10 rst=0; #100 $finish; //#100 $stop; end // $monitor($time, %b,%b,%b rst,clk,q); Endmodule

MOD3 COUNTER

module cnt(clk, rst, ent); input clk, rst; output [2:0]ent; always @(posedge clk) begin if (rst) ent <=1'b0; else ent<= cnt_in; end always @(ent) begin if (ent=4) cnt_in= 1'b0; else cnt_in = ent+1;

endendmodule

LOGIC COUNTER

module conter(clk,rst,mcnt); //0123455555567 input clk,rst; output [2:0]mcnt; reg[2:0]mcnt; reg [2:0]scnt; always@(posedge clk,rst) // mcnt begin if(rst) mcnt <= 3'b0; else if(mcnt == 7) mcnt <=3'b0; else if(mcnt ==5) begin if(scnt ==6) mcnt <=3'b110; else mcnt <= 3'b101; end else mcnt <= mcnt +1; end always @(posedge clk) //scnt 0000012345600 begin if(rst) scnt <= 3'b000; else if(scnt==6) scnt <= 3'b000; else if(mcnt == 4) scnt <= 3'b001; else if(scnt>=1) scnt <= scnt +1; else scnt <=3'b000; endendmodule LOGIC COUNTER TEST BENCH

module counter_tb(); reg clk_tb,rst_tb; wire[2:0]mcnt_tb; conter u1(.clk(clk_tb),.rst(rst_tb),.mcnt(mcnt_tb)); initial begin clk_tb=0; rst_tb =1; #15 rst_tb =0; forever #5 clk_tb = ~clk_tb; end endmodule

FINATE STATE MACHINE

module fsm1(d,clk,rst,y); //1010 input clk,rst;

input d; output reg y; reg [2:0]state,ns; parameter [2:0]idle=3'b000, s1=3'b001, s10=3'b010, s101=3'b011, s1010=3'b101;always @(posedge clk) begin if(rst) state <= idle; else state <= ns;end

always@(state,d) begin case(state) idle:if(d) ns =s1; else ns = idle; s1:if(d) ns =s1; else ns = s10; s10:if(d) ns =s101; else ns = idle; s101:if(d) ns =s1; else ns =s1010; s1010:if(d) ns =s1; else ns = idle; endcase end always @(posedge clk) begin if(state == s1010) y = 1; else y =0; end endmodule

FSM TEST BENCH

module fsm1_tb(); reg clk,rst,d; wire y; fsm1 u1(d,clk,rst,y); initial begin clk =1'b1; rst = 1'b1; d=1;#10 d=1; rst = 1'b0;#10 d=0;#10 d=1;#10 d=0;#10 d=1;#10 d=0;#10 d=1;

#10 d=0;#10 d=1;#10 d=0;

endalways #5 clk = ~clk;endmodule FSM

module fsm(clk,rst,d,y); input clk,rst,d; output y; reg y; reg [2:0]state,ns; parameter [2:0]i=3'b000, s1=3'b001, s10=3'b010, s101=3'b011, s1011=3'b100; always @(posedge clk) begin if(rst==1) state <= i; else state <=ns; end always @(d,state) begin case(state) i: if(d==1) ns = s1; else ns = i; s1: if(d==1) ns = s1; else ns = s10; s10: if(d==1) ns = s101; else ns = i; s101: if(d==1) ns = s1011; else ns = s10; s1011: if(d==1) ns = s1; else ns = i; endcase end always @(state) begin if(state==s1011) y = 1; else y =0; endendmodule

module fsm1(d,clk,rst,y); input clk,rst; input d; output reg y; reg [2:0]state,ns; parameter [2:0]idle=3'b000,

s1=3'b001, s10=3'b010, s101=3'b011, s1010=3'b101;always @(posedge clk) begin if(rst) state <= idle; else state <= ns;end

always@(state,d) begin case(state) idle:if(d) ns =s1; else ns = idle; s1:if(d) ns =s1; else ns = s10; s10:if(d) ns =s101; else ns = idle; s101:if(d) ns =s1; else ns =s1010; s1010:if(d) ns =s1; else ns = idle; endcase end always @(posedge clk) begin if(state == s1010) y = 1; else y =0; end endmodule

module fsm1_tb(); reg clk,rst,d; wire y; fsm1 u1(d,clk,rst,y); initial begin clk =1'b1; rst = 1'b1; d=1;#10 d=1; rst = 1'b0;#10 d=0;#10 d=1;#10 d=0;#10 d=1;#10 d=0;#10 d=1;#10 d=0;#10 d=1;#10 d=0;

endalways #5 clk = ~clk;

endmodule

module cnt(clk, rst, ent); input clk, rst; output reg[2:0]ent; reg [2:0]cnt_in; always @(posedge clk) begin if (rst) ent =1'b0; else ent= cnt_in; end always @(ent) begin if (ent==4) cnt_in= 1'b0; else cnt_in = ent+1; endendmodule

module mod5_tb; reg clk, rst; wire [4:0] count; countermod5 u1(clk, rst, count); initial begin clk = 0; end always #5 clk = ~clk; initial begin rst = 0; #5 rst = 1; # 5 rst = 0; #68 rst = 1; #20 rst = 0; $finish; //# 500 $stop; // excution stops at 500 ns //end //initial begin //$display(" this is mod5 counter upto 5"); end endmodule