Logic Gate C

7/29/2019 Logic Gate C

1/85

Logic Gates

Logic FunctionsLogic Functions

NMOS & CMOS TechnologiesNMOS & CMOS Technologies

Logic GatesLogic Gates

The InverterThe Inverter

The NAND GateThe NAND Gate

The NOR GateThe NOR Gate

Compound GatesCompound Gates


2/85

Binary Logic

Open Closed

Logic 0 Logic 1

A Single switch to represent:Logic 0 ( OFF, Open, Logic Low, 0 Volts)Logic 1 ( ON, Closed, Logic High, 5 Volts)


3/85

AND Function

Off

A

A B LightANDAND

B

0 1 Off1 0 Off1 1 On

On

A BF = A BF = A B

AA

BB


4/85

OR Function

Off

A

B

A B LightA B Light

OROR

B

On

0 1 On0 1 On1 0 On1 0 On1 1 On1 1 On

F = A + BF = A + B

AA

BB

A

B


5/85

Switch Implementation of

a Logic Function

F = a d + a b c + a b d + c dF = a d + a b c + a b d + c d

aa bb cc dd OpenOpen

++

--

FFClosedClosed


6/85

Switch Implementation

F = a b c + d ( a + b + c )F = a b c + d ( a + b + c )


7/85

NMOS Technology

Logic gates are built usingLogic gates are built using A single Depletion mode NA single Depletion mode N--

type Pull up transistortype Pull up transistor

VddDepletion modeDepletion mode

NN--type Transistortype Transistor

between Vbetween Vdddd and gate outputand gate output(Always ON)(Always ON)

A Number of EnhancementA Number of Enhancement

mode Nmode N--type transistorstype transistors

between gate output andbetween gate output and

ground (Vground (Vssss).).

Out

GndEnhancementEnhancementmode Nmode N--typetype

TransistorsTransistors


8/85

NMOS Inverter

DepletionDepletion

mode Trmode Tr

VddDD

Depletion mode TransistorDepletion mode Transistorgate is connected to its sourcegate is connected to its source

ie Vgs = 0ie Vgs = 0

A

Out

GndEnhancementEnhancementmode Trmode Tr

-

EA D E Out

0 On Off Vdd

1 On On Low

Depletion mode is ONDepletion mode is ON


9/85

Inverters Low output

When A=1 Pull-down Tris ON

i = V / R + r

Vdd

i

Vout = i * r

= (Vdd * r) / (R+r)

If Vdd=5V and R = 4r

Then Vout=1V (Vlow)

A = 1

Out

Gnd

Pull-down

R

r


10/85

NMOS Inverter

N-Type Transistors Out = not ( A )

Depletion

mode Tr

Vdd

dissipation when A=1

Good 1, poor 0

Ratio Logic Pull up/Pull down

must be 4 or more

A

Out

GndEnhancementmode Tr

- ype


11/85

CMOS Technology

VddEnhancementmode P-type

Transistors

Only Enhancement

mode transistors

Pull-ups

Out

GndEnhancement

mode N-type

Transistors

P-type as pull-upsbetween Vdd and Out

pin

N-type as pull-downsbetween Out pin and

GND

Pull-down


12/85

CMOS Inverter

Use enhancement NUse enhancement N--and Pand P--type Trstype Trs

Out = not AOut = not A

VddVddEnhancementEnhancement

pp--type Trtype Tr

Zero static powerZero static power

dissipationdissipation

Good 1 and 0Good 1 and 0

Ratioless LogicRatioless Logic

AA OutOut

GndGndEnhancementEnhancementnn--type Trtype Tr


13/85

CMOS Inverter


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19/85

P+

P+P+N+

N+N+


20/85


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24/85

NMOS NAND Gate

Use N-Depletion and N-Enhancement Trs

Out = not ( A B)

Vdd Depletionmode Tr

when both A and B =1

Good 1, poor 0

Ratio Logic

Pull-up/Pull-down must be 4 ormore

A

Gnd

B

Enhancement

mode Tr


25/85

CMOS NAND Gate

Use P- and N-typeEnhancement Trs

Out = not ( A B)

Vdd Enhancementp-type Trs

A B Zero static power

dissipation

Good 1 and 0

Ratioless Logic

Gnd

A

B

Enhancement

mode Trs

Out


26/85

2-input


27/85


28/85

N-Well


29/85


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N+


32/85

P+


33/85


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35/85

NMOS NOR Gate

Use N-Depletion and N-

Enhancement Trs

Out = not ( A + B)

Depletion

mode Tr

Vdd

when either A or B =1 Good 1, poor 0

Ratio Logic

Pull-up/Pull-down must be 4 or more

Out

GndEnhancementmode Tr

A B


36/85

CMOS NOR Gate

Use P- and N-typeEnhancement Trs

Out = not A + B

VddEnhancement

P-type Trs

A

Zero static powerdissipation

Good 1 and 0

Ratioless LogicGndEnhancement

N-type Tr

A B

Out


37/85

2-input


38/85


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48/85

Design of Combination Gate

Designing with NMOS technology

Minimise the given function F

Invert F ---- G = NOT ( F )

simplify the resultant G function Implement G circuit using enhancement mode N-

type Transistors and connect it between ground andoutput node

Connect the output node through Depletion mode toVdd and calculate the size of the transistor.


49/85

Designing with CMOS technology -- starting

with P-circuit Minimise the given function F and implement it as

P-type circuit and invert all inputs -- Connect this P-

circuit between the Vdd and the output node the N-type circuit is the complement of the P-circuit

connected to the same in uts as P-circuit. This circuit

must be connected between the output and theGround.


50/85

Designing with CMOS technology -- starting

with N-circuit

Compute the complement of F { G = NOT(F) }

Simplify G and implement it as N-type circuit --Connect it between the output node and the Ground.

The P-circuit is the complement of the N-circuit using

the same inputs. Connect the P-circuit between theoutput node and Vdd.


51/85

Design Problem

Implement F using

F = A + B.C

tec no ogy -- a cu ate t e pu -up

transistor size assuming the minimum size for

pull-down devices

CMOS Technology Start with the P-circuit first

Start with the N-circuit first


52/85

Clocked CMOS

Clocking the input(s) Perfect switch for each

in ut

VddC

Out

Gnd

C

a


53/85

Clocked CMOS (C2MOS)

Clocking the outputstage

Onl two transistors

Vdd

CClocked

are needed at theoutput stage of the

device. Therefore less

transistor count thanthe last CCMOS

Out

Gnd

C

A

Dynamic CMOS (Domino


54/85


technology)Vdd

L

Function

F

Out

Vss

Crl

When Crl = 0

L = VddOut = 0

When Crl = 1

L = F Out = F

(Charge Cycle)

(Evaluate Cycle)

N-typecircuit



55/85


technology)Vdd

When Crl = 1L = GND Out = 1

(Ground Cycle)

Function

F

OutVss

Crl L

P-typecircuit

When Crl = 0

L = F Out = F

(Evaluate Cycle)


56/85

IC Technologies -- CMOS

Highest density-- suitable for memories Lowest power per gate, only during logic

-

Adequate for analogue

Slower than GaAs and Bipolar

The cheapest to manufacture for high-density digital circuits with moderate

analogue requirement


57/85

CMOS Technology -- Continued

available design tools and cell libraries -low design cost

layout styles static CMOS requires 2n forn inputs

function - disadvantage

dynamic CMOS requires n+4 forn inputsfunction


58/85

CMOS Technology -- Continued

Rise and fall times are of the same order Transmission gates pass both logic levels

, ,

latches, registers and multiplexers

Voltage required to switch a gate is a fixed

percentage of Vdd. Variable range is 1.5 to15 volts.


59/85

Other IC Technologies

GaAs

The fastest raw gate speed -- suitable forcommunication applications

Design is expensive -- full customed

Bipolar

Next to GaAs in speed -- Comms applications

High power consumption -- Low integration


60/85

Types of pull-ups

N-Depletion mode Tr

N-type enhancement

Vdd

Vdd

mode Tr

P-type enhancement

mode Tr

Resistor

Vdd

Vdd

Rpu


61/85

MOS TransistorL

L Channel Length

W Channel Width

W

Direction

of flow of carriers

Z = Impedance

Z ~ L/W


62/85

Implementation of Functions

Implement F using NMOS, CMOS, C2

MOSand dynamic CMOS technologies

F = A B + C D


63/85

Design of Multiplexers

Switch S to select between inputs A&B

When S=0

Out

B

S

Out=A

When S=1Out=B

Two input Mux Circuit


64/85

S

Switch 1

Two input Mux Circuit

S

B

S

Output

Switch 2

Output = S A + S B

Output signal is

connected to A or

B and hence

never floating


65/85

Pass-Transistor Logic

a

b

c d

z Z = a c + b d

a

b

C=1 D=1

z

on

on

If C=D=1N-Type Pass Transistors are ON

z = a or b or in between.

This is called charge sharing .

If a=1 & b=0 short circuit

and circuit is dead


66/85

Pass-Transistors

a

b

c d=c

zImplement this logic as amultiplexer circuit

e =c

z = a c + b c

The output must be connected to one andonly one input signal


67/85

NAND Pass-Transistor

A

B

Z

A B Z Pass Function

0 0 1 A' + B'

0 1 1 A' + B

1 0 1 A + B'

A' A'

B' B

A A'

B' B'

BA

0

1

0 1

Modified Karnaugh Map

1 1 0 A' + B'


68/85

NAND Pass Transistor gate

A' A'

B' B

BA

0

0 1

Assume B as a control signal for the

Mux circuit and A as the input variable

=

A A'B' B'

1

= B(B) + B(A)= B(1) + B(A)

1

A

B B

zNoteB + BA = B + A

= (BA) NAND


69/85

AND Pass-Transistor

A B Z Pass Function

0 0 0 A + B

0 1 0 A + B'

' +

A

B

Z

1 1 1 A + B

A A

B B'

A' A

B B

BA

0

1

0 1



70/85

AND Pass Transistor gate



=

A A

B B'

B

A

0

0 1

= B(B) + B(A)= B(0) + B(A)

0

A

B B

zNoteB(0) + B(A) = BA

AND function

A' A

B B1


71/85

OR Pass-Transistor

A B Z Pass Function

0 0 0 A + B

0 1 1 A' + B

+ '

A

B

Z

1 1 1 A + B

A A'

B B

A A

B' B

BA

0

1

0 1



72/85

OR Pass Transistor gate



=

A A'

B B

B

A0

01

= B(A) + B(B)= B(A) + B(1)

A

1

B B

zNoteB(A) + B = A + B

OR function

A A

B' B1


73/85

NOR Pass-Transistor

A B Z Pass Function

0 0 1 A' + B'

0 1 0 A + B'

' +

A

B

Z

1 1 0 A' + B'

A' A

B' B'

A' A'

B B'

BA

0

1

0 1



74/85

NOR Pass Transistor gate



=

A' A

B' B'

B

A

0

0 1

= B(A) + B(B)= B(A) + B(0)

A

0

B B

zNoteB(A) + B(0) = AB

=(A+B) NOR function

A' A'

B B'1


75/85

Pass-Transistor -- Comments

For Y=AB TakingA&B as control

si nals

BA

Y1

When A=B=1 Y=1 Correct

Never allow a function

result to be unknown

like in thisimplementation

en or = =


76/85

Pass Transistors -- continued

Consider the function

when true and also

when false

BAY1

When true Y=AB

When False Y=(AB)=A + B

A

B0


77/85

Pass Transistor - (Y=AB)

AND Function

All inputs as controls

A B

AND as Mux circuit

n-1 control and one as data

0

Y1

4 Transistors

0

A

B

Y

2 Transistors


78/85

Pass Transistor Design Procedure C

Generate truth table from the given Booleanequation

-

when expression result =1 pass transistorfunction is represented by the input variables

when expression result =0 pass transistor

function is represented by the invert of the input

variables

Pass Transistor Design Procedure --


79/85

Use Karnaugh Map or other means togenerate the Pass Transistor Function

For n in ut variable function use n-1 as

Continued

control and one only as input data

write the expression to include the productterms of the control signals ANDed with theresultant of the minimised sum-of-product

expression {This will leave either 0, 1, data, or(data)}.


80/85

Investigation Compare the advantages and disadvantages of

NMOS implementation SCMOS implementation

DCMOS (Domino) implementation Pass Transistor implementation

Include design requirements, number and type of

transistors and total areas (ignore pads and wiring)


81/85

EXNOR Gate

baF =FFaa

VddVdd

bb4 Trs4 Trs).().( baba +=

10 Trs10 Trs

FFaa

bb


82/85

XOR Gate

baF =

a

Fb

4 Trs0V


83/85

A=B and A=B Circuit

ba

Use of Transmission

a b

a=b

gates

Discuss the circuit

operation.


84/85

Comparator a=b Circuit

a0b0

r0

r1r0 = a0b0

a1

b1a2

b2

a3b3

F =(a=b)

r2

r3

r1 = a1b1

r2 = a2b2

r3 = a3b3

F = AND(r0,r1,r2,r3)

Using Shannon Theorem for pass


85/85

transistor solution

a0b0(1)(0)b0a0b0(0)a0(1)b0a0

)b0a0(b0)(a0r0

+++=

+=

a0a0 b0Vdd b0

r0

Vss

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Logic Gate C