VMM1 Electronics Status

Sarah Jones, Charlie Armijo, Ken Johns, Jason Veatch

(Arizona)Jessica Metcalfe,

Vinnie Polychronakos (BNL)

VMM1 Readout Review

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New “C-Card”

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AZ Adapter Card (V1)

AVNET LX9 with Spartan 6 FPGA for ethernet connection to switch

Existing BNL DAQ board with ADCs and Cyclone IV for readout, configuration

StatusMini-MMFE

Left-handed version (10 count) at assembly house

Testing @ BNL 7/6 or 7/9 Right-handed version layout started

by Dan Tompkins (reroute of input channels to VMM1)

Adapter cards V2 with LVDS-RSDS and RSDS-LVDS

submitted to PCB house – due next week

Decide after testing whether to stuff V1 or V2

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StatusCables

Successfully made and tested data and real time address (trigger) cables

Need length specified for H6 useLX9’s

In hand, one @ BNL, several @ Harvard, one @ CERN

Firmware exists (Nathan) to send UDP mock data and configuration packets Being tested at Arizona and will also be

sent to CERN Firmware exists to read/write from

FIFOs5

Status

BNL DAQ Cards Due back from assembly house 7/6 Firmware exists for communication

with LX9 but needs testing and perhaps some additional specifications

Full chain tests @ BNL late this week and/or early next week

Testing configuration from DCS (George) on same time scale

16-port switch In hand @ CERN

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DAQ Status and Plans Can be used for testing with Mamma

DAQUDP datagram sent from LX9 at Harvard

Will be tested at Arizona this weekCommunication between Jack’s BNL

DAQ board and LX9 progressing well Integration at BNL 7/2 – 7/11 including

George Iakovidis et al.Need meeting with Marcin on Mamma

DAQ end

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Status

Other software Code to send/receive UDP mock data

between client and server sent to Marcin Need feedback

Code to write tree from UDP data files in progress (Sarah) may be useful for Mamma DAQ

Offline analysis of school figures and tracking in progress (Jason)

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