VLSI D iVLSI Designi h lLecture 11: Managing the Delay

f C bi ti l N t kof Combinational NetworksShaahinShaahin HessabiHessabiShaahinShaahin HessabiHessabi

Department of Computer EngineeringDepartment of Computer EngineeringSh if U i it f T h lSh if U i it f T h lSharif University of TechnologySharif University of Technology

Adapted Adapted from from lecture notes prepared lecture notes prepared by the book’s author by the book’s author (from (from Prentice Hall PTR)Prentice Hall PTR)

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Topics

Combinational network delay. Path delay Logic optimization Logic optimization.

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Sources of delay

Gate delay:drive; load.

Wire: lumped load; lumped load; transmission line.

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Fanout

Fanout adds capacitance.

sink

source sinksource sink

sink

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Ways to drive large fanout

Increase sizes of driver transistors. Must take into account rules for driving large loads.

Add intermediate buffers. This may require/allow y qrestructuring of the logic.

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Wire capacitance

Use layers with lower capacitance. Redesign layout to reduce length of wires with

excessive delay.y

dvrg1 g3

unbalanced load

g2 g4

dvrg1 g3

b l d

dvrg2 g4

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more balanced

Path delay

Combinational network delay is measured over paths through network.

Can trace a causality chain from inputs to worst-case y poutput.

Critical path = path which creates longest delay Critical path path which creates longest delay. Can trace transitions which cause delays that are

elements of the critical delay pathelements of the critical delay path.

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Path delay example

Nodes represent gates. Assign delays to edges; signal may have different

delay to different sinks. Lump gate and wire delay into a single value.

network

graph model

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Critical path through delay graph

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Reducing critical path length

To reduce circuit delay, must speed up the critical path. reducing delay off the path doesn’t help.

There may be more than one path of the same delay. y p yMust speed up all equivalent paths to speed up circuit.

Must speed up cutset through critical path Must speed up cutset through critical path.

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False paths

Logic gates are not simple nodes—some input changes don’t cause output changes.

A false path is a path which cannot be exercised due to p pBoolean gate conditions.

False paths cause pessimistic delay estimates False paths cause pessimistic delay estimates.

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Logic rewrites

Can rewrite by using sub-expressions.

Flattening logic deep logic

g gincreases gate fanin.

Logic rewrites may Logic rewrites may affect gate placement.

shallow logic

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Logic optimization

Logic synthesis programs transform Boolean expressions into logic gate networks in a particular library.

Optimization goals: minimize area, meet delay constraint.

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Technology-independent optimizations

Works on Boolean expression equivalent. Estimates size based on number of literals. Uses factorization resubstitution minimization etc to Uses factorization, resubstitution, minimization, etc. to

optimize logic. Technology independent phase uses simple delay Technology-independent phase uses simple delay

models.

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Technology-dependent optimizations

Maps Boolean expressions into a particular cell library. Mapping may take into account area, delay. May perform some optimizations on addition to simple May perform some optimizations on addition to simple

mapping. Allows more accurate delay models Allows more accurate delay models.

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