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Layout & Simulation
Somayyeh KoohiDepartment of Computer Engineering
Sharif University of TechnologyAdapted with modifications from lecture notes prepared by author
Modern VLSI Design: Chap4 2 of 29Sharif University of Technology
Topics
n Layouts for logic networksn Channel routingn Simulation
Modern VLSI Design: Chap4 3 of 29Sharif University of Technology
Standard cell layout
n Layout made of small cellsvGatesvFlip-flops, etc
n Cells are hand-designedn Assembly of cells is automatic:vCells arranged in rowsvWires routed between (and through) cells
Modern VLSI Design: Chap4 4 of 29Sharif University of Technology
Standard cell structure
VDD
VSS
n tub
p tub
Intra-cell wiring
pullups
pulldowns
pin
pin
Feed
thro
ugh
area
Modern VLSI Design: Chap4 5 of 29Sharif University of Technology
Standard cell structure (Cont’d)
n Intra-cell wiringvShort wire between logic gates in the same rowvLess capacitance compared to routing tracksvRouting tracks are saved
Modern VLSI Design: Chap4 6 of 29Sharif University of Technology
Standard cell design
n Pitch: height of cellv All cells have same pitch vMay have different widths
n Power rail: VDD, VSS connections are designed to run through cells
n A feedthrough area may allow wires to be routed over the cell
Modern VLSI Design: Chap4 7 of 29Sharif University of Technology
Single-row layout design
Routing channel
cell cell cell cell cell
cellcellcellcellcell
wire Horizontal trackVertical track
height
Modern VLSI Design: Chap4 8 of 29Sharif University of Technology
Topics
n Layouts for logic networksn Channel routingn Simulation
Modern VLSI Design: Chap4 9 of 29Sharif University of Technology
Routing channels
n Tracks form a grid for routingv Spacing between tracks is center-to-center distance
between wiresv Track spacing depends on wire layer used
n Different layers are (generally) used for horizontal and vertical wiresv Horizontal and vertical can be routed relatively
independently
Modern VLSI Design: Chap4 10 of 29Sharif University of Technology
Routing channel density
n Density: lower bound on number of horizontal tracks needed to route the channelvMaximum number of nets crossing from one end of
channel to the othervMaximum number of horizontal tracks occupied on any
vertical cut through the channelv Determines height of the channel
Modern VLSI Design: Chap4 11 of 29Sharif University of Technology
Routing channel design
n Placement of cells determines placement of pinsn Pin placement change the densityv Determines difficulty of routing problem
n Density is used to evaluate the wirability of the channel
Modern VLSI Design: Chap4 12 of 29Sharif University of Technology
Pin placement and density
before
a b c
b c a
Density = 3
after
a b c
bca
Density = 2
Modern VLSI Design: Chap4 13 of 29Sharif University of Technology
Example: full adder layout
n Two outputs: sum, carry
carry
sum
x1
x2
n1
n2
n3
n4
Modern VLSI Design: Chap4 14 of 29Sharif University of Technology
Layout methodology
n Generate candidates, evaluate area and speedvCan improve candidate without starting from
scratchn To generate a candidate:vPlace gates in a rowvDraw wires between gates and primary
inputs/outputsvMeasure channel density
Modern VLSI Design: Chap4 15 of 29Sharif University of Technology
A candidate layout
x1 x2 n1 n2 n3 n4
a
b
c
s
cout
Density = 5
Modern VLSI Design: Chap4 16 of 29Sharif University of Technology
Improvement strategies
n Swap the gates within each functionv Doesn’t help here
n Exchange larger groups of cells (e.g swap XOR gates with NAND network)v Swapping order of sum and carry groups doesn’t help either
n This seems to be the placement that gives the lowest channel densityv Cell sizes are fixedv So, channel height determines area
Modern VLSI Design: Chap4 17 of 29Sharif University of Technology
Left-edge algorithm
n Basic channel routing algorithmn Assumes one horizontal segment per netn Sweep pins from left to right:v Assign horizontal segment to lowest available trackv Track assignment is greedy
Modern VLSI Design: Chap4 18 of 29Sharif University of Technology
Example
A B C
A B B C
Modern VLSI Design: Chap4 19 of 29Sharif University of Technology
Limitations of left-edge algorithm
n Some combinations of nets require more than one horizontal segment per net
B A
A B
aligned
?
Modern VLSI Design: Chap4 20 of 29Sharif University of Technology
Vertical constraints
n Aligned pins form vertical constraintsvWire to lower pin must be on lower track vWire to upper pin must be above lower pin’s wirev Can not be satisfied simultaneously with one horizontal
segment per net
B A
A B
Modern VLSI Design: Chap4 21 of 29Sharif University of Technology
Dogleg wire
n A dogleg wire has more than one horizontal segmentn Route nets that require doglegs firstv Then route the remaining nets using the left-edge algorithm
B A
A B
Modern VLSI Design: Chap4 22 of 29Sharif University of Technology
Rat’s nest plot
n Shows the position of each component as a point or small boxv Straight lines between components connected by a wire
n Can be used to judge placement before final routing
Modern VLSI Design: Chap4 23 of 29Sharif University of Technology
Topics
n Layouts for logic networksn Channel routingn Simulation
Modern VLSI Design: Chap4 24 of 29Sharif University of Technology
Simulation
n Goals of simulation:vFunctional verificationvTimingvPower consumptionvTestability
Modern VLSI Design: Chap4 25 of 29Sharif University of Technology
Simulation (Cont’d)
n Occurs at two stages:vBefore layout is complete: enter gate or transistor
circuitsØ Pre layout simulation
vExtract a circuit from the layoutØ Post layout simulation
Modern VLSI Design: Chap4 26 of 29Sharif University of Technology
Types of simulation
n Circuit simulation:v Analog voltages and currentsv Important for delay extraction
Ø Accurate but slow
n Timing simulation:v Simple analog models to provide timing but not detailed
waveformsØ Good result for digital circuits
n Switch simulation:v Transistors as semi-ideal switchesv Useful for functional verification
Modern VLSI Design: Chap4 27 of 29Sharif University of Technology
Types of simulation (Cont’d)
n Gate simulation:vLogic gates as primitive elementsvModels for gate simulation:
Ø Zero delayØ Unit delayØ Variable delay
n Fault simulation:vModels fault propagation (more later)
Modern VLSI Design: Chap4 28 of 29Sharif University of Technology
Example: switch simulation
a
++
b
cd
c1
0
0
X
X
Xo0
1
1
Modern VLSI Design: Chap4 29 of 29Sharif University of Technology
Example (Cont’d)
a
++
b
cd
c1
0
0
0
1
1o
0
1
0 0