VHDL-AMStishreen.edu.sy/sites/default/files/Tishreen_Magazine/12_15.pdf · yet mature as digital and analog CAD. In this research, we present a contribution to modeling an optical

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Tishreen University Journal for Research and Scientific Studies - Engineering Sciences Series Vol. (30) No. (2) 2008

VHDL-AMS

2008

��

Multimedia Systems

CAD

CAD

VHDL-AMS

VHDL-AMS

Generated by Foxit PDF Creator © Foxit Softwarehttp://www.foxitsoftware.com For evaluation only.

VHDL-AMS

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Tishreen University Journal for Research and Scientific Studies - Engineering Sciences Series Vol. (30) No. (2) 2008

Optical Receiver Modeling by using VHDL-AMS

Dr. Hasan Albustani* Dr. Ali Ahmad **

Rehaab Habeeb***

(Received 26 / 3 / 2008. Accepted 4 / 5 / 2008)

� ABSTRACT �

Multimedia applications require high-speed networks which enable transferring a large amount of information in a very short time. Optical communications provide an important contribution to this field. A large amount of information can be transferred in a

very short time, ensuring a large bandwidth Electronic devices used in transmitting and

receiving circuits of optical communication play great roles in ensuring speed responsiveness, low noise, and low cost. A computer-aided design of optoelectronics is not yet mature as digital and analog CAD. In this research, we present a contribution to modeling an optical receiver which can be used in CAD tools in order to design and analyze optoelectronic applications. As is the case in our study, we use VHDL-AMS for modeling multidiscipline systems for optical and electrical signals.

Keywords: Optoelectronic, modeling, simulation, CAD of optoelectronic, operational amplifier modeling, optical receivers, and VHDL-AMS

* Assistant Professor, Department of Communication and Electronics, Faculty of Mechanical and

Electrical Engineering, Tishreen University, Lattakia, Syria.** Associate Professor, Department of Communication and Electronics, Faculty of Mechanical and Electrical Engineering, Tishreen University, Lattakia, Syria. ***Postgraduate Student, Department of Communication and Electronics, Faculty of Mechanical and Electrical Engineering, Tishreen University, Lattakia, Syria.


Tishreen University Journal. Eng. Sciences Series

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Differential and Algebraic Equations /DAEs/[1]

Simulation

VHDL-AMS

CAD

VHDL-AMS

Process Engineering

Physical systems

Modeling

Abstract form

“Model”

Characteristics

System

Simulation


VHDL-AMS

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VHDL-AMS

SystemVision

Mentor Graphicswww.mentor.com/systemvision

VHDL-AMS

VHDL-AMS

VHDL-AMS

VHD-AMS[2, 3]

anguage for Lescription Dardware H/ HSICV/Very High Speed Integrated Circuit ()ystemsS Signal-ixedMnalog and A

VHDL

Analog SystemsMixed-Signal Systems VHDL-

AMS

VHDL-AMS

Differential and Algebraic Equations /DAEs/VHDL-

AMSEnergyConserved SystemMulti-

technology Modeling

VHDL-AMS



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mechanicalthermal

Quantity

across

through

Free Quantities

acrossthrough

THROUGHACROSSDomainCurrent (A) Voltage (V) Electrical Power (W)Temperature (C )ThermalForce (N)Position (m)Mechanical (linear)

Torque (N*m)Angle velocity (rad/s)Mechanical (rotational)

Flux (Wb)Magnetic Force (n*A)Magnetical Fluidic flow (1/s)Pressure (Pa)Hydraulical

VHDL-AMS

Mixed-Signal ModelingMulti-Domain Modeling

[4, 5] Mechatronics Systems

P-N[6]

Depletion Regionb

NP

P Nvalance band

conductance band(c).

P-Nelectron – hole pair

hv Egh v

ddrift current

e


VHDL-AMS

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P-N[6]

Ip = RPinR

Responsivity Quantum efficiency[7]

Rq

h

hP

qI

rateincidentphoton

rategenerationelectron

in

P

/

/

q

v

cwhere

h

qR

24.1

[13]



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Tansimpedance Amplifier[8,9]

[10,13]

Bandwidth

Z=Vo/Ii

ARf

CdiodeCinA

CoutACnext

[9]

1

...)

1

.

1

).((1

11

2

A

CRCRs

A

CR

A

CRRs

A

RR

A

A

i

vZ

outToutAinTfoutToutAinToutAf

outAf

diode

outcl

A

Iph

VVbbiiaass

RR

Vo light

Diode Detector

Transimedance Amplifier (TIA)

Optical Fiber

RRff

CCiinnAA CCoouuttAA CCddiiooddee CCnneexxtt

A Vout


VHDL-AMS

١٩٠

1

...)

..((1 2

A

CRCRs

A

CR

A

CRs

R

i

vZ

outToutAinTfoutToutAinTf

f

diode

outcl

CinT = Cdiode +CinA CoutT = CoutA + Cnext

)..1().(

(1 outToutAinTf

f

diode

outcl

CRsA

CRs

R

i

vZ

).(

1

inAdiodetransAmp

CCRf

ABW

Operational Amplifier Modeling

ADC and DAC

Infinite open loop gain and bandwidth

Infinite common mode rejection ratio (CMRR)

Infinite input resistanceZero output resistance

Voffset = 0

input offset voltage voff

difference input resistance rinoutput resistance rout

cutoff frequency for transfer function fg1 and fg2

22

11

2

1

2

1

gg ff

[11])1)(1(

)(21

ss

AsH

A.

2

2

2121 )(dt

vd

dt

dvvvA outout

outpin

Vk = Vj

ikj = 0

il = arbitrary

ikj

j

k

ikj

il

l

+

-

A



١٩١

vin = vinp – vinniin = vin / rin

outpoutoffinoutout

out irvvkdt

vd

dt

dvv )()(0

2

2

2121

VHDL-AMS

library IEEE_proposed;use IEEE_proposed.electrical_systems.all; use ieee.math_real.all;entity opamp is generic (f1 : real := 1.0;-- First pole f2 : real := 2.0e6;-- Second pole A : real := 1.8e6);-- Open loop gain port (terminal inp : electrical; terminal inm : electrical; terminal output : electrical; terminal Vss, Vdd : electrical); end entity opamp; architecture simple1 of opamp is constant t1 : real := 1.0 / (f1*math_2_pi); constant t2 : real := 1.0 / (f2*math_2_pi); quantity vin across inp to inm; quantity vout across iout through output to ref; begin vin == (t1*t2)*vout'dot'dot/A + (t1+t2)*vout'dot/A + vout/A; end architecture simple1;

Testbench and simulation results

library IEEE_proposed;use IEEE_proposed.electrical_systems.all; use ieee.math_real.all;entity filter is end entity filter; architecture bhv of filter is quantity VD across ID through vout; begin source: Vsource (simple) generic map (dc_value := 1); port map (node1, electrical_ref); resisitor1: resistor (ideal) generic map (res:= 10000);


VHDL-AMS

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port map (node1, node2); resisitor2: resistor (ideal) generic map (res:= 10000); port map (node1, inN); capacitor1 : capacitor (ideal) generic map (cap :=113.0p, v_ic:-0.0); port map (node2, out); capacitor2 : capacitor (ideal) generic map (cap :=56.3p, v_ic:-0.0); port map (inP, electrical_ref); OpAmp: opamo (simple1) generic map (f1 := 1.0, f2 := 2.0e6, A := 1.8e6); port map (inP, inN, out,

vss, vdd); end architecture bhv;

Structural Model[12]Iph

Idark

CD



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reverse-biased capacitance

SPICE[11]

i

R

joD

v

CC

1

Cjozero-bias

junction capacitancevR i built-in voltage

RDLeakage

ResistanceRS

library ieee; use ieee.math_real.all; library ieee_proposed; use ieee_proposed.energy_systems.all; use ieee_proposed.electrical_systems.all; entity photo_diode is generic (CD : real := 1.0*PICO; -- diffusion capacitance RLEAK : real := 1.0*MEGA; -- leakage resistance RESPONSIVITY: real := 0.13; -- diode responsivity IDARK0 : real := 1.0*NANO; -- dark current at nominal temp); port (quantity ilight : in real; terminal tan, tca: electrical); end entity photo_diode; architecture bhv of photo_diode is quantity vd across id through tan to tca; quantity idark, ip, ic, ir: real; begin ir == vd/RLEAK; idark == IDARK0; ic == CD*vd'dot; ip == - RESPONSIVITY *ilight; id == idark + ip + ic + ir; end architecture bhv;

Itotal RRSS

CCDD RRDD

Iph Idark

Vo


VHDL-AMS

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testbench

library IEEE_proposed;use IEEE_proposed.electrical_systems.all; use ieee.math_real.all;entity optical_Receiver is end entity optical_Receiver; architecture optical_network of optical_receiver is quantity VD acroos ID through node1 to node2; signal ilight : real:=0.001; begin source: Vsource (simple) generic map (dc_value := -20); port map (node1, electrical_ref); photpdiode: photo_diode (bhv) generic map (CD := 1.0*PICO, RLEAK := 1.0*MEGA, RESPONSIVITY:= 0.13;

IDARK0 := 1.0*NANO); port map (ilight, node2, node1); resisitorRL: resistor (ideal) generic map (res:= 1000); port map

(node2, electrical_ref); ID == RESPONSIVITY * ilight; end architecture optical_network;

Itotal-Vo

SystemVisionV-I

Electronic Workbench MuliSim

V-Itotal P-N

Pin = 0 w Pin = 30w Pin = 50w

ID (A)

0.0 VD (V)

0.0

-2.0 -4.0 -6.0 -8.0 -10.0 -12.0 -14.0

-5.0

-10.0

-15.0

-20.0

Vb RRLL



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library IEEE_proposed;use IEEE_proposed.electrical_systems.all; use ieee.math_real.all;entity optical_Receiver2 is end entity optical_Receiver2; architecture optical_network2 of optical_receiver2 is quantity VD acroos ID through vout; signal ilight : real:=0.001; begin source: Vsource (simple) generic map (dc_value := -20); port map (inP, electrical_ref); photpdiode: photo_diode (bhv) generic map (CD := 1.0*PICO, RLEAK := 1.0*MEGA, RESPONSIVITY:= 0.13; IDARK0 := 1.0*NANO); port map (ilight, inN, electrical_ref); resisitorRL: resistor (ideal) generic map (res:= 1000); port map (inN, out); OpAmp: opamo (simple1) generic map (f1 := 1.0, f2 := 2.0e6, A := 1.8e6); port map (inP, inN, out, vss, vdd); ID == RESPONSIVITY * ilight; end architecture optical_network2;

.

Iph

VVbbiiaass

RRff

Vo light

Diode Detector


VHDL-AMS

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SystemVision

30 quantities1500

quantities

MOSFETLED



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1- LAW, A. M.; KELTON, W.D., "Simulation Modeling Analysis," 3rd Ed. McGraw-Hill, 2000, 1-8.

2- ASHENDEN, P. J.; PETERSON G.; TEEGARDEN, D. "The System Design's Guide to VHDL-AMS," Morgen Kaufman Publishers, 2004.

3- HERVÉ, H., "VHDL-AMS: Anwendungen und industrieller Einsatz," Oldenbourg Verlag, 2006.

4- MENOR GRAPHICS, "Fundamentals of VHDL-AMS for Automotive Electrical Systems," www.mentor.com, 11-16.

5- COOPER, S., "How to Model Mechatronic Systems Using VHDL-AMS," SystemVision™ Technology Series. www.mentor.com.

6- ROGERS, A., "Understanding Optical Fiber Communication," Artech House, 2001,109-125.

7- KASAP, S.O., " Optoelectronics and Photonics: Principles and Practices," Prentice-Hall, 2001, 217-254.

8- MORIKUNI, J.; KANG,S.M., "Computer-Aided Design of Optoelectronic Integrated Circuits and Systems," Prentice-Hall, 1994, 95-103.

9- INGLES, M.; STEYAET, M., "Integrated CMOS Circuit for Optical Communication." Springer Verlage, 2004, 13-40.

10- R. JAEGER and T. BLALOCK, "Microelectronic Circuit Design," McGraw-Hill, 2008, 1068-1100.

11- COOPER, R. S., "The Designer’s Guide to Analog & Mixed-Signal Modeling Illustrated with VHDL-AMS and MAST," 2004 Synopsys,

12- PÊCHEUX, F.; LALLEMENT, C. "VHDL-AMS and Verilog-AMS as Alternative Hardware Description Languages for Efficient Modeling of Multi-Discipline Systems," IEEE Transactions on Computer-Aided Design Of Integrated Circuits and Systems, Vol. 24, No. 2, February 2005.


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Documents

VHDL-AMStishreen.edu.sy/sites/default/files/Tishreen_Magazine/12_15.pdf · yet mature as digital and analog CAD. In this research, we present a contribution to modeling an optical