VHDL Lectures

Introduction to VHDL

R.B.GhongadeLecture 1

VHDL

What is VHDL? Digital system design using Hardware

Description Language is an established methodology in EDA

VHDL stands for VERY HIGH SPEED INTEGRATED CIRCUITS

HARDWARE DESCRIPTION LANUAGE

EDA stands for ELECTRONIC DESIGN AUTOMATION

FEATURES

VHDL is an amalgamation of following languages Concurrent language Sequential Language Timing Specification Simulation Language Test Language

VHDL has got powerful language constructs {ifelse}, {withselect} etc

Design hierarchies to create modular designs

Supports Design Libraries Facilitates device independent design and

portability

Concurrent Language

Concurrent statements execute at the same time in parallel as in hardware

Z

Sequential Language Sequential statements execute one at a

time in sequence As the case with any conventional

programming language the sequence of statements is important

Z

Timing Specification

Providing timing attributes in a sequential digital design is of prime importance since the operations are synchronized to a common clock

Example:processbegin

clk

Simulation language

For analyzing a digital design it is important the design be simulated

Simulation has different flavours Functional simulation Post-synthesis simulation Post- layout simulation

Any HDL should thus be equipped with simulation capability for verification and troubleshooting purposes

Test Language

Testbench It is a part of a VHDL module that generates a

set of test vectors (test inputs) and sends them to the module being tested

It collects the responses generated by the module under test and compares them against a specification of correct results

Thus testbench is required to ensure that the design is correct and that the module is operating as desired

Equivalent to checking of logical errors in any conventional programming language

Testbench use

Testtst_atst_btst_c

MODULE UNDER TEST

ABC.vhdABC_testbench.vhd

Equivalent to mechanical test jigs used for testing functionality of mass produced pcbs as in TV sets or motherboards

Design Hierarchy Hierarchy can be represented using VHDL Example

A full adder which is the top level module being composed of three lower level modules that are; half adder and OR gate

HALFADDER

HALFADDER

OR

AB

Cin

SUM

CARRY

Design hierarchy simplifies the design procedure and manageability in case of complex designs

Design Libraries Design Unit

It is any block of VHDL code or collection of VHDL codes that may be independently analyzed and inserted into a design library

Design Library It is a storage facility in which analysed VHDL

descriptions are stored for repeated uses

1

3

2

54

DesignLibrary

Simulator

Analyze

DESIGN UNIT

Logic systems Need for multi-valued logic system

Conventional logic systems have only three values i.e. 0, 1, Z

Example Consider the truth-table for AND gate

A B Y0 0 00 1 01 0 01 1 10 Z ?

HOW TO RESOLVE THIS CONDITION ?

For this problem a 9-valued logic system or package was developed that is called STD_LOGIC_1164 and it is accepted as IEEE STD 1164-1993

Multi-valued logic Unknown: value was known but not anymore Un-initialized: value was never known High impedance: net has no driver Drive strengths: handle different output

drivers Dont care: value is immaterial

Levels of abstraction

Different styles are adopted for writing VHDL code

Abstraction defines how much detail about the design is specified in a particular description

Four levels are: Layout level Logic level Register Transfer level Behavioral level LOGIC

LAYOUT

RTL

BEHAVIORAL

Layout Level

This is the lowest level and describes the CMOS layout level design on silicon

Logic Level

Design has information about Function Architecture Technology Detailed timings

Layout information and analog effects are ignored

Register Transfer Level

Using HDL every register in the design and the logic in between is defined

Design contains: Architecture information No details of technology No specification of absolute timing delays

Behavioral Level

Describing function of a design using HDL without specifying the architecture of registers

Contains timing information required to represent a function

Digital design using VHDLSTART

(STEP 1)CREATE A DIGITAL DESIGNBY

VHDL CODESCHEMATIC ENTRYSTATE DIAGRAM

(STEP 2)COMPILATION

(STEP 3)FUNCTIONAL SIMULATION

(STEP 4)(SPECIFY TARGET DEVICE)

SYNTHESIS

(STEP 5)SIMULATION

(TIMING ASPECTS)

(STEP 6)HARDWARE

PROGRAMMING

END

Active-HDLXilinx ISELibero IDE

FPGA Advantage

Active-HDLModelsim

Xilinx XSTSynplify

Leonardo Spectrum

Active-HDLModelsim

Netlist(Gate Level)

VHDL Entry(RTL Level)

Optimized Netlist(Gate Level)

Compilation

Optimization

Place & route

Physical device

Synthesis

Simulation

Simulation

Vendors providing programmable devices

Xilinx Actel Altera Cypruss Quicklogic Atmel Triscend Lattice

Next class

Elements of VHDL

Elements of VHDL


Basic building blocks

LIBRARYDECLARATIONS

ENTITY

ARCHITECTURE

CONFIGURATION

BASIC VHDL CODE

Overview

Library

It is a collection of compiled VHDL units It enables sharing of compiled designs and

hides the source code from the users Commonly used functions, procedures and

user data types can be compiled into a user defined library for use with all designs

Library should be declared before eachentity declaration even if it is in the same VHDL file

Library To declare a library (i.e. to make it visible to the

design) two lines of code are needed , onecontaining name of the library, the other a useclause

A library structure can be as follows:

FUNCTIONSPROCEDURES

TYPESCONSTANTS

COMPONENTS

LIBRARY

PACKAGE

Library syntaxLIBRARY library_name ;USE library_name.package_name.package_parts ;

LIBRARY IEEE ; -- semicolon indicatesUSE IEEE.std_logic_1164.all ; -- end of statement or

-- declarationLIBRARY work ; -- double dash (--)

-- indicates a commentUSE work.all ;

Example

Library detailsIEEE.MATH_COMPLEX.all This package defines a standard for designers

to use in describing VHDL models that make use of common COMPLEX constants and common COMPLEX mathematical functions andoperators.

IEEE.MATH_REAL.all This package defines a standard for designersto use in describing VHDL models that makeuse of common REAL constants and commonREAL elementary mathematical functions.

IEEE.NUMERIC_BIT.all This package defines numeric types andarithmetic functions for use with synthesis tools.Two numeric types are defined:-- UNSIGNED: represents an UNSIGNED number in vector form-- SIGNED: represents a SIGNED number in vector formThe base element type is type BIT.

Library detailsIEEE.NUMERIC_STD.alll This package defines numeric types and

arithmetic functions for use with synthesis tools.Two numeric types are defined:-- UNSIGNED: represents UNSIGNED number in vector form-- SIGNED: represents a SIGNED number in vector form-- The base element type is type STD_LOGIC.

IEEE.STD_LOGIC_1164.all This package defines a standard for designers to use in describing the interconnection datatypes used in VHDL modeling.Defines multi-value logic types and related functions.

IEEE.STD_LOGIC_ARITH.all This package defines a set of arithmetic,conversion, and comparison functionsfor SIGNED, UNSIGNED, SMALL_INT, INTEGER, STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR.

Library detailsIEEE.STD_LOGIC_ARITH.all This package defines a set of arithmetic,

conversion, and comparison functions forSIGNED, UNSIGNED, SMALL_INT,INTEGER, STD_ULOGIC, STD_LOGIC, andSTD_LOGIC_VECTOR. .

IEEE.STD_LOGIC_MISC.alll This package defines supplemental types, subtypes, constants, and functions for the Std_logic_1164 Package.

IEEE.STD_LOGIC_SIGNED.all This package defines a set of signedarithmetic, conversion, and comparison functions for STD_LOGIC_VECTOR.

IEEE.STD_LOGIC_TEXTIO.all This package overloads the standard TEXTIO procedures READ and WRITE.

IEEE.STD_LOGIC_UNSIGNED.all This package defines a set of unsigned arithmetic, conversion and comparison functions for STD_LOGIC_VECTOR.

Entity

It is the designs interface to the external circuitry

Equivalent to pinout /package of an IC VHDL design must include one and only one

entity per module It can be used as a component in other

entities after being compiled into a library

Entity declaration Defines the input and output ports of the design Name of the entity can be anything other than

the reserved VHDL word Each port in the port list must be allotted:

a name ( should be self-explanatory that provides information about its function

data flow direction or mode a type

Ports should be well documented with comments at the end of line providing additional information about the signal

Entity syntax

entity entity_name isport ( port_name : signal_mode signal_type ;

port_name : signal_mode signal_type ;port_name : signal_mode signal_type ) ;

end entity_name ;

Modes

Ports in the portlist have modes which indicate the driver direction

Mode also indicates whether or not the port can be read from within the entity

Four modes are available: Mode IN Mode OUT Mode INOUT Mode BUFFER

Mode INValue can be read from but not assigned to (by the entity)

ENTITY

Port signal A

Drivers resideoutside the entity

port ( A : in std_logic ) ;

Mode OUTValue can be assigned to but not read from (by the entity)

port ( B : out std_logic ) ;

ENTITY

Port signal B

Drivers resideinside the entity

Mode INOUTBi-directional , value can be assigned to as well as read from (by the entity)

port ( C : inout std_logic ) ;

ENTITY

Port signal C

Drivers reside bothinside andoutside the entity

Mode BUFFEROutput port with internal read capability

port ( D : buffer std_logic ) ;

ENTITY

Port signal D

Drivers resideinside the entity

Signal can be read inside the entityDO NOT USE UNLESS REQUIRED

Entity exampleentity and_gate is

port ( 1A , 2A , 3A, 4A : in std_logic ; 1B , 2B , 3B, 4B : in std_logic ; 1Y , 2Y , 3Y, 4Y : out std_logic ) ;

end and_gate ;

1A1

1B2

1Y3

2A4

2B5

2Y6

GND7 3Y 8

3A 9

3B 10

4Y 11

4A 12

4B 13

VCC 14

Entity exampleentity ALU is

port ( In1 : in std_logic_vector ( 3 downto 0) ; -- 1st operandIn2 ; in std_logic_vector ( 3 downto 0) ; -- 2nd operandOpsel : in std_logic_vector ( 3 downto 0) ; -- opn selectCin : in std_logic ;Mode : in std_logic ;Result : out std_logic_vector ( 3 downto 0 ) ;Cout : out std_logic ;Equal : out std_logic ) ;

end ALU ;

ALU

In1 In2 Opsel

Result

Cout

Mode

Cin

Equal

ArchitectureIt specifies

Behaviour Function Relationship between inputs and outputs of an entity

Syntaxarchitecture achitecture_name of entity_name is

[declarations] -- optionalbegin

code -- concurrent statements onlyend achitecture_name ;

Architecture can contain only concurrent statements

A design can be described in an architecture using various levels of abstraction

An entity can have more than one architectures since a function can be implemented in a number of ways

There can be no architecture without an entity

Architectural bodies Behavioural

It is the high-level description It contains a set of assignment statements to represent

behaviour No need to focus on the gate-level implementation of a design

Example:architecture behave of and_gate isbegin

process ( a, b )if a=1 and b=1 thenc

Dataflow It uses concurrent signal assignment

statements

Example:architecture dataflow of and_gate isbegin

c

Structural Components from libraries are connected

together Designs are hierarchical each component can be individually simulated it makes use of component instantiation

HALFADDER

HALFADDER

OR

AB

Cin

SUM

CARRY

Configuration Since a number of architectures can exist

for an entity , using configuration statement we can bind a particular architecture to the entity

configuration CONFIGURATION_NAME of ENTITY_NAME isfor ARCHITECTURE_NAMEend for;

end CONFIGURATION_NAME;

Syntax

Language elements

Next class

Language Elements I


VHDL is a strongly typed language Designers have to declare the type before

using it VHDL is not case sensitive ( but avoid

mixed cases as a good programming practice)

VHDL supports a wide variety of data types and operators OBJECTS OPERATORS AGGREGATES

Objects They are used to represent and store the

data in the design being described Object contains a value of specific type

Class Object Data type

SIGNAL COUNT : INTEGER

This results in an object called COUNT that holds INTEGER value that belongs to class SIGNAL

The name given to the object is called as identifier

Do not use reserved words as identifiers

Each object has a data type and class Class indicates how the object is used in the

module and what can be done with that object Type indicates what type of data the object

contains Each object belongs to one of the following class:

CONSTANT SIGNAL VARIABLE


CLASS

Data Types In order to write VHDL code efficiently it is

necessary to study the specification and use of data types

Following are the categories of data types: Pre-defined Used defined Subtypes Arrays Port arrays Records Signed and unsigned

Pre-defined data types Specified by IEEE 1076 and IEEE 1164

Package Library Type/Functions

standard std

ieee

ieee

std_logic_signed ieee Functions that allow operations with STD_LOGIC_VECTOR

ieee

BIT, BOOLEAN, INTEGER, REAL

std_logic_1164 STD_LOGIC, STD_ULOGIC

std_logic_arith SIGNED, UNSIGNED / data conversion functions

std_logic_unsigned

BIT (and BIT_VECTOR): 2 level logic (0, 1)

Examples:

SIGNAL X : BIT ;

X is declared as a one-

digit SIGNALof type BIT

SIGNAL Y : BIT_VECTOR (3 downto 0);Y is 4-bit vector,

leftmost bit is MSB

SIGNAL W : BIT_VECTOR (0 to 7);W is 8-bit

vector, rightmost bit

is MSB

To assign a value to the signal use the operator < =

Assignment examples:

X

STD_LOGIC (and STD_LOGIC_VECTOR): 8 valued logic (introduced in IEEE 1164 standard)

Symbol Description RemarkX Forcing unknown Synthesizable unknown

0 Forcing low Synthesizable logic 0

1 Forcing high Synthesizable logic 1

Z High impedance Synthesizable tri-state buffer

W Weak unknownL Weak lowH Weak high- Dont care

Examples:

SIGNAL X : STD_LOGIC ;

X is declared as a one-digit (scalar) SIGNAL of type

STD_LOGIC

SIGNAL Y : STD_LOGIC_VECTOR (3 downto 0);Y is 4-bit

vector, leftmostbit is MSB

SIGNAL Y : STD_LOGIC_VECTOR (3 downto 0) : = 0001for (optional)

initial value use :=

Most of std_logic levels are intended for simulationonly. However 0, 1 and Z are synthesizable withno restrictions

With respect to weak values, they are resolved in favour of the forcing values in multiple-driven nodes. If any two std_logic signals are connected top the same node, then conflicting logic levels are resolved by using the shown table

X 0 1 Z W L H -X X X X X X X X X0 X 0 X 0 0 0 0 X1 X X 1 1 1 1 1 XZ X 0 1 Z W L H ZW X 0 1 W W W W XL X 0 1 L W L W XH X 0 1 H W W H X- X X X X X X X X

The STD_ULOGIC has 9 valued logic levels : additional value is U for Un-resolved or Un-initialized

Other typesBOOLEAN TRUE, FALSE

INTEGER 32-bit integers (from - 2,147,483,647 to + 2,147,483,647

NATURAL Non-negative numbers (from 0 to 2,147,483,647

REAL Real numbers (from -1.0E-38 to +1.0E38)

Physical literals

Used to inform physical quantities like , time, voltage etc. Useful for simulation but not synthesizable

Character literals

Single ASCII character or a string of such characters. Not synthesizable

SIGNED, UNSIGNED

They have appearance of STD_LOGIC_VECTOR, but accept arithmetic operations which are typical of INTEGER data type

User defined data types

VHDL allows user defined data types Two categories of this data type are:

Integer Enumerated

User defined integer typeTYPE my_integer IS RANGE -32 to +32 ;

TYPE student_grade IS RANGE 0 to 100 ;

User defined enumerated typeTYPE my_logic IS (0, 1, Z );

TYPE my_state IS ( idle, forward, backward, stop) ;

An enumerated type, typically used in state machines

The encoding of enumerated types is done sequentially and automatically

Since here there are 4 states only two bits are required hence 00 is assigned to first state ( idle), 01 to second state (forward) and so on.

Subtypes

A SUBTYPE is a TYPE with a constraint Though operations between data of

different types are not allowed, they are allowed between the subtype and its corresponding base type

SUBTYPE sub_state IS my_state RANGE idle to backward ;

This means that the subtype sub_state =(idle, forward, backward)

Arrays Arrays are collections of objects of same type Can be 1-dimensional, 2-dimensionl or

1D X 1D Higher dimensional arrays are possible but not

synthesizable

0 0 1 0 0

1 0 1 0

1 1 0 0

0 1 0 0

1 1 0 1

0 1 0 1 0

1 0 1 1 0

0 1 0 1 0Scalar 1D

1D x 1D2D data array

Array syntax

TYPE type_name IS ARRAY (specification) OF data_type ;

To specify an array :

SIGNAL signal_name : type_name [:= initial_value]

To use an array :

Example : 1D x 1D array We want to build an array containing 4

vectors, each of size 8 bits we will call each vector as row and the

complete array as matrix

TYPE row IS ARRAY (7 downto 0 ) OF STD_LOGIC ;TYPE matrix IS ARRAY (3 downto 0 ) OF row ;SIGNAL X : matrix ;

1D x 1D SIGNAL

Example : 2D array This array will be created with scalars only

TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0 ) OF STD_LOGIC ;

L

M L

M

ROWS

COLUMNS

Port Arrays

In the specification of the input or output pins (PORTS) of a circuit (which is made in the ENTITY), we might need to specify the ports as arrays of vectors.

Since TYPE declarations are not allowed in an ENTITY, the solution is to declare user-defined data types in a PACKAGE, which will then be visible to the whole design (thus including the ENTITY)

------- Package: --------------------------LIBRARY ieee;USE ieee.std_logic_1164.all;----------------------------PACKAGE my_data_types ISTYPE vector_array IS ARRAY (NATURAL RANGE ) OFSTD_LOGIC_VECTOR(7 DOWNTO 0);END my_data_types;--------------------------------------------------- Main code: -------------------------LIBRARY ieee;USE ieee.std_logic_1164.all;USE work.my_data_types.all; -- user-defined package---------------------------ENTITY mux ISPORT (inp: IN VECTOR_ARRAY (0 TO 3);... );END mux;... ;--------------------------------------------

As can be seen in the example above, a user-defined data type, called vector_array,wascreated, which can contain an indefinite number of vectors of size eight bits each (NATURAL RANGE signifies that the range is not fixed, with the only restriction that it must fall within the NATURAL range, which goes from 0 to +2,147,483,647)

The data type was saved in a PACKAGE called my_data_types, and later used in an ENTITY to specify a PORT called inp

Notice in the main code the inclusion of an additional USE clause to make the user-defined package my_data_types visible to the design.

Records

Records are similar to arrays, with the only difference that they contain objects of different types.

TYPE birthday IS RECORDday: INTEGER RANGE 1 TO 31;month: month_name;END RECORD;

Signed and Unsigned data types

These types are defined in the std_logic_arith package of the ieee library

Examples:SIGNAL x: SIGNED (7 DOWNTO 0);SIGNAL y: UNSIGNED (0 TO 3);

An UNSIGNED value is a number never lower than zero. For example, 0101represents the decimal 5, while 1101 signifies 13.

If type SIGNED is used instead, the value can be positive or negative (in twos complement format). Therefore,0101 would represent the decimal 5, while 1101 would mean 3.

To use SIGNED or UNSIGNED data types, the std_logic_arith package, of the ieee library, must be declared

Next class

Language Elements II

Language Elements II


Operators

VHDL provides several kinds of pre-defined operators Assignment operators Logical operators Arithmetic operators Relational operators Shift operators Concatenation operators

Assignment operators Are used to assign values to signals, variables,

and constants.

Used to assign values to individual vector elements or with OTHERS

SIGNAL x : STD_LOGIC;VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);

x

Logical operators

Used to perform logical operations. The data must be of type:

BIT, STD_LOGIC STD_ULOGIC BIT_VECTOR STD_LOGIC_VECTOR STD_ULOGIC_VECTOR

The logical operators are: NOT AND OR NAND NOR XOR XNOR

The NOToperator has precedence

over the others

Examples:y

Arithmetic operators

Used to perform arithmetic operations. The data can be of type INTEGER, SIGNED, UNSIGNED, or REAL (the last cannot be synthesized directly).

Also, if the std_logic_signed or the std_logic_unsigned package of the ieee library is used, then STD_LOGIC_VECTOR can also be employed directly in addition and subtraction operations

+ ( Addition) - (Subtraction) * (Multiplication) / (Division) ** (Exponentiation) MOD ( Modulus) REM ( Remainder) ABS ( Absolute value)

There are no synthesis restrictions regarding addition and subtraction, and the same is generally true for multiplication

For division, only power of two dividers (shift operation) are allowed

For exponentiation, only static values of base and exponentare accepted Regarding the mod and rem operators, y mod x returns the remainder of y/x with the signal of x, while y rem x returns the remainder of y/x with the signal of y

Finally, abs returns the absolute value

For mod, rem, abs , there generally is little or nosynthesis support

Comparison operators

= Equal to /= Not equal to < Less than > Greater than = Greater than or equal to

Also called RELATIONALoperators

Shift operators sll shift left logical srl shift right logical sla shift left arithmetic sra shift right arithmetic ror rotate left logical rol rotate right logical

0

0

LOGICAL SHIFTING

ARITHMETIC SHIFTING(retains sign bit)

ROTATE

LOGICAL ARITHMETIC ROTATE

Concatenation operator

Operands can be one-dimensional array type or element type

& works on vectors only

& Concatenation

Example:SIGNAL a : STD_LOGIC_VECTOR ( 5 DOWNTO 0 ) ;SIGNAL b,c,d : STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ;BEGIN

b

Operator summary

Operator type Operators Data types

Logical NOT, AND, ANDOR, NOR, XOR, XNOR

BIT, BIT_VECTOR, STD_LOGIC, STD_LOGIC_VECTOR, STD_ULOGIC, STD_ULOGIC_VECTOR

Arithmetic +, -,*,/,** (mod, rem , abs) INTEGER, SIGNED, UNSIGNED

Comparison =, /=, , = All above

Shift sll, srl, sla, sra, rol, ror BIT_VECTOR

Concatenation &, ( , , , ) Same as for logical operators, plusSIGNED and UNSIGNED

Operator overloading

Operators can be user-defined Let us consider the pre-defined arithmetic

operators seen earlier (+,- , *, /, etc.). They specify arithmetic operations between data of certain types (INTEGER, for example)

For instance, the pre-defined + operator does not allow addition between data of type BIT.

We can define our own operators, using the same name as the pre-defined ones

For example, we could use + to indicate a new kind of addition, this time between values of type BIT_VECTOR. This technique is called operator overloading

Example: Consider that we want to add an integer to a binary 1-bit number. Then the following FUNCTION could be used

FUNCTION "+" (a: INTEGER, b: BIT) RETURN INTEGER ISBEGINIF (b='1') THEN RETURN a+1;ELSE RETURN a;END IF;END "+";

A call to the function above could thus be the following:SIGNAL inp1, outp: INTEGER RANGE 0 TO15;SIGNAL inp2: BIT;(...)outp

Aggregates

It assigns values to elements of an array

a 0 ) ; a 1, OTHERS => 0 ) ;is equivalent to a

Each object has a data type and class Class indicates how the object is used in the

module and what can be done with that object Type indicates what type of data the object

contains Each object belongs to one of the following class:



CLASS

Classes re-visited

Constants These are identifiers with fixed values The value is assigned only once when

declared Values cannot be changed during

simulationCONSTANT bus_width : INTEGER :=16 ;CONSTANT CLK_PERIOD : TIME :=15 ns ;

Constants make the design description more readable

Design changed at later time becomes easy

Signals

Equivalent to wireswithin a circuit

Example:architecture and_gate of myand issignal TEMP : STD_LOGIC ;begin

U1 : AND2 portmap ( a, b, TEMP ) ;U2 : AND2 portmap (TEMP, c , d ) ;

end and_gate ;

a

bAND2

TEMP

cAND2

d

Thus signals are used : to connect design entities together and

communicate changes in values within a design

instead of INOUT mode Each signal has a history of values i.e.

they hold a list of values which include current value of the signal and a set of possible future values that can appear on the signal

Computed value is assigned to signal afterspecified delay called DELTA DELAY

Variables

These are objects with single current value

They are used to store the intermediate values between the sequential statements

Variable assignment occurs immediately Variables can be declared and used inside

the process statement only. But they retain their value throughout the entire simulation

process ( a )variable count : INTEGER : = 1 ;begin

count : = count+ 1 ;end process ;

Example :

count contains the total number of events that occurred on signal a

Language elements III

Next class

Language Elements III


Attributes

An attribute is data that are attached to VHDL objects or predefined data about VHDL objects

Examples are the current drive capability of a buffer or the maximum operating temperature of the device

Types are Data Attributes Signal Attributes User-defined Attributes

Data AttributesThe pre-defined, synthesizable data attributes

are the following: dLOW : Returns lower array index dHIGH : Returns upper array index dLEFT : Returns leftmost array index dRIGHT : Returns rightmost array index dLENGTH : Returns vector size dRANGE : Returns vector range dREVERSE_RANGE: Returns vector range

in reverse order

Example

Consider the following signal:SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);Then:d'LOW=0, d'HIGH=7, d'LEFT=7, d'RIGHT=0, d'LENGTH=8, d'RANGE=(7 downto 0), d'REVERSE_RANGE=(0 to 7)

If the signal is of enumerated type, then: dVAL(pos) : Returns value in the position

specified dPOS(value) : Returns position of the

value specified dLEFTOF(value) : Returns value in the

position to the left of the value specified dVAL(row, column) : Returns value in the

position specified; etcThere is little or no synthesis support for enumerated data type attributes

Signal AttributesLet us consider a signal sThen: sEVENT : Returns true when an event occurs

on s sSTABLE : Returns true if no event has

occurred on s sACTIVE : Returns true if s = 1 sQUIET : Returns true if no event has

occurred during the time specified sLAST_EVENT : Returns the time elapsed since last

event sLAST_ACTIVE: Returns the time elapsed since

last s=1 sLAST_VALUE : Returns the value of s before the

last event; etc.

ExampleAll four assignments shown below are synthesizable and equivalent. They return TRUE when an event (a change) occurs on clk, AND if such event is upward(in other words, when a rising edge occurs on clk)

IF (clk'EVENT AND clk='1')... -- EVENT attribute-- used with IFIF (NOT clk'STABLE AND clk='1')... -- STABLE --attribute used

-- with IFWAIT UNTIL (clk'EVENT AND clk='1'); -- EVENT --attribute used

-- with WAITIF RISING_EDGE(clk)... -- call to a function

User-defined Attributes VHDL also allows the construction of user-defined

attributes To employ a user-defined attribute, it must be

declared and specifiedAttribute Declaration:ATTRIBUTE attribute_name: attribute_type ;

Attribute Specification:ATTRIBUTE attribute_name OF target_name: class IS value;where:attribute_type: any data type (BIT, INTEGER, STD_LOGIC_VECTOR, etc.)class: TYPE, SIGNAL, FUNCTION, etc.value: 0, 27, 00 11 10 01, etc.

ExampleATTRIBUTE number_of_inputs: INTEGER;

ATTRIBUTE number_of_inputs OF nand3: SIGNAL IS 3;

...

inputs

Generics As the name suggests, GENERIC is a way

of specifying a generic parameter a static parameter that can be easily

modified and adapted to different applications

The purpose is to make the code more flexible and reusable

must be declared in the ENTITY More than one GENERIC parameter can

be specified in an ENTITY

SyntaxGENERIC (parameter_name : parameter_type := parameter_value);

The GENERIC statement below specifies a parameter called n, of type INTEGER, whose default value is 8. Therefore, whenever n is found in the ENTITY itself or in the ARCHITECTURE (one or more) that follows, its value will be assumed to be 8

ENTITY my_entity ISGENERIC (n : INTEGER := 8; vector: BIT_VECTOR := "00001111");PORT (...);END my_entity;ARCHITECTURE my_architecture OF my_entity IS...END my_architecture;

Example

ARCHITECTURE generic_decoder OF decoder ISBEGINPROCESS (ena, sel)VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0);VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH;....

Example

Delays in VHDL

In VHDL, there are three types of delay that are encountered

Inertial delay Transport delay Delta delay

Inertial Delay

Inertial delay is the default in VHDL Behaves similarly to the actual device Output signal of the device has inertia,

which must be overcome for the signal to change value

The inertial delay model is by far the most commonly used in all currently available simulators

Inertial delay prevents prolific propagation of spikes throughout the circuit

LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY buf ISPORT ( a : IN std_logic;PORT ( b : OUT std_logic);END buf;ARCHITECTURE buf OF buf ISBEGINb

Transport Delay

It represents a wire delay in which any pulse, no matter how small, is propagated to the output signal delayed by the delay value specified

Especially useful for modeling delay line devices, wire delays on a PCB, and path delays on an ASIC

LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY delay_line ISPORT ( a : IN std_logic;PORT ( b : OUT std_logic);END delay_line;ARCHITECTURE delay_line OF delay_line ISBEGINb

Delta delay These are used since the PC that

processes and simulates a concurrent phenomenon is basically a sequential machine

The simulation program mimics concurrency by scheduling events in some order

Simulation deltas are used to order some types of events during a simulation

Specifically, zero delay events must be ordered to produce consistent results

Circuit that shows the difference!

CLK

D

E

Q'

Q

DFF

CLK

A

B

C

F

Zero delay componentsCLK=1A=1

Assumptions

Problem when no delta delay concept is used

CLK

D

E

Q'

Q

DFF

CLK

A

B

C

F

CLK

D

E

Q'

Q

DFF

CLK

A

B

C

F

CLK

D

E

Q'

Q

DFF

CLK

A

B

C

F

1) A becomes 0

2) Evaluate inverter

3) B

Problem when no delta delay concept is used

CLK

D

E

Q'

Q

DFF

CLK

A

B

C

F

DD

1) A becomes 0

2) Evaluate inverter

3) B

Delta delay useDelta 1

Delta 2

Delta 3

Delta 4

10 ns

11 ns

A

Concurrent Statements and

Constructs

Combinational vs. Sequential LogicThe output of the circuit depends solely on thecurrent inputs

Output does depend onprevious inputs hence storage elements arerequired

Combinational Logic

outputinput

StorageElements

PresentState

NextState

Combinational Logic outputinput

Concurrent Code Consider the following

statement:X = X + Y ;

In conventional softwareX and Y are registerlocations hence contentsof X and Y are added andstored in X

Register X Register Y

+

Difference in VHDL

In VHDL the same statement will mean a feedback in a purely combinational logic which is invalid

+

X Y

VHDL code is inherently concurrent (parallel) Only statements placed inside a PROCESS,

FUNCTION, or PROCEDURE are sequential Concurrent code is also called dataflow code Order does not matter We can only build combinational logic circuits

with concurrent code Concurrent assignment produces one driver for

each assignment statement

z

Multiple driver assignmentarchitecture ABC of XYZ issignal z,a,b,c,d : std_logic ;begin

z

Concurrent constructs

Next Class

Digital Hardware Revision

R.B.GhongadeLecture 6, 7

Digital Logic Binary system -- 0 & 1, LOW & HIGH, negated

and asserted. Basic building blocks -- AND, OR, NOT

A1B1A2B2

Z1

Z2

XY

Z

F

X Y

X Y Z

X

YX Y + X Y Z

Many representations of digital logic Transistor-level

circuit diagrams

Gate symbols (for simple elements)

A

B

S

VCC

Z

Truth tables

Logic diagrams

A

S

B

Z

SN ASN

SB

Table 1 -1Truth table for the multiplexer function.

S A B Z

0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

Prepackaged building blocks, e.g. multiplexer

Equations: Z = S A + S B

74x157

1A1B2A2B3A3B4A4B

G

241Y

72Y

93Y

124Y

35

611

1014

13

S115

S

BA

Z

Copyright 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e

Various hardware description languages ABEL

VHDL

Well start with gates and work our way up

module chap1muxtitle 'Two-input multiplexer example'CHAP1MUX device 'P16V8'

A, B, S pin 1, 2, 3;Z pin 13 istype 'com';

equations

WHEN S == 0 THEN Z = A; ELSE Z = B;

end chap1mux

Table 1-3VHDL program for the multiplexer.

library IEEE;use IEEE.std_logic_1164.all;

entity Vchap1mux is port ( A, B, S: in STD_LOGIC; Z: out STD_LOGIC );end Vchap1mux;

architecture Vchap1mux_arch of Vchap1mux isbegin Z

Logic levels Undefined region

is inherent digital, not analog amplification,

weak => strong Switching threshold varies with voltage, temp,

process need noise margin

The more you push the technology, the more analog it becomes.

Logic voltage levels decreasing with process 5 -> 3.3 -> 2.5 -> 1.8 V

5.0 V

3.5 V

1.5 V

0.0 V

Logic 1 (HIGH)

Logic 0 (LOW)

undefinedlogic level


MOS Transistors

VIN


gate drain

source

Voltage-controlled resistance:increase Vgs ==> decrease Rds

Note: normally, Vgs 0Vgs

+


gate drain

source

Voltage-controlled resistance:decrease Vgs ==> decrease Rds

Note: normally, Vgs 0

Vgs+


NMOS

PMOS

Voltage-controlled resistance

CMOS Inverter

Switch model

VDD = +5.0 V

VOUT = HVIN = L

(a)VDD = +5.0 V

VOUT = LVIN = H

(b)


Alternate transistor symbols

Q2(p-channel)

VIN

VDD = +5.0 V

VOUTQ1

(n-channel)

on whenVIN is low

on whenVIN is high


CMOS Gate Characteristics No DC current flow into MOS gate terminal

However gate has capacitance ==> current required for switching (CV2f power)

No current in output structure, except during switching Both transistors partially on Power consumption related

to frequency Slow input-signal rise times

==> more power Symmetric output structure

==> equally strong drive in LOW and HIGH states

Q2(p-channel)

VIN

VDD = +5.0 V

VOUTQ1

(n-channel)

on whVIN is

on wheVIN is


CMOS NAND Gates Use 2n transistors for n-input gate

CMOS NAND -- switch modelVDD

A = L

Z = H

(a)

B = L

VDD

A = H

Z = H

(b)

B = L

A =

(c

B =


VDD

Z = H

VDD

A = H

Z = H

(b)

B = L

VDD

A = H

Z = L

(c)

B = H


VDD

Z = H

VDD

A = H

Z = L

(c)

B = H

t 2000 by Prentice Hall, Inc.ign Principles and Practices, 3/e

CMOS NAND -- more inputs (3)

Inherent inversion. Non-inverting buffer:

2-input AND gate:VDD

A

B

ZQ1

Q3 Q5

Q2 Q4 Q6A

LLHH

B

LHLH

Q1

offoffonon

Q2

ononoffoff

Q3

offonoffon

Q4

onoffonoff

Q6

offoffoffon

Q5

onononoff

Z

LLLH

(a)

(b)

(c) AB Z


CMOS NOR Gates Like NAND -- 2n transistors for n-input gate

A

LLHH

B

LHLH

Q1

offoffonon

Q2

ononoffoff

Q3

offonoffon

Q4

onoffonoff

Z

HLLL

AB

Z

VDD

A

B

Z

Q2

Q4

Q1 Q3

(a)

(b)

(c)


NAND vs. NOR For a given silicon area, PMOS transistors are

weaker than NMOS transistors.VDD

A

B

Z

Q1

Q3

Q2 Q4A

LLHH

B

LHLH

Q1

offoffonon

Q2

ononoffoff

Q3

offonoffon

Q4

onoffonoff

Z

HHHL

AB

Z

(a)

(b)

(c)


NANDA

LLHH

B

LHLH

Q1

offoffonon

Q2

ononoffoff

Q

oooo

AB

VDD

A

B

Z

Q2

Q4

Q1 Q3

(a)

(b)

(c)

Copyright 2000 by PrentDigital Design Principles and

NOR

Result: NAND gates are preferred in CMOS.

For a given Si area , n-channel transistor has lower on resistance than p-channel transistor. Thus when transistors are put in series, a K n-channel transistors have lower on resistance than K p-channel ones. Hence a K-input NAND gate is generally faster and preferred over a K- input NOR gate

Limited # of inputs in one gate 8-input CMOS NAND

I5OUTOUT

I6I7I8

I1I2I3I4

I5I6I7I8

I1I2I3I4


More complicated

CMOS AND-OR-INVERT gate

VDD

C

A

B

D

Z

Q5

Q7

Q3

Q1

Q6 Q8

Q2 Q4C

LLHHLLHHLLHHLLHH

B

LLLLHHHHLLLLHHHH

A

LLLLLLLLHHHHHHHH

D

LHLHLHLHLHLHLHLH

Q1

offoffoffoffoffoffoffoffonononononononon

Q2

ononononononononoffoffoffoffoffoffoffoff

Q3

offoffoffoffononononoffoffoffoffonononon

Q5

offoffononoffoffononoffoffononoffoffonon

Q

oooooooooooooooo

Q6

ononoffoffononoffoffononoffoffononoffoff

Q4

ononononoffoffoffoffononononoffoffoffoff

(b)(a)

Copyright 2000 by PreDigital Design Principles a

A

B

C

D

Z


CMOS Electrical Characteristics Digital analysis works only if circuits are

operated in spec: Power supply voltage Temperature Input-signal quality Output loading

Must do some analog analysis to prove that circuits are operated in spec. Fanout specs Timing analysis (setup and hold times)

DC Loading An output must sink

current from a load when the output is in the LOW state.

An output must source current to a load when the output is in the HIGH state.

VCC

VOLmax

IOLmax

VIN VIN

Rn

Rp > 1 M

(a)

CMOSinverter

resistiveload

VCC

VOHmin

IOHmaxRn > 1 M

Rp

(b)

CMOSinverter

resistiveload

"sinking current"

"sourcing current"


Output-voltage drops Resistance of off transistor is > 1 Megohm,

but resistance of on transistor is nonzero, Voltage drops across on transistor, V = IR

For CMOS loads, current and voltage drop are negligible.

For TTL inputs, LEDs, terminations, or other resistive loads, current and voltage drop are significant and must be calculated.

Example loading calculation Need to know on and off resistances of

output transistors, and know the characteristics of the load.

VCC = +5.0 V

VOUTVIN

Rn

Rp

2 k

1 k

(a)CMOSinverter

resistiveload

VCC = +5.0 V

VOUTVIN

Rn

Rp

(b)CMOSinverter

Thvenin equivalentof resistive load

+

VThev = 3.33 V

RThev = 667


Calculate for LOW state

VCC = +5.0 V

VOUT = 0.43 VVIN = +5.0 V

100

> 1 M

CMOSinverter


+

VThev = 3.33 V

RThev = 667

(HIGH) (LOW)


out 10= 3.33 0.43

6601007

V V V =+

Calculate for HIGH stateVCC = +5.0 V

VOUT = 4.61 VVIN = +0.0 V

> 1 M

200

CMOSinverter


+

VThev = 3.33 V

RThev = 667

(LOW) (HIGH)


out 667= (3.33 ) (5 3.33 )

2004.61

667V V V V V + = +

Limitation on DC load If too much load, output voltage will go outside

of valid logic-voltage range.

VOHmin, VIHmin VOLmax, VILmax

High-stateDC noise margin

Low-stateDC noise margin

0.7 VCC

0.3 VCC

VCC

0

VIHmin

VOHmin

VOLmax

VILmax

HIGH

ABNORMAL

LOW


Output-drive specs VOLmax and VOHmin are specified for certain

output-current values, IOLmax and IOHmax. No need to know details about the output circuit,

only the load.VCC

VOLmax

IOLmax

VIN VIN

Rn

Rp > 1 M

(a)

CMOSinverter

resistiveload

VCC

Rn > 1

Rp

(b)

"sinking current"

"sourcing current"

VINresistive

load

VCC

VOHmin

IOHmaxRn > 1 M

Rp

(b)

CMOSinverter

resistiveload

"sourcing current"


Input-loading specs Each gate input requires a certain amount of

current to drive it in the LOW state and in the HIGH state. IIL and IIH These amounts are specified by the manufacturer.

Fanout calculation (LOW state) The sum of the IIL values of the driven

inputs may not exceed IOLmax of the driving output. (HIGH state) The sum of the IIH values of the driven

inputs may not exceed IOHmax of the driving output. Need to do Thevenin-equivalent calculation for non-

gate loads (LEDs, termination resistors, etc.)

Manufacturers data sheetTable 3 -3 Manufacturer's data sheet for a typical CMOS device, a 54/74HC00 quad NAND gate.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGEThe following conditions apply unless otherwise specified:Commercial: TA = 40C to +85C, VCC = 5.0V5%; Military: TA = 55C to +125C, VCC = 5.0 V 10%

Sym. Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

VIH Input HIGH level Guaranteed logic HIGH level 3.15 V

VIL Input LOW level Guaranteed logic LOW level 1.35 V

IIH Input HIGH current VCC = Max., VI = VCC 1 AIIL Input LOW current VCC = Max., VI = 0 V 1 AVIK Clamp diode voltage VCC = Min., IN = 18 mA 0.7 1.2 V

IIOS Short-circuit current VCC = Max.,(3) VO = GND 35 mA

VOH Output HIGH voltageVCC = Min.,VIN = VIL

IOH = 20 A 4.4 4.499 V

IOH = 4 mA 3.84 4.3 V

VOL Output LOW voltageVCC = Min.VIN = VIH

IOL = 20 A .001 0.1 V

IOL = 4 mA 0.17 0.33

ICC Quiescent powersupply current

VCC = Max. VIN = GND or VCC, IO = 0

2 10 A

SWITCHING CHARACTERISTICS OVER OPERATING RANGE, CL = 50 pF

Sym. Parameter(4) Test Conditions Min. Typ. Max. Unit

TTL Electrical Characteristics

Q5

VCC = +5 V

R120 k

D1X

D1Y

D2X D2Y

R28 k

R41.5 k

R312 k

Q2

X

YZ

R5120

Q3Q4

R64 k

R73 k

Q6

D3D4

Diode AND gateand input protection Phase splitter Output stage

VA


TTL LOW-State BehaviorVCC = +5 V

R2A8 k

R4A1.5 k

R5A120

R6A4 k

R7A3 k

D3AD4A(ON)

Q2A

(ON)Q6A

(ON)Q5A

(OFF)Q4A(OFF)

Q3A

R1B20 k

D1XB

D1YB

D2XB D2YB

R2B8 k

R4B1.5 k

R3B12 k2 V

(OFF)Q2B

0.35 V


TTL HIGH-State BehaviorVCC = +5 V

R2A8 k

R4A1.5 k

R5A120

R6A4 k

R7A3 k

D3AD4A

2.7 V

(OFF)Q2A

(OFF)Q6A

(OFF)Q5A

(ON)Q4A(ON)

Q3A

R1B20 k

D1XB

D1YB

D2XB D2YB

R2B8 k

R4B1.5 k

R3B12 k2 V

(ON)Q2B

Ileak


TTL Logic Levels and Noise Margins Asymmetric, unlike CMOS

CMOS can be made compatible with TTL T CMOS logic families



VCC = 5 V

0

VIHmin = 2.0 VVOHmin = 2.7 V

VOLmax = 0.5 VVILmax = 0.8 V

ABNORMAL

LOW

HIGH


CMOS vs. TTL Levels



0.7 VCC

0.3 VCC

VCC

0

VIHmin

VOHmin

VOLmax

VILmax

HIGH

ABNORMAL

LOW


CMOS levels VCC = 5 V

0

VIHmin = 2.0 VVOHmin = 2.7 V

VOLmax = 0.5 VVILmax = 0.8 V

ABNORMAL

LOW

HIGH


TTL levels



0.7 VCC

0.3 VCC

VCC

0

VIHmin

VOHmin

VOLmax

VILmax

HIGH

ABNORMAL

LOW

Copyright 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/eCMOS with TTL Levels

-- HCT, FCT, VHCT, etc.

TTL differences from CMOS Asymmetric input and output characteristics. Inputs source significant current in the LOW

state, leakage current in the HIGH state. Output can handle much more current in the

LOW state (saturated transistor). Output can source only limited current in the

HIGH state (resistor plus partially-on transistor). TTL has difficulty driving pure CMOS inputs

because VOH = 2.4 V (except T CMOS).

AC Loading AC loading has become a critical design factor

as industry has moved to pure CMOS systems. CMOS inputs have very high impedance, DC loading

is negligible. CMOS inputs and related packaging and wiring have

significant capacitance. Time to charge and discharge capacitance is a major

component of delay.

Transition times

(a)

(b)

(c)

tr tf

tr tf

HIGH

LOW

VIHminVILmax


Circuit for transition-time analysisVCC = +5.0 V

VOUTVIN

Rn

Rp

CMOSinverter

Equivalent load fortransition-time analysis

+

VL

RL

CL


HIGH-to-LOW transition

VCC = +5.0 V

VOUT = 5.0 V

IOUT = 0VIN

> 1 M

200

100 pF

AC load

VCC

VIN

(a) (b)

IOUT100 pF

ad

VCC = +5.0 V

VOUTVIN

AC load

100 pF

(b)

100

> 1 M


Exponential rise time

VOUT

5 V

0 Vtime0

Rn

> 1 M

100

Rp

> 1 M

200

tr

1.5 V

3.5 V


LOW-to-HIGH transitionVCC = +5.0 V

VOUT = 0 V

IOUT = 0VIN

100

> 1 M

100 pF

AC load

V

VIN

(a) (b)

IOUT0 pF

d

VCC = +5.0 V

VOUTVIN

> 1 M

200 AC load

100 pF

(b)Copyright 2000 by Prentice Hall, Inc.

Digital Design Principles and Practices, 3/e

Exponential fall time

VOUT

5 V

0 Vtime

tf

0

1.5 V

3.5 V

Rn

> 1 M

100

Rp

> 1 M

200


t = RC time constantexponential formulas, e-t/RC

Transition-time considerations Higher capacitance ==> more delay Higher on-resistance ==> more delay Lower on-resistance requires bigger

transistors Slower transition times ==> more power

dissipation (output stage partially shorted) Faster transition times ==> worse

transmission-line effects (Chapter 11) Higher capacitance ==> more power

dissipation (CV2f power), regardless of rise and fall time

Open-drain outputs No PMOS transistor, use resistor pull-up

VCC

A

B

Z

Q1

Q2

A

LLHH

B

LHLH

Q1

offoffonon

Q2

offonoffon

Z

openopenopen

L

AB

Z

(a) (b)

(c)


What good is it? Open-drain bus

Problem -- really bad rise time

Data1Enable1

Data2Enable2

Data3Enable3

Data4Enable4

Data7Enable7

Data8Enable8

VCC

RDATAOUT

Data5Enable5

Data6Enable6


Open-drain transition times Pull-up resistance is larger than a PMOS

transistors on resistance.

Can reduce rise time by reducing pull-up resistor value But not too much

tr

VOUT5 V

3.5 V

1.5 V

0 V0 50 100 150 200 250 300 time

tf


Next Class

Language Elements IV

Concurrent Constructs


Types of concurrent constructs

when else with select

These constructs need not be in the process

whenelse A concurrent statement which assigns one of

several expressions to a signal, depending on the values of Boolean conditions which are tested insequence

Equivalent to a process containing an if statement

Syntax[Label:] Target

Where to use ?architecture begin HERE - endblock begin HERE - endgenerate begin HERE - end

Rules: The reserved word guarded may only appear in a

signal assignment within a guarded block. A guarded assignment only executes when the guard expression on the surrounding block is true

An Expression on the right hand side may be replaced by the reserved word unaffected

Synthesis Conditional signal assignments are synthesized to

combinational logic The Expressions on the right hand side are multiplexed

onto the Target signal The resulting logic will be priority encoded, because the

conditions are tested in sequence

Remarks: Conditional and selected signal assignments are a

concise way to describe combinational logic in Register Transfer Level descriptions, although processes can be easier to read and maintain in some cases

A conditional assignment is a neat way to convert from a Boolean condition to the type Std_logic

Examplez

Example (Tri-state Buffer)architecture tri_buff of tri_buff_part isbeginout1

withselect A concurrent statement which assigns

one of several expressions to a signal,depending on the value of the expression atthe top.

Equivalent to a process containing a case statement

Syntax[Label:] with Expression selectTarget

Where to use ?architecture begin HERE endblock begin HERE endgenerate begin HERE end

Rules: Every case of the Expression at the top must be

covered once and only once by the choices An Expression on the right hand side may be

replaced by the reserved word unaffected All possible choices must be enumerated others clause is important since we have 9-

valued logic

Synthesis Selected signal assignments are

synthesized to combinational logic The Expressions on the right hand side

are multiplexed onto the Target signal

Remarks: Conditional and selected signal

assignments are a good way to describecombinational logic in Register Transfer Level descriptions

Example (Multiplexer)architecture mux41 of mux is -- Assumptionsbegin -- a,b,c,d,z arewith control select -- std_logicz

Block

There are two types of blocks Simple Guarded

Simple block

The BLOCK statement, in its simple form, represents only a way of locally partitioning the code

It allows a set of concurrent statements to be clustered into a BLOCK, with the purpose of turning the overall code more readable and more manageable (which might be helpful when dealing with long codes)

Syntaxlabel: BLOCK[declarative part]BEGIN(concurrent statements)END BLOCK label;

ARCHITECTURE example...BEGIN...block1: BLOCKBEGIN...END BLOCK block1 ;...block2: BLOCKBEGIN...END BLOCK block2 ;...END example ;

General form of architecture using

block for partitioning

Block can be nested inside another blockSyntaxlabel1: BLOCK[declarative part of top block]BEGIN[concurrent statements of top block]label2: BLOCK[declarative part nested block]BEGIN(concurrent statements of nested block)END BLOCK label2;[more concurrent statements of top block]END BLOCK label1;

Guarded block A guarded BLOCK is a special kind of

BLOCK, which includes an additional expression, called guard expression

A guarded statement in a guarded BLOCK is executed only when the guard expression is TRUE

Syntaxlabel: BLOCK (guard expression)[declarative part]BEGIN(concurrent guarded and unguarded statements)END BLOCK label;

Even though only concurrent statements can be written within a BLOCK, with a guarded BLOCK even sequential circuitscan be constructedLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY latch ISPORT (d, clk: IN STD_LOGIC;q: OUT STD_LOGIC);END latch;ARCHITECTURE latch OF latch ISBEGINb1: BLOCK (clk='1')BEGINq

LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY DFF ISPORT (d, clk, rst: IN STD_LOGIC;q: OUT STD_LOGIC);END DFF;ARCHITECTURE DFF OF DFF ISBEGINb1: BLOCK (clkEVENT AND clk='1')BEGINq

Homework Problems

1)Generic encoder

2) 8- bit ALU

For ALU in problem 2sel Operation Function Unit

0000 y

3) Priority Encoder

The circuit must encode the address of the input bit of highest order that is active. 000 should indicate that there is no request at the input (no bit active)

Expected waveform for Problem 3

Component Instantiation

Next Class

DO NOT MISSIN ANY CASE !

Component Instantiation

R.B.GhongadeLecture 9,10,11

Component A component is analogous to a chip socket; it gives an

indirect way to use one hierarchical block within another A component is instantiated within an architecture, and

is associated with a (lower level) entity and architecture during elaboration using information from a configuration.

A component declaration is similar in form to an entity declaration, in that it includes the required ports and parameters of the component

The difference is that it refers to a design described in a separate VHDL file

The ports and parameters in the component declaration may be a subset of those in the component file, but they must have the same names

Component can be declared in the main code itself

Component can be declared in a package

Syntax :COMPONENT component_nameGENERIC ( parameter_name : string := default_value ;parameter_name : integer := default_value);PORT (input_name, input_name : IN STD_LOGIC;

bidir_name, bidir_name : INOUT STD_LOGIC;output_name, output_name : OUT STD_LOGIC);

END COMPONENT;

Where :package - - endarchitecture - is - - begin - endblock - - begin - endgenerate - - begin - end

Rules: For default configuration, the component

name must match the name of the corresponding entity to be used in its place, and generics and ports must also match in name, mode and type

Synthesis: A component without a corresponding

design entity is synthesized as a blackbox

In VHDL'93, components are not necessary. It is possible instead to directly instantiate an entity within an architecture.

Examplecomponent Countergeneric (N: INTEGER);port (Clock, Reset, Enable: in Std_logic;Q: buffer Std_logic_vector (N-1 downto 0));end component ;

Instantiation

A concurrent statement used to define the design hierarchy by making a copy of a lower level design entity within an architecture

In VHDL'93, a direct instantiation of an entity bypasses the component and configuration

Syntax:InstanceLabel: [component] ComponentName

[GenericMap] [PortMap];InstanceLabel: entity

EntityName[(ArchitectureName)][GenericMap] [PortMap];

InstanceLabel: configuration ConfigurationName[GenericMap] [PortMap];

Where:architecture begin - - endblock begin - - endgenerate begin - - end

Rules: An entity, architecture or configuration

must be compiled into a library before the corresponding instance can be compiled

However, an instance of a component can be compiled before the corresponding design entity has even been written

Example :G1: NAND2 generic map (1.2 ns)

port map (N1, N2, N3);G2: entity WORK.Counter(RTL)

port map (Clk, Rst, Count);

Generic Map

Used to define the values of generics Usually given in an Instance, but may also

appear in a configuration

Syntaxgeneric map ([Formal =>] Actual, ...)

Formal = {either} Name FunctionCallActual = Expression

Where :Label : ComponentName port map ();for - use - port map ()block generic (); ; port begin - end

Rules :The two forms of syntax (ordered list or explicitly named choices) can be mixed, but the ordered list must come before the named choices

A generic map does not end with a semicolon!

Example:architecture Structure of Ent is

component NAND2generic (TPLH, TPHL: TIME := 0 NS);port (A, B: in STD_LOGIC;

F : out STD_LOGIC);end component;

beginG1: NAND2 generic map (1.9 NS, 2.8 NS)

port map (N1, N2, N3);G2: NAND2 generic map (TPLH => 2 NS, TPHL => 3 NS)

port map (N4, N5, N6);end Structure;

Port Map

A port map is typically used to define the interconnection between instances in a structural description (or netlist)

A port map maps signals in an architecture to ports on an instance within that architecture

Port maps can also appear in a configuration or a block

Syntax:port map ([Formal =>] Actual, ...);

Formal = {either} Name FunctionCallActual = {either} Name FunctionCall open

Where:Label : ComponentName generic map () ;for - use - generic map () ;block - port () ; ; - begin - end

Rules: The two forms of syntax (ordered list or explicitly named

ports) can be mixed, but the ordered list must come before the named ports

Within an instance, the formals are ports on the component or entity being instanced, the actuals are signals visible in the architecture containing the instance

Within a configuration, the formals are ports on the entity, the actuals are ports on the component

If the actual is a conversion function, this is called implicitly as values are passed in

If the formal is a conversion function, this is called implicitly as values are passed out

Use the port names rather than order to improve readability and reduce the risk of making connection errors

Example:component COUNTER

port (CLK, RESET: in Std_logic;UpDown: in Std_logic := '0';-- default valueQ: out Std_logic_vector(3 downto 0));

end component;...-- Positional association...G1: COUNTER port map (Clk32MHz, RST, open, Count);-- Named association (order doesn't matter)...G2: COUNTER port map ( RESET => RST,CLK => Clk32MHz,Q(3) => Q2MHz,Q(2) => open, -- unconnectedQ(1 downto 0) => Cnt2,UpDown => open);

Top Level Entity and Lower Level Entity

TOP LEVEL ENTITY

Clk32MHz Q2MHz

Cnt2

RST

COUNT

COUNTER(LOWER LEVEL ENTITY)

CLK

RESET

QUpdown

TOP LEVEL ENTITY

Clk32MHz

Q2MHz

Cnt2

RST

COUNT

G1

CLK

RESET

Q

UpdownG2

CLK

RESET

Q(3)

Updown

Q(0)

CLK => Clk32MHzQ(3) => Q2MHz

UpDown => open

RESET => RST

A still simpler exampleentity ND4 is

port (in1,in2,in3,in4 : in std_logic ;z : out std_logic);

end ND4;architecture ND4_CI of ND4 iscomponent ND2

port (a , b : in std_logic;c : out std_logic);

end component ;signal temp1, temp2 : std_logic;beginU1 : ND2 port map (a => in1 , b => in2 , c => temp1);U2 : ND2 port map (a => in3 , b => in4 , c => temp2);U3 : ND2 port map (a => temp1 , b => temp2 , c => z);end ND4_CI ;

infersND4

U1

U3

U2

IN1

IN2

IN3

IN4

Z

a

a

b

b

a

b

c

c

c

c => temp1 for U1a => temp1 for U3

c => temp2 for U2b => temp2 for U3

Generate statement A concurrent statement used to create

regular structures or conditional structuresduring elaboration

Used to create multiple copies of components , processes or blocks

It provides a compact description of regular structures such as memories , registers and counters

Two flavours of generate statement are: for generate

Number of copies is determined by a discrete range

if generate Zero or one copy is made conditionally

Range must be a computable integer in any of the following forms: integer_expression to integer_expression integer_expression downto integer_expression Each integer_expression evaluates to an integer

Syntax :Label: for ParameterName in Range generate[Declarations...begin]ConcurrentStatements...

end generate [Label];

Label: if Condition generate[Declarations...begin]ConcurrentStatements...

end generate [Label];

Where:architecture begin - - endblock begin - - endgenerate begin - - end

Rules : The Range and Condition must both be

static, i.e. they cannot include signals The Label at the beginning of the generate

statement cannot be omitted

Synthesis: Synthesis is straightforward, but not all

synthesis tools support generate!

Example:architecture ABC of full_add4 is

component full_addport (PA , PB , PC : in std_logic ;

PCOUT , PSUM : out std_logic) ;end component ;

signal c: std_logic_vector(4 downto 0);begin

c(0)

infers

FA2

A(2) B(2)

C(2)

SUM(2)

FA3

A(3) B(3)

Cout

SUM(3)

FA0

A(0) B(0)

CinC(1)

SUM(0)

FA1

A(1) B(1)

SUM(1)

C(3)

architecture SHIFTER_ARCH of SHIFTER iscomponent DFF

port (D , CLK : in std_logic ;Q : out std_logic) ;

end component ;beginGK : for k in 0 to 3 generate

GK0 : IF k=0 generateDFILPFLOP : DFF port map (count , clock , Q(k));

end generate GK0 ;GK1_3 : if k > 0 generate

DFILPFLOP : DFF port map (Q(k-1), clock , Q(k));end generate GK1_3 ;

end generate GK ;end SHIFTER_ARCH ;

Another example

infers

DF1DF0 DF3DF2

CLOCK

COUNT

Q(0) Q(1) Q(2) Q(3)

Ways to describe a circuit!

Three types of descriptions possible with VHDL Structural Dataflow Behavioral

Structural Method At the structural level, which is the lowest level, you

have to first manually design the circuit. Use VHDL to specify the components and gates that

are needed by the circuit and how they are connected together by following your circuit exactly

Synthesizing a structural VHDL description of a circuit will produce a netlist that is exactly like your original circuit

The advantage of working at the structural level is that you have full control as to what components are used and how they are connected.

But you need to first come up with the circuit and so the full capabilities of the synthesizer are not utilized

Dataflow Method At the dataflow level, you use the built-in logical

functions of VHDL in signal assignment statements to describe a circuit, which again you have to first design manually

Boolean functions that describe a circuit can be easily converted to signal assignment statements using the built-in logical functions

The only drawback is that the built-in logical functions such as the AND and OR function only take two operands. This is like having only 2-input gates to work with !

All the statements use in the structural and dataflowlevel are executed concurrently

Behavioral Method Describing a circuit at the behavioral level is

most similar to writing a computer program You have all the standard high-level

programming constructs such as the FOR LOOP, WHILE LOOP, IF THEN ELSE, CASE, and variable assignments

The statements are enclosed in a process block and are executed sequentially

Example

BCD to 7- segment display decoder

a

b

c

d

e

fg

BCD to 7-segmentdisplay decoder

I3I2I1I0

segs(6) {seg 'a'}segs(5) {seg 'b'}segs(4) {seg 'c'}segs(3) {seg 'd'}segs(2) {seg 'e'}segs(1) {seg 'f'}segs(0) {seg 'g'}

Truth-table

Logic Equations

2 1 0

3 1 2 0'

'2 1 0

' ' ' ' '1 0 2 0 2 1 2 1 0

' ' '1 0 2 0

' ' ' '3 2 1 2 0 1 0

'3 2 1 1 0

( )

( )

( )

a I I I Ib I I Ic I I Id I I I I I I I I Ie I I I If I I I I I I Ig I I I I I

= + += += + += + + += += + + += + +

::

Logic gates

Structural VHDL descriptionENTITY myxnor2 IS PORT(i1, i2: IN BIT;o: OUT BIT);END myxnor2;ARCHITECTURE Dataflow OF myxnor2 ISBEGINo

ENTITY myand3 IS PORT(i1, i2, i3: IN BIT; o: OUT BIT);END myand3;ARCHITECTURE Dataflow OF myand3 ISBEGINo

ENTITY myor4 IS PORT(i1, i2, i3, i4: IN BIT; o: OUT BIT);END myor4;ARCHITECTURE Dataflow OF myor4 ISBEGINo

LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY bcd IS PORT(i0, i1, i2, i3: IN BIT;a, b, c, d, e, f, g: OUT BIT);END bcd;ARCHITECTURE Structural OF bcd ISCOMPONENT inv PORT (i: IN BIT ;o: OUT BIT);END COMPONENT;COMPONENT myand2 PORT(i1, i2: IN BIT;o: OUT BIT);END COMPONENT;COMPONENT myand3 PORT(i1, i2, i3: IN BIT;o: OUT BIT);END COMPONENT;COMPONENT myor2 PORT(i1, i2: IN BIT;o: OUT BIT);END COMPONENT;COMPONENT myor3 PORT(i1, i2, i3: IN BIT;o: OUT BIT);END COMPONENT;COMPONENT myor4 PORT(i1, i2, i3, i4: IN BIT;o: OUT BIT);END COMPONENT;COMPONENT myxnor2 PORT(i1, i2: IN BIT;o: OUT BIT);END COMPONENT;COMPONENT myxor2 PORT(i1, i2: IN BIT;o: OUT BIT);END COMPONENT;

SIGNAL j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z: BIT;BEGINU1: INV port map(i2,j);U2: INV port map(i1,k);U3: INV port map(i0,l);U4: myXNOR2 port map(i2, i0, z);U5: myOR3 port map(i3, i1, z, a);U6: myXNOR2 port map(i1, i0, y);U7: myOR2 port map(j, y, b);U8: myOR3 port map(i2, k, i0, c);U9: myAND2 port map(i1, l, x);U10: myAND2 port map(j, l, w);U11: myAND2 port map(j, i1, v);U12: myAND3 port map(i2, k, i0, t);U13: myOR4 port map(x, w, v, t, d);U14: myAND2 port map(i1, l, s);U15: myAND2 port map(j, l, r);U16: myOR2 port map(s, r, e);U17: myAND2 port map(i2, k, q);U18: myAND2 port map(i2, l, p);U19: myAND2 port map(k, l, o);U20: myOR4 port map(i3, q, p, o, f);U21: myXOR2 port map(i2, i1, n);U22: myAND2 port map(i1, l, m);U23: myOR3 port map(i3, n, m, g);END Structural;

Dataflow VHDL descriptionLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY bcd IS PORT (I: IN STD_LOGIC_VECTOR (3 DOWNTO 0);Segs: OUT std_logic_vector (1 TO 7));END bcd;ARCHITECTURE Dataflow OF bcd ISBEGINSegs(1)

Behavioral VHDL descriptionlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity BCD is

port( I : in STD_LOGIC_VECTOR(3 downto 0);segs : out STD_LOGIC_VECTOR(6 downto 0) );

end BCD;architecture Behavioral of BCD isbeginwith I selectSegs

Output

Equations for carry_generate(G) and carry_propagate(P) for ALU 74181

Carry Lookahead Logic

xi

yi

xi-1

x0

yi-1y0

c0

ci

hsisi

gi= xi . yipi=xi + yi

ci+1= gi + pi . ci

Assignment No 3

c1= g0 + p0 . c0

c2= g1 + p1 . g0 + p1.p0.c0

c3= g2 + p2 . g1 + p2.p1.g0+p2.p1.p0.c0

c4= g3 + p3 . g2 + p3.p2.g1+p3.p2.p1.g0+p3.p2.p1.p0.c0

Additional Information

G_L= (g3+p3.g2+p3.p2.g1+p3.p2.p1.g0)

P_L=(p3.p2.p1.p0)

Implement the Carry_Generate and Carry_Propagateoutputs also to complete the ALU assignment

Equations for implementation of G_L , P_L outputs

Sequential Statements

Next Class

generated doubt !

fulladder

GK.0.FA

fulladder

GK.3.FA

fulladder

GK.2.FA

fulladder

GK.1.FA

COUT[4]SUM[3:0][3:0]

CinB[3:0] [3:0]A[3:0] [3:0]

[0] PA[0] PB

PC[1]PCOUT[0]PSUM

[3] PA[3] PB[3] PC

[4]PCOUT[3]PSUM

[2] PA[2] PB[2] PC

[3]PCOUT[2]PSUM

[1] PA[1] PB[1] PC

[2]PCOUT[1]PSUM

fulladder

GK.3.FAfulladder

GK.0.FA

fulladder

GK.1.FA

fulladder

GK.2.FA

COUT[4]SUM[3:0][3:0]

CinB[3:0] [3:0]A[3:0] [3:0]

[3] PA[3] PB[3] PC

[4]PCOUT[3]PSUM

[0] PA[0] PB

PC[1]PCOUT[0]PSUM

[1] PA[1] PB[1] PC

[2]PCOUT[1]PSUM

[2] PA[2] PB[2] PC

[3]PCOUT[2]PSUM

GK : for k in 3 downto 0 generate GK : for k in 0 to 3 generate=

Sequential Statements


Sequential Statements VHDL code is inherently concurrent Sections of code that are executed

sequentially are : PROCESS FUNCTION PROCEDURE

One important aspect of sequential code is that it is not limited to sequential logic

We can build sequential circuits as well as combinational circuits

Sequential code is also called behavioral code Thus a PROCESS is a concurrent statement which

describes behaviour

Sequential statements are allowed only inside PROCESSES, FUNCTIONS, or PROCEDURES

Sequential statements are: IF WAIT CASE LOOP

VARIABLES are also restricted to be used in sequential code only

VARIABLE can never be global, so its value can not be passed out directly

SIGNALS and VARIABLES revisited !

VHDL has two ways of passing non-static values around: by means of a SIGNAL or by means of a VARIABLE

A SIGNAL can be declared in a PACKAGE, ENTITY or ARCHITECTURE (in its declarative part), while a VARIABLE can only be declared inside a piece of sequential code

SIGNAL is global while VARIABLE is local The value of a VARIABLE can never be passed out of

the PROCESS directly; if necessary, then it must be assigned to a SIGNAL

Update of VARIABLE is immediate whereas new value for SIGNAL is generally only guaranteed to be available after the conclusion of the present run of the PROCESS

Assignment operator for SIGNAL is

Process

A PROCESS is a sequential section of VHDL code

It is characterized by the presence of IF, WAIT, CASE, or LOOP, and by a sensitivity list (except when WAIT is used)

A PROCESS must be installed in the main code, and is executed every time a signal in the sensitivity list changes (or the condition related to WAIT is fulfilled)

Syntax

[label:] [postponed] PROCESS (sensitivity list)[VARIABLE name type [range] [:= initial_value;]]BEGIN(sequential code)END [postponed] PROCESS [label];

entity - begin - - end architecture - begin - - endblock - begin - - endgenerate - begin - - end

Where POSTPONEDis a reserved VHDL word

Rules A process must contain either a sensitivity

list or wait statements, but not both Every process executes once during

initialization, before simulation starts A postponed process is not executed until

the final simulation cycle of a particular simulation time, and thus sees the stable values of signals and variables

A process with neither a sensitivity list nor a wait will loop forever !

To construct a synchronous circuit, monitoring a signal (clock, for example) is necessary

A common way of detecting a signal change is by means of the EVENT attribute

For instance, if clk is a signal to be monitored, then clk EVENT returns TRUE when a change on clk occurs (rising or falling edge)

Using EVENT attribute

IF construct A sequential statement which executes one

branch from a set of branches dependent upon the conditions, which are tested in sequence

Syntax[Label:] if Condition thenSequentialStatements...[elsif Condition thenSequentialStatements...]... {any number of elsif parts}[elseSequentialStatements...]end if [Label];

Be careful about the spelling of elsif and end if

Synthesis Assignments within if statements generally

synthesize to multiplexers Incomplete assignments, where outputs remain

unchanged for certain input conditions, synthesize to transparent latches in unclockedprocesses, and to flip-flops in clockedprocesses

In some circumstances, nested if statements synthesize to multiple logic levels. This can be avoided by using a case statement instead

A set of elsif branches can be used to impart priority to the conditions tested first

To decode a value without giving priority to certain conditions, use a case statement instead

ExampleIF (x'0');

D Flip-Flop with asynchronous reset

A D-type flip-flop is the most basic building block in sequential logic circuits. In it, the output must copy the input at either the positive or negative transition of the clock signal (rising or falling edge)

If rst = 1, then the output must be q = 0 ,regardless of the status of clk. Otherwise, the output must copy the input (that is, q = d) at the positive edge of clk

LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY dff ISPORT (d, clk, rst: IN STD_LOGIC;q: OUT STD_LOGIC);END dff;ARCHITECTURE behavior OF dff ISBEGINPROCESS (clk, rst)BEGINIF (rst='1') THENq

Output

q

Rq

rst

clkd Q[0]D[0]

qRq

rst

clkd Q[0]D[0]

Changing the statementELSIF (clk'EVENT AND clk=0') THEN

One Digit counter example

Progressive 1-digit decimal counter (0 -> 9 ->0)

Single bit input (clk) and a 4-bit output (digit).

LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY counter ISPORT (clk : IN STD_LOGIC; digit : OUT INTEGER RANGE 0 TO 9);END counter;ARCHITECTURE counter OF counter ISBEGINcount: PROCESS (clk)VARIABLE temp : INTEGER RANGE 0 TO 10;BEGINIF (clk'EVENT AND clk='1') THENtemp := temp + 1;IF (temp=10) THEN temp := 0;END IF;END IF;digit

Output

In a counter like circuits always use comparison statements with constant valuesThis ensures simple comparator inference as against full comparator inference for comparison with unknown values

digit[3:0]

clk

[3][30][1]

[32]

[3][30][1]

[32] un2_temp[29:32] +

count.un1_temp =10) THEN temp := 0;

Extra Hardware

Sequential Statements cont..

Next Class

Sequential Statements II


Wait statement

The operation of WAIT is sometimes similar to that of IF

PROCESS cannot have a sensitivity list when WAIT is employed

Three flavours of WAIT statements are: WAIT UNTIL WAIT ON WAIT FOR

Syntax

WAIT UNTIL signal_condition; The WAIT UNTIL statement accepts only one signal,

thus being more appropriate for synchronous code than asynchronous

Since the PROCESS has no sensitivity list in this case, WAIT UNTIL must be the first statement in the PROCESS

The PROCESS will be executed every time the condition is met

Example ( 8-bit register )

PROCESS -- no sensitivity listBEGINWAIT UNTIL (clk'EVENT AND clk='1');IF (rst='1') THENop

Output and Inference

op[7:0]

op[7:0][7:0]inp[7:0] [7:0]rst

clk[7:0]Q[7:0]

[7:0] D[7:0]R

Output changes only with clk

Syntax

WAIT ON signal1 [, signal2, ... ];

The WAIT ON statement accepts multiplesignals

The PROCESS is put on hold until any of the signals listed changes

Example ( 8-bit register )

PROCESSBEGINWAIT ON clk, rst;IF (rst='1') THENop


op[7:0]

Rop[7:0][7:0]inp[7:0] [7:0]

rst

clk[7:0]Q[7:0]

[7:0] D[7:0]

Output changes with clk and rst

DFF revisited with WAIT!LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY dff ISPORT (d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC);END dff;ARCHITECTURE dff OF dff ISBEGINPROCESSBEGINWAIT ON rst, clk;IF (rst='1') THENq


q

Rq

rst

clkd Q[0]D[0]

Infers exactly the same hardware as the earlier design

As a homework problem repeat the one digit counter with WAIT statement

Syntax

WAIT FOR time;

WAIT FOR is intended for simulation only(waveform generation for test-benches)

Case statement CASE is another statement intended exclusively

for sequential code The CASE statement (sequential) is very similar

to WHEN (combinational) All permutations must be tested, so the keyword

OTHERS is often helpful Another important keyword is NULL (the

counterpart of UNAFFECTED), which should be used when no action is to take place

CASE allows multiple assignments for each test condition while WHEN allows only one

[Label:] case Expression iswhen Choices =>

SequentialStatements...when Choices =>

SequentialStatements...... {any number of when parts}end case [Label];

Syntax

Choices = Choice | Choice | ...Choice = {either}

ConstantExpressionRangeothers {the last branch}

Whereprocess begin - - endfunction begin - - endprocedure begin - - endif then - - elsif then - -else - - endcase - => - - when - => - -endloop--end

Rules The Expression must not be enclosed in

parenthesis The type of the Expression must be

enumeration, integer, physical, or a onedimensional array

Every case of the Expression must be covered once and only once by theChoices

Synthesis Assignments within case statements

generally synthesize to multiplexers Incomplete assignments (i.e. where

outputs remain unassigned for certain input conditions) in unclocked processes synthesize to transparent latches

Incomplete assignments in clocked processes synthesize to recirculation around registers

Examplecase ADDRESS iswhen 0 => -- Select a single valueA A

2 - digit counter with SSD output

COUNTER

a

b

c

d

e

fg

a

b

c

d

e

fg

DIGIT 1

7 BITS

CLK

RST

DIGIT 2

Progressive 2-digit decimal counter (0-> 99-> 0) , with external asynchronous reset plus binary-coded decimal (BCD) to seven-segment display (SSD) conversion

LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY counter IS

PORT (clk, rst : IN STD_LOGIC;digit1, digit2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));

END counter;ARCHITECTURE counter OF counter ISBEGIN

PROCESS (clk, rst)VARIABLE temp1: INTEGER RANGE 0 TO 10;VARIABLE temp2: INTEGER RANGE 0 TO 10;

BEGINIF (rst='1') THEN

temp1 := 0;temp2 := 0;

ELSIF (clk'EVENT AND clk='1') THENtemp1 := temp1 + 1;IF (temp1=10) THEN

temp1 := 0;temp2 := temp2 + 1;

IF (temp2=10) THENtemp2 := 0;

END IF;END IF;

END IF;

CASE temp1 ISWHEN 0 => digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 NULL;

END CASE;CASE temp2 IS

WHEN 0 => digit2 digit2 digit2 digit2 digit2 digit2 digit2 digit2 digit2 digit2 NULL;END CASE;

END PROCESS;END counter;

Output

Inference

DO NOT TRY TO WORK OUT HOW THIS CIRCUIT WORKS !!!

Test !!!

Next Class

Sequential Statements III


Loop statement LOOP is useful when a piece of code must

be instantiated several times Like IF, WAIT, and CASE, LOOP is

intended exclusively for sequential code, so it too can only be used inside a PROCESS, FUNCTION, or PROCEDURE.

There are several ways of using LOOP A loop is an infinite loop (and thus an

error) unless it contains an exit or wait statement

FOR / LOOP: The loop is repeated a fixed number of times

[label:] FOR identifier IN range LOOP(sequential statements)END LOOP [label];WHILE / LOOP: The loop is repeated until a condition no

longer holds

[label:] WHILE condition LOOP(sequential statements)END LOOP [label];

[label:] LOOP(SequentialStatements)END LOOP [label];

Syntax

EXIT: Used for ending the loop

[label:] EXIT [label] [WHEN condition];

NEXT: Used for skipping loop steps

[label:] NEXT [loop_label] [WHEN condition];

WAIT : Continue looping until..

FOR i IN 0 TO 5 LOOPx(i)

WHILE (i < 10) LOOPWAIT UNTIL clk'EVENT AND clk='1';(other statements)END LOOP;

In this example, LOOP will keep r

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