E.E. 451.3ENEL 489

VLSI/Integrated Circuit Design

VHDL USER GUIDE:

Comprehensive Example

Andrew R. Kostiuk,TRLabs

University of Regina108-2 Research DriveRegina, Saskatchewan

R.J. BoltonDepartment of Electrical Engineering

University of Saskatchewan57 Campus Drive

Saskatoon, SaskatchewanS7N 5A9

E.E. 451.3/ENEL 489 VHDL USER GUIDE: Comprehensive Example

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Introduction

The following example is intended to be a comprehensive example to introducethe novice Very High Speed Integrated Circuit Hardware Description Language (VHDL)designer to the structure of VHDL design. To do this an 8-bit serial to parallel converterwith parity will be designed.

All items in BOLD UPPERCASE in the listings to follow are either VHDLreserved keywords or user defined types.

Specification

Consider the example of a serial input bit stream (rxd) with a clock (clk). Theinput stream is to be formed into a byte (r) and a parity bit (pb) generated. The byteshould be output in parallel (r(0), r(1), r(2), .., r(7)). A flag (char_available) should beset when an entire character (i.e., the r byte) has been received and it should be resetwhen the byte and parity are read (or the reset signal is asserted).

From this description, we can already write the VHDL interface declarationwithout worrying yet about what is inside the entity. Lets call the entity “s_to_p_with_p”.

Listing 1. VHDL code of Entity (s_to_p_with_p).

--****************************************************-- Design of Serial to Parallel Circuit with Parity------------------------------------------------------

-------------------------------------------------------- Designed by: Top Level Designer-- Date: December 6, 1996------------------------------------------------------

--****************************************************-- Since we have a byte, lets declare a PACKAGE------------------------------------------------------

PACKAGE BUSES ISTYPE BYTE IS ARRAY (7 DOWNTO 0) OF BIT;

END BUSES;

--****************************************************-- Top Level Interface------------------------------------------------------

USE BUSES.ALL;

ENTITY s_to_p_with_p ISPORT (rxd, clk, reset : IN BIT ; r : OUT BYTE; pb, char_available : OUT BIT);

END;

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Design

Now what is inside? Well, we will need an eight bit shift register to do the serial-to-parallel conversion, call it “eight_shift”. A parity generator, call it “parity_gen”. A fourbit counter to count the number of bits clocked in and a common reset. Call the counter“counter” and we get a circuit like Figure 1.

parityparity_gen

d(0) d(1) d(2) d(3) d(4) d(5) d(6) d(7)

pb

input

clock

eight_shift

q(1) q(2) q(3) q(4) q(5) q(6) q(7)q(0)

clock counter

reset q2q1q0 q3

char_available

reset

rxd

clk

r8

Figure 1. Schematic Diagram of Entity (s_to_p_with_p).

Now we can write the VHDL architectural body declaration.

Listing 2. VHDL code - Architecture (s_to_p_with_p).

--****************************************************-- Architecture of s_to_p_with_p------------------------------------------------------

ARCHITECTURE spp_body OF s_to_p_with_p ISCOMPONENT eight_shift PORT(input, clock : IN BIT; q : OUT BYTE);END COMPONENT;COMPONENT parity_gen PORT(d : IN BYTE; parity : OUT BIT);END COMPONENT;COMPONENT counter PORT(reset, clock : IN BIT; q0, q1, q2, q3 : OUT BIT);END COMPONENT;

BEGINshift_reg: eight_shift PORT MAP(rxd, clk, r);parity: parity_gen PORT MAP(R, pb);count: counter PORT MAP(reset, clk, OPEN, OPEN, OPEN, char_available);END;

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The associated ports on the instances can be quickly identified by looking at theCOMPONENT declarations. Note that q0, q1, and q2 of instance “count” are leftunconnected.

Eight Bit Shift Register

Now lets do eight_shift (see Figure 2). Assume that a shift register (shift) existsin some standard cell library that is appropriate to the fabrication technology we plan touse. As an example of such a library, see Appendix A.

q(1) q(2) q(6) q(7)q(0)input

clock

qd

shift

ck

cb

qd

shift

ck

cb

qd

shift

ck

cb

qd

shift

ck

cb

qd

shift

ck

cb

phi

phibar

two

inphi

phase

. . .

. . .

. . .

Figure 2. Eight Bit Shift Register (eight_shift).

The VHDL code for the Eight Bit Shift Register is shown below.

Listing 3. VHDL code - Eight Bit Shift Register (eight_shift).

--******************************************************-- Eight Bit Shift Register--------------------------------------------------------

USE BUSES.ALL;

ENTITY eight_shift ISPORT(input, clock : IN BIT; q : OUT BYTE);

END eight_shift;

ARCHITECTURE eight_shift_body OF eight_shift ISCOMPONENT shift PORT(d, ck, cb : IN BIT; q : OUT BIT);END COMPONENT;COMPONENT twophase PORT(inphi : IN BIT; phi, phibar : OUT BIT);END COMPONENT;SIGNAL phi0, phi1 : BIT;

BEGINphase: twophase PORT MAP(clock, phi0, phi1);sslice: FOR i IN 0 TO 7 GENERATEslif: IF i = 0 GENERATEsh1: shift PORT MAP(input, phi0, phi1, q(i));

END GENERATE;slif1: IF i > 0 GENERATEsh2: shift PORT MAP(q(i-1), phi0, phi1, q(i));

END GENERATE;END GENERATE slice;

END;

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Parity Generator

A parity generator can be constructed as a network of xor gates as shown inFigure 3. Assume there is an xor gate called “xor2” in the previously mentionedstandard cell library (see Appendix A).

d(0)

d(1)

d(2)

d(3)

d(4)

d(5)

d(7)

parity

d(6)

xor2

xor2

xor2

xor2

xor2

xor2

xor2

Figure 3. Parity Generator (parity_gen).

The VHDL code for the Parity Generator is shown below.

Listing 4. VHDL code - Parity Generator (parity_gen)

--*****************************************************-- Parity Generator-------------------------------------------------------

USE BUSES.ALL;

ENTITY parity_gen ISPORT(d : IN BYTE; parity : OUT BIT);

END;ARCHITECTURE parity_body OF parity_gen IS

TYPE NIBBLE IS ARRAY (0 TO 3) OF BIT;TYPE DUAL IS ARRAY (0 TO 1) OF BIT;COMPONENT xor2 PORT(a, b : IN BIT; z, zb : OUT BIT);END COMPONENT;SIGNAL inner: NIBBLE;SIGNAL inner2: DUAL;

BEGINfj: FOR j IN 0 TO 3 GENERATEx2: xor2 PORT MAP(d(2*j), d(2*j+1), inner(j), OPEN);ij: IF j MOD 2 GENERATEx2m: xor2 PORT MAP(inner(j-1), inner(j), inner2(j/2), OPEN);

END GENERATE;END GENERATE;

xf: xor2 PORT MAP(inner2(0), inner2(1), parity, OPEN);END;

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Four Bit Ripple Counter

Finally the four bit counter. Assume that a resettable D-type flip-flop (rdff) existsin the standard cell library (see Appendix A). The rdff D-type flip-flop requires a twophase clock, as do most flip-flops implemented in the CMOS technologies used fordesign in E.E. 451.3. Luckily, a single phase to two phase (inverted phases) standardcell called “twophase” exists in the library (see Appendix A). If we keep it simple and doa ripple counter, we get Figure 4.

rdff

d

ck

q

qb

reset

cb

q1 q2 q3q0

reset

clockphi

phibar

inphi

twophase rdff

d

ck

q

qb

reset

cb

rdff

d

ck

q

qb

reset

cb

rdff

d

ck

q

qb

reset

cb

Figure 4. Four Bit Ripple Counter (counter).

The VHDL code for the Four Bit Ripple Counter is shown below.

Listing 5. VHDL code - Four Bit Ripple Counter (counter).

--***********************************************************-- Four Bit Ripple Counter

USE BUSES.ALL;

ENTITY counter ISPORT(reset, clock : IN BIT; q0, q1, q2, q3 : OUT BIT);

END;

ARCHITECTURE body_counter OF counter ISCOMPONENT rdff PORT(d, ck, cb, reset : IN BIT; q, qb : OUT BIT);END COMPONENT;COMPONENT twophase PORT(inphi : IN BIT; phi, phibar : OUT BIT);END COMPONENT;SIGNAL phi0, phi1 : BIT;SIGNAL i0, i1, i2, i3 : BIT;

BEGINphases: twophase PORT MAP(clock, phi0, phi1);slice_0: rdff PORT MAP(i0, phi0, phi1, reset, q0, i0);slice_1: rdff PORT MAP(i1, i0, q0, reset, q1, i1);slice_2: rdff PORT MAP(i2, i1, q1, reset, q2, i2);slice_3: rdff PORT MAP(i3, i2, q2, reset, q3, i3);END;

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Summary

Note that while the completed VHDL description may appear to be somewhatverbose it is basically self-documenting and, once written, easy to change.

Some things to note when writing VHDL code:

• case does not matter. Use UPPERCASE for reserved keywords

• if you plan on using buses, make a PACKAGE declaration

• use comments (a line starting with --) liberally

• make sure your spelling is correct

• don’t forget the semi-colons in the declarations

• don’t forget the semicolons, both in the declarations and the end of most lines

• port types must match (i.e., IN and OUT, etc.)

• unused signal must be connect to an OPEN

Please note that the example shown above may not be usable with the particularlibrary of standard cells that you are using. In this case changes may have to be madeto the VHDL code, most notably in the names of the lower-level leaf cells.

Good luck!

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Appendix A

NC3LIB Gates and Signal Names(standard cell library for Nortel CMOS3)

† Note 1: The tgate is a bi-directional device. It can be usedwith a as the input and b as the output, or with b as the inputand a as the output. In order for circuits using this device tocompile properly, both a and b must be declared as inputs.

Cell Name Inputs Outputs Poweramux a, b, s z vdd, gndand2 a, b z, zb vdd, gndand3 a, b ,c z, zb vdd, gndand4 a, b ,c, d z, zb vdd, gndand5 a, b ,c, d, e z, zb vdd, gndinverter a z vdd, gndldff a, b, ck, cb, ld, sh q vdd, gndmux a, b, sa, sb z vdd, gndnand2 a, b z vdd, gndnand3 a, b, c z vdd, gndnand4 a, b, c, d z vdd, gndnand5 a, b, c, d, e z vdd, gndnor2 a, b z vdd, gndnor3 a, b, c z vdd, gndnor4 a, b, c, d z vdd, gndor2 a, b z, zb vdd, gndor3 a, b, c z, zb vdd, gndor4 a, b, c, d z, zb vdd, gndrdff d, ck, cb, reset q, qb vdd, gndrdff2 d, ck, cb, rb q vdd, gndrsnandff r, s q, qb vdd, gndrsnorff r, s q, qb vdd, gndshift d, ck, cb q vdd, gndshiftqbar d, ck, cb q, qbar vdd, gndtgate ck, cb, a, b † See Note 1 vdd, gndtwophase inphi phi, phibar vdd, gndxor2 a, b z, zb vdd, gnd