Very Large Scale Integration (VLSI) Very... · 2019-03-04 · Dr. Ahmed H. Madian-VLSI 31 Design Rules A set of geometrical specifications that dictate the design of the layout masks

Dr. Ahmed H. Madian-VLSI 1

Very Large Scale Integration (VLSI)

Dr. Ahmed H. [email protected]

Lecture 1


Course outline

◼ Overview of VLSI

◼ Technologies for Micro- and Nanostructures

◼ Low-Voltage and power design

◼ Synchronous and Asynchronous Circuit Design

◼ Architectures for VLSI Applications

◼ Test and Measurement Techniques for VLSI Circuits


What is VLSI?

◼ VLSI stands for (Very Large Scale Integrated circuits)

◼ Craver Mead of Caltech pioneered the filed of VLSI in the 1970’s.

◼ Digital electronic integrated circuits could be viewed as a set of geometrical patterns on the surface of a silicon chip.

◼ Complexity could thus be dealt with using the concept of repeated patterns that were fitted together in structured manner.


VLSI History

•Jack Kilby, working at Texas Instruments, first dreamed up the idea of a monolithic “integrated circuit” in July 1959. By the end of the year, he had

constructed several examples, including the flip-flop shown in the patent drawing above. Components are connected by hand-soldered wires and isolated by “shaping” and pn diodes used as resistors.


VLSI History (cont.)

◼ 1961: TI and Fairchild introduced the first logic IC’s (cost

~$50 in quantity!). This is a dual flip-flop with 4 transistors.

◼ 1963: Densities and yields are improving. This circuit has

four flip flops.

In 1970, making good on its promise to its investors Intel starts selling a 1K bit RAM, the 1103.


VLSI History (cont.)

◼ Introduced in 1972, the 8008 had 3,500

transistors supporting a byte-wide data

path. Despite its limitations, the 8008

was the first microprocessor capable of

playing the role of computer CPU as

demonstrated on the cover of the July

‘74 issue of Radio-Electronics.


Today

◼ Many disciplines have contributed to the current VLSI designs:◼ solid-state physics◼ materials science◼ lithography and fab◼ device modeling◼ architecture◼ algorithms◼ CAD tools◼ circuit design & layout


Chip Complexity

Chip classification according to number of active elements and minimal feature size:


VLSI Chip Types

◼ Full custom

Every circuit is custom designed

◼ Application-specific integrated circuits (ASICS) Design is created using a standard CAD tools without the need to interact with the silicon structure

◼ Semi-custom

In between of full-custom and ASIC-type circuits. The majority of the chip is designed using a primitive predefined cells (standard cells) from library as building blocks.


Design hierarchy overview

System specifications

Abstract High-level modelVHDL, Verilog, HDL

Logic synthesis

Circuit design

physical design

Manufacturing

Finished VLSI chip

Top design level

bottom design level

Initial concept

System design and verification

Logic design and verification

CMOS design and verification

Silicon logic design and verification

Mass production, testing and packaging

Marketing


VLSI Design

System specifications

Abstract High-level modelVHDL, Verilog, HDL

Logic synthesis

Circuit design

physical design

Manufacturing

Finished VLSI chip

Top design level

bottom design level

Initial concept

System design and verification

Logic design and verification

CMOS design and verification

Silicon logic design and verification

Mass production, testing and packaging

Marketing


Physical design

◼ CMOS ICs are electronic switching networks that are created on small area of silicon wafer using complex set of physical and chemical processes.

◼ A primary task for VLSI designer is to translate circuit schematics into silicon form (this process is called physical design)


Design Examples VLSI

◼ Draw the CMOS realization and the layout of logic function

◼ Colors of layers

polysilicon (gates) : Red

Doped n+/p+ (active) : Green

N-Well : Yellow

Metal 1 : BLUE

Metal 2 : Grey

Contacts : Black X’s

cbaf .+=


CMOS RealizationVDD

a

b

c

a

b c

f


Logic function Layout

PFET

NFET

N-Well

P+

N+

VDD

a

b

c

a

b c

f



PFET

NFET

N-Well VDD

XX X

bc a

VDD

a

b

c

a

b c

f



PFET

NFET

N-Well VDD

XX X

X X

GND

X

X

f

abc

VDD

a

b

c

a

b c

f


Layout Rules

◼ Layout rules are the common language between design and process engineers

◼ conservative rules absorb process disturbances and variations◼ layout rules must be respected by the designer◼ layout rules reflect the limits of a process, they describe:

◼ minimal distance, overlap◼ minimal width (e.x. channel length, λ)

◼ layout readability is improved using colors:◼ metal blue◼ polysilicium red◼ n-diffusion green◼ p-diffusion yellow◼ n-well brown◼ contact, via black


Layout


Stick Diagram

◼ stick diagrams are technology independent

◼ no layout rules need to be known

◼ mask layout may be generated automatically


Digital Layout: horizontal or vertical gates?

◼ Vertical gates◼ Good for circuits where fets

sizes are similar and each gate has limited fanout. Best choice for multiple input static gates and for datapaths.

◼ Horizontal gates

◼ Good for circuits where long and short fets are needed or where nodes must control many fets. Often used in multiple-output complex gates (e.g, sum/carry circuits).


Eliminating Gaps


Complex CMOS Gates compact layout.

◼ Euler Rule:◼ Generate an n-graph by replacing the nfet block

with vertices for nodes and edges for fets◼ Generate a dual p-graph◼ Find a sequence containing all edges in the n-

graph. This sequence is called Euler n-path.◼ Generate an Euler p-path with the same labeling

as the Euler n-path. If not possible start again.◼ The labeling sequence of the 2 Euler paths are the

gate sequence of the single row nfet/pfet CMOS gate.


◼ Draw the most compact layout for the following logic function using Euler’s rule.

F= A.(B+C)

Example


Solution

VDD

A

A

B

C

C B

N1

F

N2

GND

F

N2

GND

N1

FVDD

A

BC

A → B → C


Layout of Example

A → B → C

A B C


Design Rules

◼ Why we need design rules?◼ We can specify the design rules using some

convenient units, e.g., microns but what happens if we want to manufacture the chip using different manufacturers?◼ use an abstract unit, the lambda (), and scale the design

to the appropriate actual dimensions when the chip is to be manufactured.

◼ Each piece of fabrication equipment used in the IC manufacturing process has limited accuracy.

◼ So, we need rules to ensure that the inaccuracy in the fabrication will not result in malfunction IC.

Lambda Rule

◼ Design rules based on single parameter, λ

◼ Simple for the designer

◼ Wide acceptance

◼ Provide feature size independent way of setting out mask

◼ If design rules are obeyed, masks will produce working circuits

◼ Minimum feature size is defined as 2 λ

◼ Used to preserve topological features on a chip

◼ Prevents shorting, opens, contacts from slipping out of area to be contacted



Lambda-based Rules

◼ One lambda (λ)= one half of the “minimum” mask dimension, typically the length of a transistor channel. This can be used to derive design rules and to estimate minimum dimensions of a junction area and perimeter before a transistor has to be laid out.


Lambda-based Rules, why?

◼ probably okay for retargeting between “similar” processes, e.g., when later process is a simple “shrink” of the earlier process. Some 0.35μm processes are shrinks of an earlier 0.5μm process. Can be useful for “fabless” semiconductor companies.

◼ most industrial designs use micron rules to get the extra space efficiency. Cost of retargeting by hand is acceptable for a successful product, but usually it’s time for a redesign anyway.


Design Rules

◼ A set of geometrical specifications that dictate the design of the layout masks.

◼ It provides numerical values for minimum dimensions, line spacing, and other geometrical quantities that are derived from the limits of a specific processing line.

◼ This rules must be followed to ensure functional structures on the fabricated chip.

Poly (gate)

Poly (gate)

Sp-p

wp

wp

Wp = min. width of a polysilicon lineSp-p = min. poly-to-poly spacing


Design Rules

◼ Classified into four main types

◼ Min. width to avoid breaks

◼ Min. spacing to avoid shorts

◼ Min. surround

◼ Min. extension

N+

oxideoxideActive

contact

cut

P-substrate

Sa-ac

Poly (gate)

Poly (gate)

Sp-p

wp

wp

N+

oxideoxide

P-substrate


Design Rules

◼ Min. extension to ensure complete overlaps

dpo

Drain-source

short


Design Rules (cont.)

◼ Most foundry allows submission of designs using simpler set of design rules that can be easily scaled to different processes.

◼ These are called “lambda design rules” that has units of µm.

◼ All distance and widths and spacing are written as value = m, where m is scaling multiplier.

for ex.: w =3 , s = 4 If the factory will use technology =0.15 µm

w =0.45 µm, s = 0.6 µm


Design Rules

◼ The masking sequence was established as:◼ P-type substrate

◼ nWell

◼ Active

◼ Poly

◼ pSelect

◼ nSelect

◼ Active contact

◼ Poly contact

◼ Metal1

◼ Via

◼ Metal2

◼ Overglass


DR for N-Wells

◼ Required for pFET

◼ Snw-nw

◼ Wnw-nw

P-substrate

N-Well N-Well

Snw-nw

wnw-nw wnw-nw


DR for Active Areas

◼ Silicon devices are built on active areas of the substrate◼ Wa = min width of active feature

◼ Sa-a = min. edge-to-edge spacing of active mask polygon

Silicon substrate

FOXActive Active

Sa-a

Wa


DR for Doped silicon (n+)

◼ Wa = min width of an active area

◼ sa-n = min. active-to-nSelect spacing

Silicon substrate

FOXActive Active

N+ N+

wa

Sa-n

Sa-n


Silicon substrate

N-well

DR for Doped silicon (P+)

◼ Wa = min width of an active area

◼ sa-p = min. active-to-nSelect spacing

◼ Sa-nw = min. p+ to nWell spacing

FOXActive

wa

Sa-n

Sa-n

P+

P SelectSp-nw

Sp-nw Active

P Select


MOSFETs◼ MOSFET structure exists every time a poly gate line completely

crosses an n+ or p+ region

◼ DRs for poly features are

◼ Wp = min. poly width of a poly line

◼ dpo = min. extension of poly beyond Active

P substrate

N+ N+

Poly L

N+ N+

wp

N+

Sp-p

dpo


DR for Active contact

◼ Active contact is a cut in the oxide that allows the first layer of metal to contact as active n+ or p+ region.

◼ Sa-ac = min. spacing between active and active contact

◼ dac,v = vertical size of the contact

◼ dac,h = horizontal size of the contact

P-substrate

N+

N-well

P+

Active contact

dac,h

dac,v

Sa-ac


DR for Metal1

◼ Metal1 is applied to the wafer after oxide. It is used as interconnect for signals and also for power supply distribution.

◼ Wm1 = min. width of Metal1 line

◼ Sm1-ac = min. spacing from Metal1 to Active Contact

P-substrate

N+

Metal 1

Sm1-ac

wm1


DR Vias and higher level Metals

◼ Vias is a cut in the oxide layers to contact between two metals.

P-substrate

N+

Metal 1

Via

Metal2

Via

metal1

metal2

dv Sv-m2

Sv-m1

Sm2-m2

wm2

Layout Design Rules summary

Dr. Ahmed H. Madian-VLSI

Layout Design Rules (cont.)

◼ Transistor dimensions are in W/L ratio

◼ NFETs are usually twice the width

◼ PFETs are usually twice the width of NFETs

◼ Holes move more slowly than electrons (must be wider to deliver same current)

Dr. Ahmed H. Madian-VLSI

Layout example


3-input NAND

VLSI layout library


Layout


It’s required to draw the layout of:

◼ Inverter

◼ 4 input NAND gate

◼ 4 input NOR gate

◼ 3 input XOR gate

according to the Design rules given in the lecture due date next lecture.

(use layout tool submission will be soft copy and hard copy)

1st assignment

Documents

Very Large Scale Integration (VLSI) Very... · 2019-03-04 · Dr. Ahmed H. Madian-VLSI 31 Design Rules A set of geometrical specifications that dictate the design of the layout masks