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Gate level/ Structural
Modeling
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Experiment 1:
Verilog Code for basic Logic Gates
Program for 3 input and gate
module and3(y,a,b,c);output y;input a,b,c;and (y,a,b,c);
endmodule
Program for 4 input or gatemodule or4(y,a,b,c,d);
output y;input a,b,c,d;or (y,a,b,c,d);
endmodule
Program for inverter
module inv(y,a);
output y;input a;not (y,a);
endmodule
Exercise:
Write Verilog Modules and simulate the following gates
1. 4 Input NAND Gate2. 3 Input NOR Gate3. 2 Input XOR Gate4. 2
Input XOR using minimum number of 2 input NAND gates.
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Experiment 3: Arithmetic Units (Adders, Subtractors)
Program for half adder
module ha(s,c,a,b);output s,c;input a,b;xor (s,a,b);and
(c,a,b);
endmodule
Program for full adder using two half adders
module fa(s,cout,a,b,cin);output s,cout;input a,b,cin;wire
l1,l2,l3;ha g0(l1,l2,a,b);ha g1(s,l3,l1,cin);or g2(cout,l2,l3);
endmodule
Program for 4 bit adder using full adders
module fa4(s,cout,a,b,cin);output [3:0]s;input [3:0]a,b;output
cout;input cin;wire l0,l1,l2;
fa g0(s[0],l0,a[0],b[0],cin);
fa g1(s[1],l1,a[1],b[1],l0);fa g2(s[2],l2,a[2],b[2],l1);fa
g3(s[3],cout,a[3],b[3],l2);
endmodule
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Stimulus block for half adder
module test_ha;reg t_a,t_b; //test inputs should always be
regwire t_s,t_c; // test outputs should always be wireinitial
begint_a=1'b0; t_b=1'b0;
#5 t_a=1'b0; t_b=1'b1;#5 t_a=1'b1; t_b=1'b0;#5 t_a=1'b1;
t_b=1'b1;end
ha testha(t_s,t_c,t_a,t_b);initial
$monitor($time,"\t a=%b \t b=%b \t sum=%b \t carry
=%b",t_a,t_b,t_s,t_c);endmodule
Stimulus block for full adder
module test_fa;reg t_a,t_b,t_cin; //test inputs should always be
regwire t_s,t_cout; // test outputs should always be wire
initialbegin
t_a=1'b0; t_b=1'b0;t_cin=1'b0;#5 t_a=1'b0;
t_b=1'b0;t_cin=1'b1;#5 t_a=1'b0; t_b=1'b1;t_cin=1'b0;#5 t_a=1'b0;
t_b=1'b1;t_cin=1'b1;#5 t_a=1'b1; t_b=1'b0;t_cin=1'b0;#5 t_a=1'b1;
t_b=1'b0;t_cin=1'b1;#5 t_a=1'b1; t_b=1'b1;t_cin=1'b0;
#5 t_a=1'b1; t_b=1'b1;t_cin=1'b1;end
fa testfa(t_s,t_cout,t_a,t_b,t_cin);initial$monitor($time,"\t
a=%b \t b=%b \t cin=%b \t sum=%b \t carry
= %b",t_a,t_b,t_cin,t_s,t_cout);endmodule
