ICA LAB MANUAL - vardhamaneee2k12.files.wordpress.com€¦ · Web viewIC Applications lab Objectives: ... Immense knowledge of Verilog coding language will be obtained to implement

IC Applications lab Objectives:

1. To provide the hands on practical experience on principles of both linear and digital integrated circuits analysis and design knowledge which are required in analog IC design industry for designing various projects and for research.

2. To introduce the practical knowledge of the basic building blocks and their Pinout and usage of linear integrated circuits.

3. To design and study the characteristics, linear and non-linear applications of OP-AMPs and the practical usage in the real world.

4. To analyze and design various types of filter circuits using OP-AMPs and obtain their frequency response. Also emphasize the design of practical filters for a host of applications in the field of communications.

5. To study the internal functional blocks and to implement the applications of special ICs like IC 555 timers, PLL circuits, VCO etc.

6. Immense knowledge of Verilog coding language will be obtained to implement almost all digital logics.

7. To study the ICs and implement them practically with the help of Verilog language on cadence tool for various digital logic families and their characteristics, combinational circuits: encoder, multiplexer, digital comparator systems.

8. To study the ICs and implement them practically with the help of Verilog language on cadence tool for various digital logic families and their characteristics, sequential circuits: registers, counters. Also memories: ROM,RAM

IC APPLICATIONS LAB

PART - B

LINEAR ICS: (Hardware Verification)

1. Measurement of IC741 op-amp parameters.

2. Basic applications of IC741 op-amp.

3. Integrator and differentiator using IC741 op-amp.

4. Precision rectifiers using IC741 op-amp.

5. Active Low Pass & High Pass Butterworth filters (1st & 2nd Order).

6. RC Phase Shift and Wien Bridge Oscillators using IC 741 Op-Amp

7. IC 555 timer in Astable and Monostable operation.

8. Schmitt trigger circuits using IC 741 op-amp & IC 555 timer.

9. Operation of phase locked loop using IC565.

10. Voltage regulator IC 723, three terminal voltage regulators- 7805, 7809, 7912.

PART-A EXPERIMENT NO: 1

MEASUREMENT OF IC741 OP-AMP PARAMETERS

PRELAB:

1. Pinout of IC 741C with supply voltage rejection ratio.2. Immense knowledge of Op-Amp’s AC and DC characteristics.

OBJECTIVE:

1. To study the pin configurations, specifications & functioning of different integrated circuits used in the practical applications.

2. To measure the Op-Amp parameters and compare them with ideal characteristics.

DESIGN CONSTRAINT:

Design an Op-Amp with a supply voltage of +12V and -12V for studying its parameters.

APPARATUS REQUIRED:

1. IC µA 741 OP-Amp.2. Cathode Ray Oscilloscope.3. Regulated Power Supply (Dual Channel).4. Connecting Wires.

PINOUT AND CIRCUIT DIAGRAM:

IC µA741 OP-AMP

Figure.1

Specifications

1. Supply voltage: a. µA 741A, µA 741, µA 741E ---------------- ±22Vb. µA 741C ---------------- ±18 V

2. Internal power dissipationa. DIP package ----------------- 310 mw.

3. Differential input voltage ---------------- ±30 V.4. Operating temperature range

a. Military (µA 741A, µA 741) ---------------- -550 to +1250 C.b. Commercial (µA 741E, µA 741C) --------------- 00 C to +700 C.

5. Input offset voltage ---------------- 1.0 mV.6. Input Bias current ---------------- 80 nA.7. PSSR ---------------- 30µV/V.8. Input resistance ----------------- 2MΩ.9. CMMR ------------------ 90dB.10. Output resistance ------------------ 75Ω.11. Bandwidth ------------------ 1.0 MHz.12. Slew rate ------------------ 0.5 V/µ sec.

a) Input bias current and input offset current

Figure.2

b) Input offset voltage

Figure.3

c) Slew rate and Bandwidth

Figure.4d) Input and output voltage ranges

Figure.5

THEORY:

An op-amp is a high gain, direct coupled differential linear amplifier choose response characteristics are externally controlled by negative feedback from the output to input, op-amp has very high input impedance, typically a few mega ohms and low output impedance, less than 100Ω.

Op-amps can perform mathematical operations like summation integration, differentiation, logarithm, anti-logarithm, etc., and hence the name operational amplifier op-amps are also used as video and audio amplifiers, oscillators and so on, in communication electronics, in instrumentation and control, in medical electronics, etc.

The ideal op-amp

The ideal behaviour of an op-amp implies that

1. The output resistance is zero.2. The input resistance seen between the two input terminals (called the differential

inputresistance) is infinity.3. The input resistances seen between each input terminal and the ground (called the

commonmode input resistance) are infinite.4. op-amp has a zero voltage offsetie., for V1 = V2 = 0, output voltage VO = 0.5. Common mode gain ACis zero.6. Differential mode gain, Adis infinity.7. Common Mode Rejection Ratio (CMRR) is infinity.8. Bandwidth is infinite i.e., Adis real and constant.9. Slew rate is infinite.

Since VO = Ad (V1 – V2) and Ad = ∞,V1-V2 = VO/Ad = 0 i.e., V1 = V2

The above condition implies that the inverting and non-inverting terminals are at the same potential because of the very high (infinite) gain property. This condition along with the condition i1 = i2 = 0 are the keys to the simplified analysis of the op-amp circuits.

The above condition implies that the inverting and non-inverting terminals are at the same potential because of the very high (infinite) gain property. This condition along with the condition i1 = i2 = 0 are the keys to the simplified analysis of the op-amp circuits.

Op-Amp characteristics

An ideal op-amp draws no current from the source and its response is also independent of temperature. However, a real op-amp does not work this way. Current is taken from the source into op-amp inputs. Also the two inputs respond differently to current and voltage due to mismatch in transistors. A real op-amp also shifts its operation with temperature. These non-ideal characteristics are:

1. Input bias current

2. Input offset current

3. Input offset voltage

4. Thermal drift

5. Slew rate

6. Input and output voltage ranges

Input bias current

The op-amp’s input is a differential amplifier, which may be made of BJT or FET. In either case the input transistors must be biased into this linear region by supplying currents into the bases. In an ideal op-amp, no current is drawn from the input terminals. However, practically, input terminals conduct a small value of dc current to bias the input transistors when base currents flow through external resistances, they produce a small differential input voltage or unbalance; thisrepresents a false input signal. When amplified, this small input unbalance produces an offset in the output voltage.The input bias current shown on data sheets is the average value of base currents entering into the terminals of an op-amp.

For 741, the bias current is 500nA or less. The smaller the input bias current, the smaller will be the offset at the output voltage.

Input offset current

The input offset current is the difference between the two input currents driven from a common source

It tells you how much larger one current is than the other. Bias current compensation will work if both bias currents IB+ and IB- are equal. So, the smaller the input offset current the better the OP amp. The 741 op-amps have input offset current of 20nA.

Input offset voltage

Ideally, the output voltage should be zero when the voltage between the inverting and non-inverting inputs is zero. In reality, the output voltage may not be zero with zero input voltage. This is due to un-avoidable imbalances, mismatches, tolerances, and so on inside the op-amp. In order to make the output voltage zero, we have to apply a small voltage at the input terminals to make output voltage zero. This voltage is called input offset voltage .i.e., input offset voltage is the voltage required to be applied at the input

for making output voltage to zero volts. The 741 op-amp has input offset voltage of 5mV under no signal conditions. Therefore, we may have to apply a differential input of 5mV, to produce an output voltage of exactly zero.

Thermal drift

Bias current, offset current and offset voltage change with temperature. A circuit carefully mulled at 25oC may not remain so when the temperature rises to 35oC. This is called drift often, offset current drift is expressed in n A/oC and offset voltage drift in mV/oC.These indicate the change is offset for each degree Celsius change in temperature. There are very few techniques that can be used to minimize the effect of drift.

Slew rate

Among all specifications affecting the ac operation of the op-amp, slew rate is the most important because it places a severe limit on a large signals operation. Slew rateis defined as themaximum rate at which the output voltage can change. The 741 op-amp has a typical slew rate of0.5 volts per microsecond (V/µs). This is the ultimate speed of a typical 741 its output voltage can change no faster than 0.5V/µs. If we drive a 741 with large step input, it takes 20µs (0.5 V/µs*10V) for the output voltage to change from 0 to 10V.

Band width

Slew rate distortion of a sine wave starts at a point where the initial slope of the sine wave equals the slew rate of the op-amp. The maximum frequency at which the op-amp can be operated without distortion is

where SR=slew rate of op-amp, VP= peak voltage of output sine wave. As an example, if the output sine wave has a peak voltage of 10V and the op-amp slew rate is 0.5 V/µs, the maximum frequency for large signal operation is

Frequency ƒmax is called bandwidth of op-amp. The 741 op-amp has a bandwidth of approximately 8 KHz. This means the undistorted band width for large signal operation is 8 KHz.

Input and output voltage ranges

Maximum positive and negative input voltage applied to the op-amp for undistorted output gives the input voltage range. Maximum positive and negative undistorted output voltage of the op-amp gives the output voltage range.

OP Amp applications1. Signal conditioners a. Linear – eg. Adder, subtractor, differentiator, integrator, V-I converter, etc. b. Non-Linear – eg., log amplifier, anti-log amplifier, multiplier, divider, etc.

2. Signal Processors a. Linear – eg., voltage follower, instrumentation amplifier, etc. b. Non-Linear – eg., log amplifier, anti-log amplifier, multiplier, divider, etc.

Note: Use op-amp dc power supply voltages ±15V wherever not specified

DESIGN PROCEDURE:

1. Connect the IC 741 with supply voltages on a bread board.2. Connect the CRO as per the requirement for voltage and for current measurement.3. Measure the parameters of Op-Amp and compare them with ideal one.

1. Input bias current and input offset current

a. Connect the circuit of figure mentioned above for Input bias current and input offset current

b. Using a DMM, measure the dc voltage at the (-) terminal & record the values c. By ohm’s law, calculate the input currents; IB+ and IB-. Average these values to

find out the input Bias current. Also, find the difference between these two currents to know the input offset current. Record these values in Table 1-2-1.

DC voltage atDC voltage at Input bias

the non- Input offset

the invertingV

+

V

−current

Inverting I+

= I−= current

TerminalB

220KB

220K+ −

Terminal I B =(IB+IB )

IOS = |IB+ - IB

-|-2

V+V

Table 1-2-

1

2. Input offset voltage

a. Connect the circuit of Figure mentioned above for Input offset voltageb. Measure the DC output voltage at pin 6 using multimeter and record the result

in Table c. Calculate the input offset voltage using the formula Vi = Vout / 1000and record

the value in table

Vout Vin = Vout/1000

3. Slew rate and bandwidth

a. Connect the circuit of Figure mentioned above for Slew rate and bandwidthb. Using an AFO, provide a 1V peak to peak square wave with a frequency of 25

KHz.

c. With an oscilloscope, observe the output of OPAMP. Adjust the oscilloscope timing the get a couple of cycles.

d. Measure the voltage change ∆V and time change ∆T of the output waveform. Record the results in Table 1-2-3.

e. Calculate the slew rate using the formula

SR = ∆V / ∆T

f. Using the circuit of figure 3, set the AFO at 1KHz. Adjust the signal level to get 20V peak – to – peak (20 VPP) out of the op-amp.

g. Increase the frequency and watch the waveform somewhere above 10 KHz, slew rate distortion will become evident. That maximum frequency ƒ max at which the op-amp can be operated is called bandwidth of an op-amp record the value in Table 1-2-3

∆V ∆T SR = ∆V/∆T BW

4. Input and output voltage ranges

a. Assemble the voltage follower circuit as shown in Figure 1-2-10 with R1 = R2 = 100 kΩ. Use op-amp dc power supply voltages of ±9 V

b. Apply ±5 V, 100 Hz sinusoidal input, Vs. Observe on a CRO the voltages at the non-inverting input and output pins simultaneously. Increase the signal amplitude until distortion is observed at the peak value of the output. Measure the positive and negative input voltage peak values. This gives the op-amp input voltage range.

c. Change the circuit of Figure 1-2-10 to an inverting amplifier. Connect R1 between the source and inverting input. Ground the non-inverting input. Choose R1 = 10 kΩ, R2 = 100 kΩ. Repeat observations of step 2 starting with ±0.5 V, 100 Hz sinusoidal input. Measure the positive and negative output voltage peak values. This gives the op-amp output voltage range.

RESULT:

The pin configuration, specifications & functioning of different integrated circuits used in the practical applications have been studied.

REVIEW QUESTIONS:

1. Determine the output voltage of an op-amp for the input voltages of V i1=150µV and Vi2=140µV. The amplifier has a differential gain of Ad=4000 and the value of CMRR is 100.

2. Calculate the output voltage of an inverting amplifier for values of VS=1V, Rf=500K and R1=100K.

3. Calculate the output voltage of a non-inverting amplifier for values of VS=1V, Rf=500K and R1=100K.

4. Calculate the output offset voltage of the circuit in Fig (a). The op-amp spec lists VIO=1.2mV.

5. Calculate the offset voltage for the circuit in fig (a) for op-amp spec listing IIO=100nA.

6. Calculate the total offset voltage for the circuit of fig (a) for an op-amp with specified values of VIO=1.2mV and IIO=100nA.

7. Calculate the input bias current at each input of an op-amp and input offset current having specified values of IIO=5nA and IIB=30nA.

8. For an op-amp having a slew rate of 2 V/µs, what is the maximum closed loop voltage gain that can be used when the input signal varies by 0.5V in 20µs.

9. How long does it take the output voltage of an op-amp to go from -10V to +10V if the slew rate is 0.5V/µs.

10. Determine the input bias current and input offset current, given that the input currents of an op-amp are 8.3µA and 7.9µA.

11. Verify the parameters of other Op-Amp IC LM 311N voltage comparator

Specifications

1. Total supply voltage ------------ 36 V

2. Input Voltage ------------ ±15V

3. Power dissipation ------------ 500mW

4. Operating temperature ------------ 00 C to 700C

5. Input offset voltage ------------- 2.0 mV

6. Input Bias current ------------ 100nA

7. Voltage gain ------------- 200V/mV

OUTCOMES:

1. After completion of this experiment the student will have a complete idea of an Op-Amp and its parameters.

2. Students will know about the connectivity and biasing of an IC (IC 741) and also the supply and they also learn theprocedure for measurement.

3. They will know about the difference in ideal values and practical values.


BASIC OP-AMP APPLICATIONS(Adder, Subtractor, Comparator using IC 741 Op-Amp)

PRELAB:

1. Immense knowledge of op-amp in open loop and closed loop configurations.2. Pinout of IC 741C with supply voltage rejection ratio.

OBJECTIVE:

To design and implement basic op-amp applications using IC 741 Operational amplifier such as

1. Adder 2. Subtractor3. Comparator

DESIGN CONSTRAINTS:

1. Design a 3-input ADDER circuit with input voltages of Va=1v,Vb=2v,Vc=3v using IC 741.Consider Op-amp as ideal.

2. Design a SUBSTRACTOR circuit with input voltages of Va=4v and Vb=2v using IC 741. Consider Op-amp as ideal.

3. Design an Inverting and Non-Inverting COMPARATOR with peat-to-peak input voltage of 4v and reference voltage (Vref) of (plus /minus) 1v and output saturation voltage(Vsat) at (plus/minus) 2v using IC 741.

APPARATUS REQUIRED:

1. Component Development System Board with in-built power supply and Bread Board.2. Function Generator.3. Cathode Ray Oscilloscope.4. Regulated Power Supply (Dual Channel).5. Connecting Wires.

COMPONENTS REQUIRED:

1. IC741 :1No2. Resistor ------ 1KΩ :4No

10KΩ :3No100Ω :1No

CIRCUIT DIAGRAMS:

a) ADDER

wFigure.1

b) SUBTRACTOR

Figure.2

c) COMPARATOR

i. Non-Inverting Comparator

Figure.3

ii. Inverting Comparator

Figure.4

DESIGN PROCEDURE:

Adder:

A typical summing amplifier (Inverting Adder) with three inputs Va ,Vb&Vc applied at the inverting terminal of IC741 is shown in fig(1). The following analysis is carried out assuming that the Op-Amp is an ideal one, that is AOL = ∞, Ri = ∞ & R0=0; since the input bias current is assumed to be zero, there is no voltage drop across the resistor R comp and hence the non-inverting input terminal is at ground potential.

The voltage at node ‘A’ is zero as the non- inverting input terminal is grounded. The nodal equation by KCL at node ‘a’ is given as

Case 1: Ra=Rb=Rc=Rf

V0 = - (Va + Vb+ Vc)

Case 2: Ra=Rb=Rc=3Rf

V0 = - (Va + Vb+ Vc)/3

Subtractor

A typical subtractor with two inputs Va&Vbapplied at the non-inverting terminal & Inverting terminal of IC741 respectively is shown in fig(2). The following analysis is carried out assuming that the Op-Amp is an ideal one, that is AOL = ∞, Ri = ∞ & R0=0;

Let Ra = Rb= Rf = R,

Vo= Va- Vb

Comparator

A Comparator is a circuit that makes a comparison between two signals applied on to inverting and non-inverting input terminals. One signal is the input signal and the other is a reference signal with which the input is compared. Based on the application of input signal to inverting or non-inverting the comparators are of two types

1. Non-Inverting Comparator and 2. Inverting Comparator

As shown in the figure 3 and 4 respectively and their outputs are defined as +Vsat or –Vsat

depending on the relation between Vin and Vref.

PROCEDURE:

Adder

1. Connect the Adder circuit as shown in fig.1 with Ra = Rb = Rc = Rf = 1KΩ, RL =100KΩ and R = 250Ω on the CDS board.

2. Switch ‘ON’ the power supply and apply +15V to pin no.7 and -15V to pin no.4 of the IC741.

3. Apply the input voltages from the regulated supplies to the corresponding inputs at the inverting input terminal of IC741 (pin no.2).

4. Connect the Digital Multimeter at the Output terminals (pin no.6), and note down the output voltage and verify with theoretical values.

5. Repeat the above steps for different input voltages.

Subtractor

1. Connect the Subtractor circuit as shown in fig.2 with Ra = Rb = Rf = R = 1KΩ and RL

=100KΩ on the CDS board.


3. Apply the input voltages from the regulated supplies to the corresponding inputs at the inverting & non-inverting input terminals of IC741 (pin no.2 & 3 respectively).

3. Connect the Digital Multimeter at the Output terminals (pin no.6), and note down the output voltage and verify with theoretical values.

4. Repeat the above steps for different input voltages.

Comparator

1. Connect the comparator circuit as shown in fig.3.

2. Connect the 1MHz function generator to the input terminals. Apply 1V signal at non-inverting terminals of the op-amp IC741.

3. Connect the 20MHz C.R.O at the output terminals.

4. Keep 1V reference voltage at the Inverting terminal of the Op-amp. When V in is less than the Vref, then output voltage is at –Vsat because of the higher input voltage at negative terminal. Therefore the output voltage is at logic low level

5. Now, Keep –1V reference voltage. When Vref is less than the Vin, then the output voltage is at +Vsatbecause of the higher input voltage at positive terminal. Hence, the output voltage is at logic high level.

6. Observe and record the output voltage and waveforms.

EXPECTED WAVEFORMS:

1. If Vrefis Positive in the Inverting comparator

2. If Vref is Negative in the Inverting comparator

3. If Vrefis Positive in the Non-inverting comparator

3

4. If Vref is Negative in the Non-inverting comparator

RESULT:

Adder and Subtractor are designed using 741 Op – Amp and the experimental results were compared with the theoretical values .Applied input signal is compared with reference voltages in a comparator using 741 Op – Amp and the corresponding waveforms were noted.

REVIEW QUESTIONS:

1. Draw an Op- amp circuit whose output VO = V1+ V2 – V3 –V4.

2. Show that the o/p of an n-input inverting adder is V0 = - (Va +Vb + … + Vn)

3. Design a mixed adder for V0=V1+2V2-V3-5V4.

4. Design a Subtractor for V0 = Va - 5Vb -2Vc

5. If a triangular waveform is applied to an op-amp in open loop configuration, with non-inverting terminal grounded, sketch the output wave form.

6. For the circuit shown determine the expression for V0.

7. For the circuit shown, find the current through R4.

Given: R1 = 10 kΩ; R2 = 20 kΩ; R3 = 1 kΩ, R4 = 4.8 kΩ; V1 = 1 V

8. Determine the value of V0 for the circuit shown, if V1 = 2V and V2 = 1V.

9. For the circuit shown, calculate I, V0 and ACL.

10. For the circuit shown, Rf = 470 kΩ. R1 = 10 kΩ, V1= −0.5 V. Calculate closed loop voltage gain ACL.

11. Draw the outputs for Inverting comparator with negative bias and non-inverting comparator with positive bias.

12.Draw the output waveform for Inverting comparator with positive bias of 2V and supply voltage ±12V.

13. Calculate VO in the circuit shown below for V1 = 5V, V2 = 2V.

14. For the circuit shown for Problem 14, if the peak input voltage is −5 V, determine the peak output voltage.

OUTCOMES:

1. After completion of this experiment the student will have a complete idea of open loop and closed loop usage of an Op-Amp.

2. Students will know about the connectivity and biasing of an IC(IC 741) and also the supply and input output ranges.

3. Students will be able to design ac or dc adder, subtractor and comparator for any type of input or any value of input.


INTEGRATOR AND DIFFERENTIATOR USING IC741

OP-AMP

PRELAB:

1. Immense knowledge of op-amp in open loop and closed loop configurations.2. Pinout of IC 741C with supply voltage rejection ratio.3. Concepts of integrator and differentiator and their mathematical relations of cut-off

frequencies and gain.

OBJECTIVE:

To design, construct and verify the response of

1. Integrator using Op-amp IC741.2. Differentiator using Op-amp IC741.

DESIGN CONSTRIANT: 1. Integrator using Op-amp IC741 for sine and square wave inputs at 1KHz frequency.2. Differentiator using Op-amp IC741 for sine and square wave inputs at 1KHz frequency.

APPARATUS REQUIRED:

1. Bread Board / CDS Board.2. Function Generator (1MHz).3. Cathode Ray Oscilloscope (20MHz/30 MHz)4. Regulated Power Supply (Dual Channel).5. Connecting Wires.


1. IC741 :1No2. Resistor ----- 10KΩ :2No3. 100KΩ POT/ Decade Resistance Box (DRB) :1No4. 10KΩ POT/ Decade Resistance Box (DRB) :1No5. Capacitor ---- 0.1µF :2No

CIRCUIT DIAGRAMS:

(a)Integrator:

Figure.1

(b)Differentiator:

Figure.2

THEORY:

1. Integrator

A circuit in which the output voltage waveform is the integration of the input is called integrator.

The equation (1) indicates that the output voltage is directly proportional to the negative integral of the input voltage and inversely proportional to the time constant R1CF. For Example if the input is a sine wave, the output will be a cosine wave or if the input is a square wave, the output will be a triangular wave.

When the input signal frequency is ZERO, the integrator works as an open – loop amplifier. This is because of the capacitor CF acts as an open circuit (XCF =1/ωCF = infinite for f=0).

Therefore the ideal integrator becomes unstable & suffers with low frequency noise. To overcome this problem RF is connected across the feedback capacitor CF. Thus RF limits the low-frequency gain and hence minimizes the variations in the output voltage.

Frequency fb at which the gain of the integrator is 0 dB, is given by

fb =1/2∏R1CF ----------- (2)

Both the stability and the low – frequency roll-off problems can be corrected by the addition of a resistors RFin the feedback path. The frequency response of practical integrator is as shown in figure (3). In this ‘f’ is relative operating frequency and for f <fa

gain of the integrator is constant and is equal to RF / R1. However after fa the gain decreases at a rate of 20dB/decade. In other words, between faand fb the circuit acts as an integrator. The gain-Limiting frequency fa is given by

fa =1/2∏RFCF ---------- (3)

NOTE: The input signal will be integrated properly if the time period T of the input signal is greater than or equal to RFCF.

2. Differentiator

The differentiator circuit performs the mathematical operation of differentiation. That is the output waveform is the derivative of the input waveform. Therefore

VO = RFC1dVin / dt -------------- (4)

The above equation (4) indicates that the output voltage is directly proportional to the derivative of the input voltage and also proportional to the time constant RFC1.

For Example if the input is a sine wave, the output will be a cosine wave or if the input is a square wave, the output will be spikes.

The reactance of the circuit increases with increase in frequency at a rate of 20dB/ decade. This makes the circuit unstable. In other words the gain of an ideal differentiator circuit is direct dependent on input signal frequency. Therefore at high frequencies (f=∞), the gain of the circuit becomes infinite making the system unstable.

The input impedance XC1 decreases with increase in frequency, which makes the circuit very susceptible to high frequency noise.

The frequency response of the basic differentiator is shown in figure.4 In this fig fa is the frequency at which the gain is 0 dB.

fa =1/2∏RFC1 ----------- (5)

Both the stability and the high – frequency noise problem can be corrected by the addition of two components R1 and CF as shown in figure.2.The frequency response of which is shown infig.4. From f to fa the gain decreases at 40dB/decade.This 40 dB/decade

change in gain is caused by the R1C1 and RFCF combinations. The gain limiting frequency fbis given by

fb =1/2∏R1C1 ---------- (6) Where R1 C1 = RF CF.

R1C1 and RFCF help to reduce significantly the effect of high frequency input, amplifier noise, and offsets. Above all, it makes the circuit more stable by preventing the increase in gain with frequency. In general, the value of f1, and in turn R1C1 and RFCF should be selected such that fa<fb< fc, Where fc is the unity gain- bandwidth of an open-loop Op-Amp.

NOTE: The input signal will be differentiated properly if the time period T of the input signal is greater than or equal to RF C1.

PROCEDURE:

Integrator

1. Connect the circuit as shown in figure.1 on the breadboard.2. Switch ‘ON’ the power supply and apply +15V to pin no.7 and -15V to pin no.4 of the

IC741.3. Apply a sine wave input signal of 2V peak-to-peak amplitude at 1 KHz frequencyfrom

the function generator (at pin no.2 of the IC741).4. Connect the C.R.O at (pin no.6) the output terminals.5. Observe and plot the input & output voltage waveforms.6. Measure the output voltage (Vo) from the experimental results.7. Calculate the output voltage of the inverting Amplifier theoretically using the formula

8. Apply a square wave input signal of 2V P-P amplitude at 1 KHz frequency from the function generator and repeat the above steps.

9. Compare the experimental results with the theoretical values.

Differentiator

1. Connect the circuit as shown in figure.2 on the breadboard.2. Switch ‘ON’ the power supply and apply +15V to pin no.7 and -15V to pin no.4 of the

IC741.3. Apply a sine wave input signal of 2V peak-to-peak amplitude at 1 KHz frequency from

the function generator (at pin no.2 of the IC741).4. Connect the C.R.O at (pin no.6) the output terminals.5. Observe and plot the input & output voltage waveforms.

6. Measure the output voltage (Vo) from the experimental results.7. Calculate the output voltage of the inverting Amplifier theoretically using the formula

VO = RFC1dVin /dt8. Apply a square wave input signal of 2V P-P amplitude at 1 KHz frequency from the

function generator and repeat the above steps.9. Compare the experimental results with the theoretical values.

EXPECTED WAVEFORMS:

Fig.3. Frequency Response of Integrator

Fig.4. Frequency Response of Differentiator

Fig.5a: Output waveform of Integrator for Sine wave input

Fig.5b: Output waveform of Integrator for Square wave input

Fig.6a: Output waveform of Differentiator for Sine wave input

Fig.6b: Output waveform of Differentiator for Square wave input

RESULT: The Integrator & Differentiator circuits were constructed using IC 741 and verified their response for sine & square wave inputs.

REVIEW QUESTIONS:

1.For an op-amp integrator circuit, sine wave input of 4 Sin 1000t is given. In the circuit, R = 200 MΩ and C = 0.1μF. Determine the value of output voltage.

2. Sketch the output wave forms, if a square wave input is applied to op-amp differentiator circuit. Given R = 0.1kΩ, C = 0.01μF frequency of the square wave input is 100Hzs.

3. Sketch the Input and Output waveforms when we apply a 1Khz triangle wave with peak to peak value of 5V to the Differentiator circuit.

4. What type of output waveform is obtained when a triangular wave is applied to integrator circuit?

5. A low frequency differentiator is desired for a particular application to Perform the operation Vo (t) =-0.001 dvi(t)/dt . Determine the suitable design of differentiator circuit for the periodic signal with a frequency of 1 KHz.

6Determine the component values of a differentiator circuit to perform true differentiation, when the input is a square wave of 1kHz frequency.

7. What value of R and C must be used if spike output is to be obtained from a square wave input of 5kHzs frequency? Draw the circuit.

8. Determine the component values of R and C to perform true integration, when the input given is a square wave of 1kHzs frequency.

9. It is desired to get triangular waveform output from square wave input of 5kHzs. Draw the circuit and give values of R and C.

10. For an op-amp integrator with R = 100 MΩ and C = 1μF, an input of 2sin1000t is applied. Determine the value of v0

OUTCOMES:

1. After completion of this experiment the student will have a complete idea of closed loop usage of an Op-Amp.

2. Students will know about the connectivity and biasing of an IC (IC 741) and also the supply and input output ranges.

3. Students will be able to implement the mathematical operators such as integration and differentiation for any type of input or any value of input.


PRECISION RECTIFIERS USING IC741 OP-AMPPRELAB:

1. Immense knowledge of op-amp in open loop and closed loop configurations.2. Pinout of IC 741C with supply voltage rejection ratio.3. Basic knowledge of precision rectifier (Half wave rectifier & Full wave rectifier) is

needed.

OBJECTIVE:

To construct precision half wave rectifier and full wave rectifier using Op Amp.

DESIGN CONSTRIANT:

1. Taking an Op-Amp design a circuit to conduction only in one direction.2. Design one circuit generate an output for conduction of one half of the input cycle and

also another circuit for complete input cycle in only one direction.

APPARATUS REQUIRED:

1. IC µA 741 OP-Amp2. Resistors3. AFO4. Diode IN 40015. Connecting wires6. CRO7. Bread board

CIRCUIT DIAGRAMS:

1. Precision Half Wave Rectifier

Figure.1HalfwaveRectifier

2. Precision Full Wave Rectifier

Figure.2 Fullwave Rectifier

THEORY:

The major limitation of ordinary diodes is that it cannot rectify voltage below 0.6v,thecutin voltage of the diode.The precision rectifier, which is also known as a super diode, is a configuration obtained with an operational amplifier in order to have a circuit behaving like an ideal diode and rectifier.It can be useful for high-precision signal processing.

Figure.3 Pin-outdiagramof 741Op-Amp

HALF WAVE RECTIFIER:

A half-wave rectifier is an electronic circuit. The rectifier circuit takes alternating current (AC) from the wall outlet and converts it into a positive direct current (DC) output. The particular electronic device that accomplishes this task is a semiconductor called a diode. The diode like all semiconductors is a material which has a resistance in between that of a conductor or wire and an insulator like that of a plastic.

FULL WAVE RECTIFIER:

A Full Wave Rectifier is a circuit, which converts an ac voltage into a pulsating dc voltage using both half cycles of the applied ac voltage. It uses two diodes of which one conducts during one half cycle while the other conducts during the other half cycle of the applied ac voltage.During the positive half cycle of the input voltage, diode D1 becomes forward biased and D2 becomes reverse biased. Hence D1 conducts and D2 remains OFF. The load current flows through D1 and the voltage drop across RL will be equal to the input voltage. During the negative half cycle of the input voltage, diode D1 becomes reverse biased and D2 becomes forward biased. Hence D1 remains OFF and D2 conducts. The load current flows through D2 and the voltage drop across RL will be equal to the input voltage.

PROCEDURE:

Precison Half Wave Rectifier and Full wave rectifier

1. Connect the circuit as shown in the figures for Half wave and Full wave rectifier.

2. Set the input signal voltage using AFO.

3. Observe the output waveform in CRO and measure the output parameters.

INPUT OUTPUT FREQUENCY

Amplitude Time Amplitude TimeON OFF

EXPECTED WAVEFORMS:

1.Precision Half Wave Rectifier

2. Precision Full Wave Rectifier

REVIEW QUESTIONS:

1. Draw the equivalent circuit of a full wave rectifier for input voltage less than zero volts(Vi<0)

OUTCOMES:

1. After completion of this experiment the student will have a complete idea of closed loop usage of an Op-Amp.

2. Students will know about the connectivity and biasing of an IC (IC 741) and also the supply and input output ranges.

3. Students will be able to implement the half wave and full rectifier circuit for an ac input to obtain a pulsating dc.


ACTIVE LOW PASS & HIGH PASS BUTTERWORTH FILTERS

(1st& 2nd ORDER)

PRELAB:

1. Immense knowledge of op-amp in open loop and closed loop configurations.2. Pinout of IC 741C with supply voltage rejection ratio.3. Concepts of low pass and high pass Butterworth filter and their mathematical relations

of cut-off frequencies and gain.

OBJECTIVE:

To design, construct and plot the frequency response of

1. 1storder low pass Butterworth filterwith cut-off frequency of 5KHz2. 1storder high pass Butterworth filter with a cut-off frequency of 1KHz.3. 2nd order Low pass & High pass Butterworth Active Filtersat1KHz frequency.

APPARATUS REQUIRED:

1. Bread Board / CDC Board.2. Function Generator (1MHz).3. Cathode Ray Oscilloscope (20MHz/30MHz)4. Regulated Power Supply (Dual Channel).5. Connecting Wires.6. Decade Resistance Box.


1. IC741 :1No

2. 1KΩ Potentiometer / DRB :1No3. Resistor ------- 10KΩ :2No

100KΩ :1No

4. Capacitor ----- 0.1µF :1No0.01µF :1No

CIRCUIT DIAGRAMS:

a) 1ST ORDER LOW PASS FILTER

Fig .1. Circuit diagram of 1st Order LPF

b) 1ST ORDER HIGH PASS FILTER

Fig .2. Circuit diagram of 1st Order HPF

C). 2ND ORDER LOW PASS FILTER AND HIGH PASS FILTER

Figure.3 Circuit diagram of 2nd Order LPF and HPF

THEORY:

A first order filter consists of a single RC network connected to the non-inverting input terminal of the op-Amp as shown in the figure. Resistors R1 &Rf determine the gain

of the filter in the pass band. Components R & C determine the cutoff frequency of the filter.

Low-Pass filter: The circuit of 1st order low-pas filter is shown in fig.1 & its frequency response is as shown in the fig3. The dashed curve in the fig.3 indicates the ideal response & solid curve indicates practical filter response. It is not possible to achieve ideal characteristics. However with special design techniques (Higher order filters) it is possible to closely approximate the ideal response. Active filters are typically specified by the voltage transfer function,

H(s) = V0 (s)/ Vi(s) ___________(1)(under steady state conditions)

i.e s=jω

=>H (jω) = H(jω) eJΦ(w)_________(2),

Where H(jω) is the magnitude function and eJΦ(w) is the phase function. Magnitude function is 20 log H(jω)dB & phase function is -Φ(ω) * 57.296 degrees.

High Pass Filter: The circuit of 1st order high pass filter is shown in fig.2 & its frequency response is as shown in the fig4. The dashed curve in the fig.4 indicates the ideal response & solid curve indicates practical filter response. When an input signal is applied to High pass filter, the signals at high frequencies are passed through circuit and signals at low frequencies are rejected. That is the signal which are having frequencies less than the lower cutoff frequency fL are rejected and the signal with frequency greater the lower cut off frequency fL are passed through the circuit. That is

1. For f >fL, Vo(s) /Vi(s) = Maximum and is called as pass band.

2. For f <fL, Vo(s) /vi(s) = 0 and is called as the stop band.

2nd order LPF and HPF:

An Improved filter response can be obtained by using a second order active filter. It consists of two RC pairs & has a roll-of rate of -40dB/decade. The results derived

can be used for analyzing Low pass & High pass filters.

The op-amp is connected as non-inverting amplifier as shown in the circuit diagram & hence,

V 0=(1+R f /R1 )V B=A f V B , where A f=1+

RfR1 & VB is the voltage at Node B.

Case I:For the Low Pass Filter

The Normalized Transfer Function H ( s )=

A fS2+αS+1

Where α is damping Factor

Normalized Frequency S =j (ω / ωh)

By putting S = jω

H ( jω )=A f

√1+(ωωh

)4

Case II: For HighPass Filter

H ( S )=A fS2+αS+1 Where S=j ω &

H ( jω )=A f

√1+(ωLω

)4

DESIGN:

Step1: Choose C = 0.01 µF

Step2: We have fh = 1/2π RC=>R=1/2 πf hC => R= 15.9 KΩ

In the Circuit R1=R2=R = 15.9 KΩ & C1 = C2 = C = 0.01 µF

Step3: Damping Factor (α) = 1.414 (From Butterworth Polynomials)

We have α = 3 - Af =>Af = 3 – α = 1.586

Step 4: But A f=1+

RfR1 yields Rf = 0.586 R1

Step 5: Choose R1 = 10 KΩ =>Rf= 5.86KΩ

PROCEDURE:

1st order Low pass Filter

1. Connect the circuit as shown in fig.1 on the breadboard.


2

1

3. Apply a sine wave input signal of 2V peak-to-peak amplitude from the function generator (at pin no.3 of the IC741 via RC Low pass network).

4. Connect the C.R.O at (pin no.6) the output terminals.

5. Increase the input signal frequency in steps from 10Hz to 1MHz & Observe the corresponding output voltage of the filter and tabulate the results.

6. Calculate the gain of the filter from the experimental results.

7. Plot the frequency response curve of the low pass filter with the experimental results obtained &compares it with the expected waveform shown in Fig.1.

OBSERVATION TABLE: VIN = 2V p-p

Input Frequency(fin) in Hz

Vin

Input volatage in volts

Vout

Output Voltage

in volts

GAIN

Vout/ Vin20 Log (Vout/ Vin) Magnitude in dB

1st order High pass Filter

1. Connect the circuit as shown in figure.2 on the breadboard.


3. Apply a sine wave input signal of 2V peak-to-peak amplitude from the function generator (at pin no.3 of the IC741 via RC High pass network).


5. Increase the input signal frequency in steps from 10Hz to 1MHz & Observe the corresponding output voltage of the filter and the results.

6. Calculate the gain of the filter from the experimental results.

7. Plot the frequency response curve of the high pass filter with the experimental results obtained & compare it with the expected waveform shown in Fig.2.

OBSERVATION TABLE:

VIN = 2V P-P

Input Frequency(Fin) in Hz

Vin

Input volatage in volts

Vout

Output Voltage

in volts

GAIN


PROCEDURE:

Second order Low –Pass Filter

1. Connect the circuit as shown in fig.1 on the breadboard with Y1=Y2=1/R & Y3=Y4= jωC.


3. Apply a sine wave input signal of 2V peak-to-peak amplitude from the function generator (at pin no.3 of the IC741).


5. Increase the input signal frequency in steps from 10Hz to 1MHz & Observe the corresponding output voltage of the filter.

6. Measure the gain of the filter from the experimental results.

7. Plot the frequency response curve of the low pass filter with the experimental results obtained & compare it with the expected waveform shown in Fig.2

OBSERVATION TABLE:

Vin=2V p-p


Vout

Output Voltage(in volts)

GAIN


Second order High –Pass Filter

1. Connect the circuit as shown in fig.1 on the breadboard with Y1=Y2= jωC& Y3=Y4=1/R.


3. Apply a sine wave input signal of 2V peak-to-peak amplitude from the function generator (at pin no.3 of the IC741).


5. Increase the input signal frequency in steps from 10Hz to 1MHz & Observe the corresponding output voltage of the filter.

6. Measure the gain of the filter from the experimental results.

7. Plot the frequency response curve of the low pass filter with the experimental results obtained & compare it with the expected waveform shown in Fig.3.

OBSERVATION TABLE:

Vin = 2V p-p


Vout

Output Voltage(in volts)

GAIN


DESIGN PROCEDURE:

Pass band gain of the active filter VO/Vin = Af= 1 + Rf/R1 __________(3)

Higher cut-off frequency of the low pass filter, fH =1/2ПRC ____________(4)

Lower cut-off frequency of the High pass filter, fL =1/2ПRC ____________(5)

First order LPF

1. The higher cut-off frequency is given as, fH = 5 KHz.

2. Choose the value of C such that the value of C ≤1µF (Typically C= 0.1µF)

3. Calculate the value of R, using the formula

R =1/2ПCfH ___________ (6)

= 318.47Ω (320 Ω Approx.)

4. Get the value of damping factor, α from the Butterworth polynomials

Note: For a 1st order Butterworth active filter, the value of damping factor α=1 (from Butterworth polynomials)

1. Calculate the value of pass-band gain, AF using the formula, α =3-Af _________ (7)

=> AF = 3- α = 3-1= 2 _________ (8)

6. Using the formula AF = 1 + RF/R1, get a relation between RF & R1.

=>RF/R1=AF -1 = 1

=>RF=R1 _______________(9)

7. Choose the value of R1=10 KΩ => RF=10 KΩ ___________ (10)

First order HPF

1. The lower cut-off frequency is given as, fL = 1 KHz.

2. Choose the value of C such that the value of C ≤1µF (Typically C= 0.01µF)

3. Calculate the value of R, using the formula

R =1/2ПCfL= 15.9 KΩ __________ (11)

4. Get the value of damping factor, α from the Butterworth polynomials

Note: For a 1st order Butterworth active filter, the value of damping factor α=1 (from Butterworth polynomials)

5. Calculate the value of pass-band gain, AF using the formula, α =3-Af _________ (12)

=> AF = 3- α = 3-1= 2 _________ (13)

6. Using the formula AF = 1 + RF/R1, get a relation between RF & R1.

=>RF/R1=AF -1 = 1

=>RF=R1 _________ (14)

7. Choose the value of R1=10 KΩ => RF=10 KΩ _________ (15)

EXPECTED WAVEFORMS:

Figure. 4 Frequency response of 1st Order LPF

Figure. 5 Frequency response of 1st Order HPF

Figure. 6 Frequency response of 2nd Order LPF

Figure. 7 Frequency response of 2nd Order HPF

RESULT: The first and second order LPF & HPF are designed for a chosen cutoff frequency and the frequency response curves were plotted between voltage gain (dB) and frequency (Hz).

REVIEW QUESTIONS:

1. Design a first order low pass filter for 2KHz frequency.

2. Design a five pole low pass active Butter worth filter with 3dB cut off frequency of 2 KHz.

3. Show that the amplitude response of low pass Butter worth filter well above cutoff decreases by 20dB per decade.

4. Draw the fourth order High pass filter for cut off frequency fL=10 KHz.

5. Design a two pole high pass active Butter worth filter with a 3dB cutoff frequency of 1 KHz.

6. Design 4th order butter worth high pass filter with 3dB cutoff frequency of 5 KHz.

7. Design a second order LPF in Butterworth Type to have unity gain and cut-off frequency of 800 Hz, and maximally flat response.

8. Determine the component values for a Chebyshev filter with positive, non-unity gain, second order LPF, to have fc = 500 Hzs and 0.5 db ripple.

9. Determine the component values for a second order BRF, to reject the frequencies in the range 5 kHz to 15 kHz.

10. Determine the component values for a fourth order Butterworth HPF with fc = 15 kHz, given 2K1 = 0.765; 2k2 = 1.848.

11. Determine the component values of a Chebyshev filter with positive non-unity gain, LPF of second order to have 3 db frequency = 500 Hz and 0.5 db ripple

12. Design a BRF to have fL = 25 kHz and fH = 1 kHz.

13. For the circuit shown if R = 22 kΩ, C = 0.01 μF, determine the value of fc.

14. Design and setup a filter with roll off rate = 60 dB/decade.

15. Design and setup a filter with roll off rate = -40 dB/decade.

16. Design and setup a filter with roll off rate = 40 dB/decade, which blocks all thesignals of frequency less than 2 KHz and greater than 6 KHz.

OUTCOMES:1. Student will know the difference between passive and active filters.2. They will be getting the concept of pass band, stop band and the cut off frequency.3. After performing this experiment student will be able to design any type of filter

required for any cut off frequency which is usually used in the field of communication systems.

PART-A EXPERIMENT NO:6

RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS USING IC 741 OP-AMP

PRELAB:

1. Immense knowledge of op-amp in open loop and closed loop configurations.2. Pinout of IC 741C with supply voltage rejection ratio.3. Concepts of Oscillator and their conditions of sustained oscillations and the

construction of low frequency sinusoidal oscillators are required.

OBJECTIVE:1. To study and designan RC Phase shift Oscillator using IC 741 Op-Amp anddetermine

the frequency of Oscillations.2. To study and design the WeinBridge Oscillator using IC 741 Op-Amp and to determine

the frequency of Oscillations.

DESIGN CONSTRAINT: 1. To design an RC Phase shift Oscillator using IC 741 Op-Amp for a frequency of 649Hz.2. To design theWeinBridge Oscillator using IC 741 Op-Amp for a frequency of 1.06KHz.

APPARATUS REQUIRED: 1. Bread Board/ CDS Board2. Cathode Ray Oscilloscope3. Regulated Power Supply (Dual Channel).4. Connecting Wires.

COMPONENTS REQUIRED:1. Resistors ----- 1KΩ : 4No.

33KΩ : 1No.15KΩ : 1No.

1.5KΩ : 2No.100KΩ : 1No.

2. Capacitors ---- 0.1µF : 3No.3. IC 741 :1 No.4. Decade Resistance Box : 1 No

CIRCUIT DIAGRAM:

RC Phase shift Oscillator

Figure.1

Wein–Bridge Oscillator

Figure.2

THOERY:


Phase shiftoscillator which consists of an Op-Amp as the amplifying stage & three RC cascaded networks as the feedback circuit that provides feedback voltage from the output back to the input of the amplifier. The output is used in inverting mode. Therefore any signal that appears at the inverting terminal is shifted by 1800 phase shift required for oscillation is provided by the cascaded RC networks. Thus the total phase shift of the cascaded RC networks is exactly 3600 or 00. At some specific frequency when the phase shift of the cascaded RC network is exactly 1800 and the gain of the amplifier is sufficiently large and circuit oscillates at that frequency.

The frequency of oscillations f0 is given by

At this frequency the gain Av must be at least be 29.

That is

=>Rf= 29 R1

Thus the circuit will produce a sinusoidal waveform of frequency fo if the gain is 29 and the total phase shiftaround the circuit is exactly 3600.


The most commonly used audio frequency oscillator is wien-bridge oscillator. From the figure shown above it may be noted that the feedback signal in the circuit is connected to the positive terminal so that the Op-Amp is working as a non-inverting amplifier. Therefore the feedback network needs not to provide any phase shift. The circuit can be viewed as a wien bridge with a series RC network in one arm and a parallel RC network in the adjoining arm. The addition of zero phase around the circuit is achieved by balancing the bridge.

The frequency of the oscillations in WeinBridge is given by

fO = 1/ 2∏RC

At fO, The feedback factor β is equal to 1/3. Therefore for sustained oscillation, the amplifier must have a gain of precisely 3. However from practical point of view, AVmay be slightly less or greater than 3. For AV<3 the oscillations will either die down or fail to start when power is first applied and for AV>3, the oscillations will be growing.

DESIGN PROCEDURE:1. For a frequency f=1/2∏RC√6.of 650Hz RC Phase Shift Oscillator of R=1KΩ & C=0.1µF

are chosen and for gain more than 29,Rf=100KΩ and R1=1KΩ.2. For a frequency f=1/2∏RCof 1.06KHz Wein bridge Oscillator of R=1.5KΩ & C=0.1µF

are chosen and for gain of 3,Rf=30KΩ and R1=15KΩ.

PROCEDURE:


1. Connect the circuit as shown in figure1.2. Connect Oscilloscope at output terminals V0 observe the output sine wave.3. Record the output waveform andmeasure the practical frequency of the output

waveform.4. From the given values of R & C calculate theoretical frequency using the formula

f=1/2∏RC√6.5. Compare the theoretical and practical frequencies.


1. Connect the circuit as shown in the figure1.2. Connect the C.R.O at the output terminals and observe the output waveform.3. Record the output waveform and measure the practical frequency from the waveform.

4. For different values of R, calculate theoretical frequency using the formulafO = 1/ 2∏RC

and also measure the frequency of output signal from the waveform.5. Compare the theoretical and practical frequencies of the output signal.

OBSERVATION TABLE:

S.NO

R (in Ohms) C ( in µF)f theoretical = 1/2∏RC√6

(in Hz)

f practical

(in Hz)

S.NO

R (in Ohms) C ( in µF)f theoretical = 1/2∏RC

(in Hz)

f practical

(in Hz)

EXPECTED WAVEFORM:

Fig.2

RESULT:

Operation ofRC Phase shift Oscillator and Wein –Bridge Oscillator using IC 741 Op-Ampis studied and oscillations of 650Hz and 1.06KHz frequency are generated respectively.

REVIEW QUESTIONS:

1. Generate the waveform,

2.Generate the waveform,

3.Generate the waveform,

4.A μA 741C op-amp is used in the circuit, the output voltage for the ideal op-amp will be

5. Construct a phase shift oscillator for fo= 500Hz and study its operation.6. Calculate the value of C1 = C2 for the Wien bridge oscillator to operate at a frequency

of 20 kHz. Assume R1 = R2 = 50 k and R3 = 3R4 = 600 ?

7. Refer to this figure. Calculate the resonant frequency

8. Referring to this figure, calculate the voltage gain with the feedback for the following circuit values: RD = 4 k , RS = 1 k , RF = 15 k , and gm = 5000 μS.

9. Given gm = 5000 S, rd = 40 k , R = 10 k , and A = 35. Determine the value of RD

for oscillator operation at 1 kHz.

10. An amplifier with a gain of –500 and a feedback of = –0.1 has a gain change of 15% due to temperature. Calculate the change in gain of the feedback amplifier.

11. Referring to this figure, calculate the amplification gain where the op-amp gain (A) is 200,000, R1 = 1.5 k , and R2 = 400 .

12. Referring to this figure, calculate the voltage gain with feedback Avf.

13. Determine the voltage gain with feedback for a voltage-series feedback having A = –100, R1 = 15 k , Ro = 20 k , and a feedback of = –0.25.


ASTABLE AND MONOSTABLE MULTIVIBRATOR USING IC 555 TIMER

PRELAB:

4. Immense knowledge of op-amp in open loop and closed loop configurations.5. Pinout of IC 741C with supply voltage rejection ratio.6. Concepts of multivibrators and IC555 modes of operation along with their

mathematical relations of cut-off frequencies and gain.

OBJECTIVE:

1. Using IC555 design a. AstableMultivibratorb. MonostableMultivibrator

DESIGN CONSTRAINT:

1. To design an AstableMultivibrator using IC 555 timer to generate a square wave of 6.9 KHz with 52.38 % Duty Cycle.

2. To design a MonostableMultivibrator using 555 timer to get 10msec pulse output.

APPARATUS:

1. C.R.O2. Function generator3. Regulated DC power Supply4. CDS Board/ Bread Board.5. Connecting patch chords.


1. IC 555 Timer :1 No.2. Resistors ---- 100 KΩ :1 No.

10 KΩ :1 No.1 KΩ :1 No.

3. Capacitor ---- 1µF :1 No.0.01µF :1 No.

CIRCUIT DIAGRAM:

PIN CONFIGURATION OF 555 TIMER:

Figure. 1

MONOSTABLE MULTIVIBRATOR

Figure.2MonostableMultivibrator

Figure.3 Trigger Circuit

1.ASTABLE MULTIVIBRATOR:

Figure.4AstableMultivibrators

THEORY:

The 555 Timer is used in number of applicationsit can be used as monostable, Astablemultivibrators, DC to DC converters, digital logic probes, analog frequency meters, voltage regulators and time delay circuits.

The IC 555 timer is 8-pin IC and it can operate in free- running (Astable) mode or in one-shot (Monostable) mode. It can produce accurate and highly stable time delays or oscillations. MonostableMultivibrator can also called as One-shot Multivibrator. Figure.1 shows the Pin configuration of IC555 and figure.2 is aMonostableMultivibrator. When the output is low, the circuit is in stable state, Transistor Q1 is ON and capacitor C is shorted out to ground. However, upon application of a negative trigger pulse to pin-2, transistor Q1 is turned OFF, which releases short circuit across the external capacitor and drives the output High. The capacitor C now starts charging up toward Vcc through R. However, when the voltage across the external capacitor equals 2/3 Vcc, the output of comparator1

switches from low to high, which in turn drives the output to its low state. The output,of the flip flop turns transistor Q1 ON, and hence, capacitor C rapidly discharges through the transistor. The output of the Monostable remains low until a trigger pulse is again applied. Then the cycle repeats. Figure.3 shows the trigger circuit & Figure 5 shows trigger input, output voltage and capacitor voltage waveforms.

Pulse width of the trigger input must be smaller than the expected pulse width of the output waveforms. Trigger pulse must be a negative going input signal with amplitude larger than 1/3 Vcc. The time during which the output remains high is given by

tp =1.1RC -------------(1)

Once triggered, the circuit’s output will remain in the high state until the set time tp elapses. The output will not change its state even if an input trigger is applied again during this time interval tp.

The IC 555 timer is 8-pin IC and it can operate in free- running (Astable) mode or in one-shot (Monostable) mode. The pin configuration of NE 555 Timer is as shown figure.1. It can produce accurate and highly stable time delays or oscillations.

AstableMultivibrator often called a free-running Multivibrator. External Trigger input is not required to operate the 555 as an Astable Configuration. However, the time during which the output is either high or low is determined by two external components Resistor & Capacitor. Figure.4 shows the 555 as AstableMultivibrator. Initially, when the output is high, capacitor C starts charging towards Vcc through resistor Ra and Rb. As soon as voltage across the capacitor equals to 2/3 Vcc, comparator-1 triggers the flip-flop, and the output is low. Now capacitor discharges through Rb and transistor Q1. When the voltage across capacitor C equals to 1/3Vcc, comparator-2’s output triggers the flip-flop, and the output goes high. Then the cycle repeats. The output voltage waveforms are as shown in figure.5.In this way capacitor periodically charges and discharges between 2/3Vcc and 1/3Vcc respectively.

The time during which the capacitor charges from 1/3Vcc to 2/3 Vcc is equal to the ONtime of the timer (i.e. the output is HIGH) and is given by

tc=0.69(Ra+Rb)C ---- (1)

The time during which the capacitor discharges from 2/3 Vcc to 1/3Vcc is equal to the OFF time of the timer, during which the output is LOW and is given by

td =0.69(Rb)C ---- (2)

The total time period of the output is the sum of charging time (tc)and discharging time(td) and is given by

T = tc + td= 0.69(Ra + 2Rb) C --- (3)

Therefore the frequency of oscillations of Astablemultivibrator is given by

F = 1/T = 1.45/ (Ra + 2Rb) C --- (4)

DUTY CYCLE:

This term is in conjunction with AstableMultivibrator. The duty cycle is the ratio of the ONtime, tc during which the output is high to the total time period T. It is generally expressed as a percentage.

Duty cycle, D = (TON /TON+ TOFF) = tc /T = (Ra + Rb) / (Ra + 2Rb) --- (5)

DESIGN PROCEDURE:

MONOSTABLE MULIVIBRATOR:

1.Choose C=1µF.

2. Since in monostablemultivibrator, tp=1.1RC.

Therefore, R= tp/ 1.1C ---- (2)

3. Using equation 2, design the value of R.

ASTABLE MULTIVIBRATOR:

1. Choose C=0.01 µF

2. Using the formula,F = 1.45/ (Ra + 2Rb) C, Get a relation between Ra&Rb.

3. Consider the expression for duty cycle,D= (TON /TON+ TOFF) = (Ra + Rb) / (Ra +2Rb) & obtain a relation between Ra &Rb.

4. Using the relations between Ra &Rb., obtained in step2 & step3, solve for Ra &Rb.

PROCEDURE:

MONOSTABLE MULIVIBRATOR:

1. Connect the 555 timer in Monostable mode as shown in figure.1.

2. Connect the C.R.O at the output terminals & observe the output.

3. Apply external trigger at the trigger input terminal (PIN 2) and observe the output of MonostableMultivibrator.

4. Record the trigger input, voltage across the capacitor & output waveforms and measure the output pulse width.

5. Verify results with the sample output waveforms as shown in figure.5

6. Calculate the time period of pulse (tp =1.1RC) theoretically & compare it with practical values.

ASTABLE MULTIVIBRATOR:

1. Connect the IC 555 timer in Astable mode as shown in figure.4

2. Connect the C.R.O at the output terminal (pin 3) and observe the output.

3. Record the waveforms at pin3, across the capacitor & compare them with the sample output waveforms as shown in fig (3).

4. Measure the charging time (tc), discharging time (td) and total time period/ Frequency from the output waveform.

5. Calculate tc, td, time period (T), frequency (f) of the square wave output and percentage duty cycle theoretically.

6. Compare the theoretical values charging time (tc), discharging time (td) ,total time period/ Frequency & % Duty cycle with the practical values.

OBSERVATION TABLE:

S.No

Theoretical value of o/p pulse width (in m.sec)

(tp =1.1RC)

Practical value of the o/p pulse width (in

m.sec)

S.NO

Theoretical Values Practical Values

tc

(m.sec)td

(m.sec)T

(m.sec)F

(Hz)D tc

(m.sec)td

(m.sec)T

(m.sec)F

(inHz)D

EXPECTED WAVEFORMS:

Figure.5

Figure.6

RESULT:

Hence designed & studied 555 timer as a Monostablemultivibrator and Astablemultivibrator also theoretical & Practical of time period values of the output waveform are compared.

REVIEW QUESTIONS:

1. Consider the Astablemultivibrator with R1=10KΩ,R2=200KΩ and C=0.1µF. Determinea) High state interval b) Low state interval c) Period d) Frequency e) Duty cycle.2. Design an Astable 555 timer circuit to produce a 2kHz square wave with a duty cycle

of 70%. 6. What is the function of control input (pin5) of 555 timer?3. Compare the time period ‘T’ of the Astablemultivibrator using IC555 timer& op-amp

IC741.4. Why do we connect pin 4 of IC 555 timer to supply pin when it is not used.5. Consider 555 monostablemultivibrator circuit. If RA = 10 kΩ, determine the value of C

for output pulse duration of 1 msec.6. For the above circuit, if RA = 10 kΩ and C = 0.1 μF, determine the value of tH.7. In the case of 555 monostable circuit, if RA = 10 kΩ and C = 0.2 μF, calculate the time

interval.8. Considering the circuit monostable what value of RA should be installed, to divide a 5

kHz input signal by 3?9. The Monostablemultivibrator circuit is to be used as a divided by 2 network. The

frequency of the input trigger signal is 2 KHz. If the value of C=0.01 µF, what should be the value of RA (Let tp =1.2T).

10. Consider the Monostablemultivibrator with R=3KΩ and C=0.0068µF. Determine the pulse width.

11. Design a Monostablemultivibrator to produce an output pulse 2 msec wide.

OUTCOMES:

1. Usage of IC555 timer will be known.2. Student will know the design of Monostable and Astablemultivibrator using IC555.3. After performing this experiment student will be able to design a square wave

generator of various frequencies and use it in various field of electronics.


SCHMITT TRIGGER USING IC741 AND IC555 OP-AMP

PRELAB:

1. Immense knowledge of op-amp in open loop and closed loop configurations.2. Pinout of IC 741C with supply voltage rejection ratio.3. Concepts of Sine to Square converter using IC741, IC555 and their mathematical

relations of upper and lower threshold voltages.

OBJECTIVE:

1. To construct and study the Schmitt Trigger using IC741 Operational Amplifier. 2. To construct and study of the Schmitt Trigger using IC 555 timer.

DESIGN CONSTRIANT:

1. To design a schmitt trigger for an upper threshold of +1.09V and lower threshold of -1.09V using IC 741 for with saturation voltages as 14V.

2. To design a schmitt trigger using IC555 with a duty cycle of 50%.

APPARATUS REQUIRED:

1. Function Generator.2. Regulated DC power Supply.3. Dual Channel Oscilloscope(CRO).4. Digital Multimeter.5. CDS Board / Bread Board.6. Connecting wires.


1. IC 741 : 1 No.2. Resistors -------- 1KΩ : 2 No.3. Decade Resistance Box (DRB) : 1 No.

CIRCUIT DIAGRAM:

Figure.1

Figure.2

THEORY:

Circuit diagram of Schmitt trigger is shown in Figure 1. It’s also called regenerative comparator. The input Voltage is applied to the inverting terminal &feed back voltage to the non-inverting terminal. The input voltage vitriggers the output Voevery time it

exceeds certain voltage levels. These voltage levels are called upper threshold & lower threshold. The hysteresis width is difference between these two values.

These voltages are calculated as follows

Suppose the output voltage Vo= +Vsat. The voltage at inverting terminal will be

----- (1)

For Vo= -Vsatthen

---- (2)

The input voltage Vi must become lesser than VLin order to cause Vo to switch from -Vsatto + Vsat.

The hysterisiswidth VHcan be written as

---- (3)

In Schmitt Trigger two internal comparators are tied together and externally biased at VCC/2 through R1 & R2. Since the upper comparator will trip at (2/3) VCC and lower comparator at (2/3) VCC the bias provided by R1 & R2 is centered within these two thresholds. Thus a sine wave of sufficient amplitude (>VCC/6 = 2/3 VCC – VCC/2) to exceed the reference levels causes the internal flip –flop to alternately set and reset providing a square wave output.

PROCEDURE:

Schmitt trigger using IC 741:

1. Connect the circuit as shown Figure.1.

2. Set Function Generator output for sine wave signal of Amplitude at 1V(p-p) & frequency

1KHz.

3. Set R1 and R2 values at fixed positions and note down the values in tabular column.

Calculate theoretical values of Vut and Vlt and note down the values in tabular column.

(+Vsat = 14V,- Vsat = -14V).

4. Apply Function Generator output at input terminals Vi, connect C.R.O.- CH2 at output

terminals Vo, C.R.O-CH1 at input terminals Vi.

5. Observe square wave output on C.R.O for the given input sine wave & compare them

with the sample waveform as shown in fig.2.

6. Note down the practical Vut, Vlt and VH values in tabular column.

7. Compare the theoretical and practical values of Vut,Vlt and VH.

Schmitt trigger using IC555:

1. Connect the circuit as shown in fig (1).

2. Apply the input sine wave 5V (P-P) using function generator at 1KHZ frequency.

3. Observe the output waveform at Pin No: 3.

4. Calculate the duty cycle using formula.

= =0.5 or 50%

OBSERVATION TABLE:

S.No

Theoretical Values Practical Values

R1 R2

in Volts in Volts

VH

in volts

Vlt(Volts)

Vut

(Volts)

VH

in volts

INPUT AND OUTPUT WAVE FORMS OF SCHMITTH TRIGGER:

Fig.2

RESULT:

A sine to square wave converter is studied and implemented with the Schmitt Trigger circuit using IC 741 and 555 timer.

REVIEW QUESTIONS:

1. In the circuit shown R2 = 100Ω, R1 = 50KΩ ,Vref = 0V, Vi = 1VPP(Peak to Peak) sine wave and saturation Voltage = ± 14V. Determine threshold voltages VUT and VLT

2. Find UTP and LTP values when R1=20 KΩ, R2=5KΩ, Vref=0V and Vcc=±12v

3. When the op amp is operated with Vcc=± 12 V then what will be the saturated output voltages.

4. Calculate the threshold voltage and sketch the input-output characteristics curve with

R1 = 10Kohms, R2 = 16Kohms & V = ± 13V for Inverting Schmitt trigger.

5. Sketch the output waveform, when a triangular wave of 5V p-p is applied to non- inverting Schmitt trigger.

6. Design a symmetrical square waveform generator of 10kHz.

7.Construct and observe the waveforms of a 1 KHz square wave form generator using 555 timer for duty cycle of 0.25 and 0.50.

OUTCOMES:

1. Student will know the circuit that can convert a sine wave to square wave.2. A schmitt trigger construction using IC 741 and IC 555 is known.3. After performing this experiment student will be able to design and used a sine to

square converter in various field of electronics.

PART-A EXPERIMENT NO:9

PHASE LOCKED LOOP (PLL) USING IC 565

PRELAB:

1. Immense knowledge of Phase Locked Loop IC 565 Pinout diagram and internal circuitry is required.

2. Supply voltage application to IC565 should be known..3. Basic terminology like free running range, lock in range capture range should be

known.

OBJECTIVE:

To calculate free running frequency, capture range and lock range of PLL System.

DESIGN CONSTRAINTS:

Design PLL for a free running frequency of 3KHz using IC565.

APPARATUS REQUIRED:1. C.R.O2. Function Generator 3. DC power supply 4. CDS board / Bread Board5. Connecting wires

COMPONENTS REQUIRED:1. LM 565 IC : 1No2. Resistors 10K : 1No

680Ω : 2No3. Capacitors 0.1F : 1No

1F : 1No 0.01F : 1No

CIRCUIT DIAGRAM:PIN DIAGRAM:

Figure.1 Pin configuration of IC 565

Figure. 2 Phase-locked loop (PLL)

THEORY:

The fig.1 shows the phase-locked loop (PLL) in its basic form. The PLL consists of i) a phase detector ii) a low pass filter and iii) a voltage controlled oscillator as shown. The phase detector, or comparator compares the input frequency f IN with the feedback frequency fOUT. The output of the phase detector is proportional to the phase difference between fIN and fout. The output voltage of a phase detector is a dc voltage and therefore is often referred to as the error voltage. The output of the phase detector is then applied to the low-pass filter, which removes the high-frequency noise and produces a dc level. This dc level, in turn, is the input to the voltage-controlled oscillator (VCO). The filter also helps in establishing the dynamic characteristics of the PLL circuit. The output frequency

of the VCO is directly proportional to the input dc level. The VCO frequency is compared with the input frequencies and adjusted until it is equal to the input frequencies. In short, the phase-locked loop goes through three states: free running, capture, and phase lock.

Before the input is applied, the phase-locked loop is in the free-running state. Once the input frequency is applied, the VCO frequency starts to change and the phase-locked loop is said to be in the capture mode. The VCO frequency continues to change until it equals the input frequency, and the phase-locked state. When phase locked, the loop tracks any change in the input frequency through its repetitive action.LockRange: The range of frequencies over which the PLL can maintain lock with incoming signal is called the “ LockRange” or “TrackRange”

fL= 8f0/V-------(1) where V= + V –(–V), where f0 is free running frequency.Capture range: The range of frequencies over which the PLL can acquire lock with an input signal is called the capture range.

fC = [fL/ 2(3.6 103)C2 ] ½ ---------(2)PROCEDURE:

1. Apply +5v to pin 10 and –5v to pin 1 of LM565 2. Connect R1= 10K resistor from pin 8 to10 and C1 =0.01F capacitor from pin 9 to

1.3. Connect 680 resistor from pin 2 & pin 3 to ground.4. Connect pin 4(VCO o/p) to CRO and measure its frequency. This frequency is

called the free running frequency, fo.

5. Calculate f0 theoretically using the formula f0 = 1.2 /4R1C1 and compare it with practical value.

6. Connect the circuit as shown in fig.7. Apply square wave at the input with an amplitude of 2Vpp and also connect it to

channel 1 of CRO. 8. Connect pin 4(VCO o/p) to channel 2 of CRO.9. Vary the input signal frequency in steps and measure its corresponding o/p

frequency.10. Find the lock range and capture range from the obtained data.11. Calculate lock range, fL and capture range, fC theoretically using formula

fL= 8 f0/V Hz where V = +V- (-V)and fC= [ fL/(2 3.6 103 C2 )]1/2

12. Compare theoretical and practical values.

TABULAR COLUMN:

S.No. Input Output fCin Hz fL in Hz

frequency, Hz frequency, Hz

RESULT:Free running frequency, lock range and capture range of PLL are measured practically and compared with theoretical values.

REVIEW QUESTIONS:

1. For a PLL select the filter components whose lowest frequency from phase detector is 5 Hz. A 0.5% variation in frequency is allowable. How long will it take for output from the filter to stabilize?

2. Design a PLL for the given specificatons, f0 = 2.5 kHz, fc = 50 Hz, VCC = − VEE = 12 V.3. If the free running frequency, VC voltage shift from VCO, the new frequency shift from

VCO in a PLL is?

4. Determine the dc controlled voltage Vc at lock if signal frequency fs= 10 KHz,VCO free running frequency is 10.66kHz and the voltage to frequency transfer coefficient of VCO is 6600Hz/V.

5. Calculate the output frequency fo , lock range ΔfL and capture range Δfc of a 565 PLL if RT=10KΩ ,CT= 0.01µF and C=10µF.

OUTCOMES:

1. Usage of IC565 Phase Locked Loop will be known.2. Student will know the usage of IC565 for frequency synchronization.3. After performing this experiment student will be able to use PLL IC565 for measuring

the incoming signal frequency in the field of Communication systems.


VOLTAGE REGULATOR IC 723, THREE TERMINAL VOLTAGE REGULATORS- 7805 AND7905.

PRELAB:

1. Immense knowledge of voltage regulator.2. Pinout of IC7805, IC7905 and IC723 should be known.3. Connectivity of the regulator ICs and their voltage ranges.

OBJECTIVE:

1. To construct and study the 3-terminal fixed voltage regulator using IC 78XX and 79XX series.

2. To construct and study low and high voltage regulators using IC 723.3. To find the %regulation of low and high voltage regulators.4. To find line regulation and load regulation of the IC regulator.

DESIGN CONSTRAINTS:

1. Design and verify the fixed voltage regulators for +5V and -5V.2. Design and verify the variable voltage regulator for low voltage of +3V and high

voltage of +12V using IC723.

APPARATUS REQUIRED:

1. Oscilloscope.2. Digital Multimeter.3. Connecting patch chords.4. CDS Board / Bread Board5. Regulated Power Supply

COMPONENTS REQUIRED:1. IC 723 : 1No.

IC7805 :1No.IC 7905 :1No.

2. Resistors ---- 2.2KΩ : 2No. 1 KΩ : 1No. 10K POT : 1No.

3. Capacitors ---- 100 pF : 1No.0.1 µF : 1No.1000 µF : 1 No.22 µF : 1 No.

CIRCUIT DIAGRAM:

Figure.1Fixed Positive Voltage regulator

Figure.2Fixed Negative Voltage Regulator

Figure.3 Low voltage Regulator

Figure.4 High Voltage Regulator

THEORY:

The IC 723 is a monolithic integrated circuit voltage regulator featuring high ripple rejection, excellent input and load regulation & excellent temperature stability etc. It consists of a temperature compensating reference voltage amplifier, an error amplifier, 150mA output transistor and an adjustable output current limiter.

The basic low voltage regulator type 723 circuit is shown in figure.1.The unregulated input voltage is 24V and the regulated output voltage is varied from 0.2V to 7.5V by varying the value of R2. A stabilizing capacitor (C1) of 100pF is connected between frequency compensation terminal and inverting (INV) terminal. External NPN pass transistor is added to the basic 723-regulator circuit to increase its load current capability. For intermediate output voltages the following formula can be used

Vout = (R2/R1+R2) Vref----------(1)

The basic high voltage regulator type 723 circuit is shown in figure.2.The output voltage can be regulated from 7 to 37Volts for an input voltage range from 9.5 to 40Volts. For intermediate output voltages the following formula can be used

----------(2)

DESIGNPROCEDURE:For fixed positive voltage regulator (7805):

1. Connect the circuit diagram as shown in figure.1.

2.Apply the unregulated voltage to the IC 78XX and note down the regulator output voltage,varyinput voltage from 7V to 20V and record the output voltages

3. Calculate the line regulation of the regulator using the formula

Line Regulation = ΔVO /ΔVi------------- (3)

4. By varying the load resistance RLnote down the regulator output voltage.

5.Calculate the Load regulation of the regulator using the formula

Load Regulation =ΔVO / ΔIL ------------(4)

For fixed negative voltage regulator (7905):


2.Apply the unregulated voltage to the IC 79XX and note down the regulator output voltage, varyinput voltage from 7V to 20V and record the output voltages

3. Calculate the line regulation of the regulator using the formula

Line Regulation = ΔVO /ΔVi------------- (3)

4. By varying the load resistance RLnote down the regulator output voltage.

5.Calculate the Load regulation of the regulator using the formula

Load Regulation ==ΔVO / ΔIL ------------(4)

LOW VOLTAGE REGULATOR


2. Apply the unregulated voltage to the 723 IC and note down the regulator output voltage.

3.Calculate the line regulation of the regulator using the formula

Line Regulation = ΔVO / ΔVi-------------(3)

4. By varying 10K potentiometer at the load section and note down the regulator output voltage.

5. Calculate the Load regulation of the regulator using the formula

Load Regulation ==ΔVO / ΔIL ------------(4)6. Also calculate the Percentage of load regulation using the formula

----------------- (5)Where E1 = Out put voltage without load & E2 = Out put voltage with load.

HIGH VOLTAGE REGULATOR

1. Connect the circuit diagram as shown in figure.4.2. Apply the unregulated voltage to the 723 IC and note down the regulator output

voltage.3. Calculate the line regulation of the regulator using the formula

Line Regulation = ΔVO / ΔVi ------------ (6)4. By varying 10K potentiometer at the load section and note down the regulator output

voltage.5. Calculate the Load regulation of the regulator using the formula

Load Regulation = ΔVO / ΔIL ------------ (7)6. Also calculate the Percentage of load regulation using the formula

-----------------(8)Where E1 = Output voltage without load & E2 = Output voltage with load.

OBSERVATION TABLE:

1.FOR POSITIVE VOLTAGE REGULATOR

LINE REGULATION:(RL is constant)

S.NO Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts

LOAD REGULATION: (Viis Constant)

S.NO Load Resistance, RL in Ohms Regulated DC output, VO in Volts

2.FOR NEGATIVE VOLTAGE REGULATOR

LINE REGULATION:(RL is constant)

S.NO Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts

LOAD REGULATION: (Vi is constant)

S.NO Load Resistance, RL in Ohms Regulated DC output, VO in Volts

3. FOR LOW VOLTAGE REGULATORLINE REGULATION: (RL is constant)

S.No Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts

LOAD REGULATION: (Vi is Constant)

S.No Load Resistance, RL in Ohms Regulated DC output, VO in Volts

4. FOR HIGH VOLTAGE REGULATOR

LINE REGULATION: (RL is constant)

S.No Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts

LOAD REGULATION: (Vi is constant)

S.No Load Resistance, RL in Ohms Regulated DC output, VO in Volts

EXPECTED WAVE FORMS

Fig.3. Line Regulation

Fig.4. Load Regulation

EXPECTED WAVE FORMS

Figure.3. Line Regulation For 78XX

Figure.4. Load Regulation for 78XX


Figure.5. Line Regulation for 79XX


RESULT:

Low and high voltage regulators using IC 723 were constructed and studied. Also the line and load regulations of the low & high voltage regulators are verified.Hence constructed and studied the 3-terminal fixed voltage regulator using IC 78XX and 79XX series &also the line regulation and load regulation of them are verified.

REVIEW QUESTIONS:

1. Design a high voltage and low voltage regulator using IC 723.2. Design a series regulated power supply to provide a nominal output voltage of 20 V, at

IL = 1.2 A. Given Vi = 40 ± 5 V, r0 = 15 Ω, Rz = 10 Ω, Iz = 15 mA, IC2 = 12 mA, hie2 = 600 Ω. hfe2 = 300. IL = 10 mA.

3.Design a regulated power supply using 3-terminal I.C. to give V0 = + 5 V. I0 = 0.6 A, Vin

= 12 VDC, TA = 60°C.4.Design a power supply using 3-terminal I.C. regulator to give + 5 V output at 400 μA at

30°C.5.Using I.Cs, design a regulated power supply to give output voltage, which is adjustable

from 1.2 V to 12 V. IL is to be 0.5 A, TA = 35°C.6. Design a regulated power supply using 3-terminal I.C. to give V0 = + 5 V. I0 = 0.6 A, Vin

= 12 VDC, TA = 60°C.7. Design a power supply using 3-terminal I.C. regulator to give + 5 V output at 400 μA at

30°C.8. Using I.Cs, design a regulated power supply to give output voltage, which is adjustable

from 1.2 V to 12 V. IL is to be 0.5 A, TA = 35°C.9. Design a current source using 7805 to supply a load current of 0.6 A, to drive a load of

20 Ω.

10. Design a voltage regulator using 78XX regulator to get a voltage output of 15V.

OUTCOMES:

1. Design of regulator and the concepts of stabilizers will be known to the students.2. Usage of IC 7805, IC 7905, and IC 723 which are fixed positive, fixed negative and

variable voltage regulators respectively will be known.3. After performing this experiment student will be able design their own regulator for

their mini project circuits as per their requirements.

PART – B

DIGITAL ICS(HDL Coding and Simulation using Active HDL 8.1/Xilinx ISE 9.2i)

1.Adder and Subtractor2. Parity generator.3. Code converters4. Comparator5. Decoders and Encoders.6. Multiplexers and De-multiplexers.7. Flip-flops.8. Counters.9. Shift Registers.10. Random Access Memory (RAM).

PART-B EXPERIMENT NO: 1

DESIGN OF ADDER AND SUBTRACTOR USING VERILOG HDL

PRELAB:

1. Complete idea about the logic diagram and truth table of adder and Subtractor.2. Immense knowledge about the structure of Verilog design module and pc installed

with cadence NC launch Tool.

OBJECTIVE:

To design the following adder and Subtractor in Verilog HDL

1. Half adder2. Full adder3. Half Subtractor4. Full Subtractor5.4-Bit binary adder

SIMULATOR TOOL REQUIRED:

PC INSTALLED WITH CADENCE NC LAUNCH TOOL.

DESIGN CONSTRAINTS:

1. Design a half adder and full adder module using gate primitives in verilog. 2. Design a half Subtractor and full Subtractor module in behavior level modeling.3. Design a 4 bit binary adder by instantiating four 1-bit adders using gate primitives.

1. HALF ADDER

BLOCK DIAGRAM:

LOGIC DIAGRAM:

PROGRAM:

module ha ( a,b,s,c);

input a,b;

output s,c;

xor g1 (s,a,b);

and g2 ( c,a,b);

endmodule

2. FULL ADDER

BLOCK DIAGRAM:

LOGIC DIAGRAM:

PROGRAM:

module fa ( a,b,cin,s,co);

input a,b,cin;

output s,co;

wire c1,c2,c3s1;

xor g1 (s1,a,b);

xor g2 (s,s1,cin);

and g3 ( c1,a,b);

and g4 ( c2,b,cin);

and g5 ( c3,a,cin);

or g6(co,c1,c2,c3);

endmodule

HALF SUBTRACTOR

A

B

Difference ‘D’

Borrow ‘Bo’

3. HALF SUBTRACTOR

BLOCK DIAGRAM:

PROGRAM:

module hs (a,b,d,bo);input a,b;output d,bo;regd,bo;always @ (a or b)bo,d=a-b;endmodule

4. FULL SUBTRACTOR

BLOCK DIAGRAM:

PROGRAM:

module mux(a,b,c,d,bo);input a,b,c;output d,bo;regd,bo;always @ (a or b or c)bo,d=(a-b)-c;endmodule

5. 4-BIT BINARY ADDER

BLOCK DIAGRAM:

FULL SUBTRACTOR

A

B

Difference ‘D’

Borrow ‘Bo’C

PROGRAM:

module fourbit_adder( a,b,cin,s,co);

input [3:0]a,b;

input cin;

output [3:0] s;

output c0;

wire c1,c2,c3;

Fa fa1(a[0],b[0],cin,s[0],c1);

Fa fa2(a[1],b[1],c1,s[1],c2);

Fa fa3(a[2],b[2],c2,s[2],c3);

Fa fa4(a[3],b[3],c3,s[3],c0);

endmodule

module Fa( a,b,cin,s,cout);

input a,b,cin;

output s,cout;

wire c1,c2,c3;

xor g1(s,a,b,cin);

and g2 (c1,a,b);

and g3 (c2,b,cin);

and g4 (c3,cin,a);

or g5(cout,c1,c2,c3);

endmodule

PROCEDURE:1. Create a module with required number of variables and mention it’s input/output.2. Write the description of the adder and subtractor.3. Create another module referred as test bench to verify the functionality.4. Follow the steps required to simulate the design and compare the obtained output

with the corresponding truth tableRESULT:

Adder and Subtractor are designed using different styles of Verilog and the results were verified using the cadence simulator

REVIEW QUESTIONS:

1. Design the 4 bit binary Subtractor using behaviour design in Verilog

2. Design a BCD adder and write the Verilog code for the same in data flow level of modelling

3. Design a adder /Subtractor circuit and write the Verilog for it in behaviour level of modelling

OUTCOMES:

After completion of this experiment,

1. Student will have clear idea of different styles of designing a module in Verilog.2. Student will be familiar with the gate level architecture of adders /subtractors by

synthesizing in pc installed with cadence NC launch Tool.3. Students will be able to design adders and Subtractor for ‘N’ number of bits.


DESIGN OF PARITY GENERATOR VERILOG HDLPRELAB:

1. Complete idea about the logic diagram and truth table of Parity generator.2. Immense knowledge about the structure of Verilog design module and cadence tool.

OBJECTIVE:

To design the following code convertors Verilog HDL

1. 4 bit binary to gray code converter2. 4-bit gray to binary code converter



DESIGN CONSTRAINTS:

Design Parity generator in gate modelling in Verilog.

LOGIC DIAGRAM:

ODD PARITY GENERATOR

TRUTH TABLE:

PROGRAM:

module odd_pa(a,p);

input[3:0] a;

output p;

wire a1,a2;

p

xor(a1,a[0],a[1]);

xor(a2,a[2],a1);

not(p,a2);

endmodule

PROCEDURE:1. Create a module with required number of variables and mention it’s input/output.2. Write the description of the parity generators.3. Create another module referred as test bench to verify the functionality.4. Follow the steps required to simulate the design and compare the obtained output

with the required one.

RESULT:Odd parity generator is designed using different styles of Verilog and the results were verified using the cadence simulator.

REVIEW QUESTIONS:

1. Design even parity generator using behaviourmodelling in Verilog.2. Design the parity checker using behaviourmodelling in Verilog.

OUTCOMES:

After completion of this experiment student will be familiar with the gate level architecture of parity generator synthesizing in cadence tool.


DESIGN OF CODE CONVERTER USING VERILOG HDL PRELAB:

1. Complete idea about the logic diagram and truth table of code convertors.2. Immense knowledge about the structure of Verilog design module and cadence tool.

OBJECTIVE:

To design the following code convertors Verilog HDL

1. 4 bit binary to gray code converter2. 4-bit gray to binary code converter



DESIGN CONSTRAINTS:

1. Design binary to gray code convertor in behaviourmodelling in Verilog. 2. Design gray to binary code convertor in behaviourmodelling in Verilog.

LOGIC DIAGRAM:

1. BINARY TO GRAY CODE CONVERTER

2. GRAY TO BINARY CODE CONVERTER

TRUTH TABLE

PROGRAM

module btog (b, g);

input [3:0] b;

output [3:0] g;

assign g [3] = b [3];

xor (g[2], b[2], b[3]);

Binary code(B3B2B1B0)

Gray Code(G3G2G1G0)

0000 00000001 00010010 00110011 00100100 01100101 01110110 01010111 01001000 11001001 11011010 11111011 11101100 10101101 10111110 10011111 1000

xor (g[1], b[3], g[2]);

xor (g[0], b[4], g[1]);

endmodule

GRAY TO BINARY CODE CONVERTER

module gtob (b, g);

input [3:0] g;

output [3:0] b;

assign b [3] = g [3];

xor (b[2], g[2], g[3]);

xor (b[1], g[1], b[2]);

xor (g[0], b[1], g[2]);

endmodule

PROCEDURE:1. Create a module with required number of variables and mention it’s input/output.2. Write the description of the code converters.3. Create another module referred as test bench to verify the functionality.4. Follow the steps required to simulate the design and compare the obtained output

with the required one.

RESULT:

Code converter is designed using verilog and the results were verified using the cadence simulator

REVIEW QUESTIONS:1. Design and implement a synchronous 3 – bit up/down counter using J-K flip-flops.2. Implement a ring counter.3. Implement a Johnson counter.4. Design a 4-bit ripple counter and verify its functionality.

OUTCOMES

After completion of this experiment student will be familiar with the gate level architecture of code converters synthesizing in cadence tool.


DESIGN OF MAGNITUDE COMPARATOR USING VERILOG HDL

PRELAB

1. Complete idea about the logic diagram and truth table of 4 bit magnitude comparator2. Immense knowledge about the structure of verilog design module and pc installed

with cadence NC launch Tool

OBJECTIVE

To design 4 bit magnitude comparator in verilog HDL

SIMULATOR TOOL REQUIRED


DESIGN CONSTRAINTS

Design 4 bit magnitude comparator module using data flow modelling in Verilog.

BLOCK DIAGRAM

PROGRAM

module comp (a_gt_b,a_lt_b,a_eq_b,a,b);

input [3:0] a,b;

output a_gt_b,a_lt_b,a_eq_b;

assign a_gt_b=(a>b);

assign a_lt_b=(a<b);

assign a_eq_b=(a==b);

endmodule

PROCEDURE:1. Create a module with required number of variables and mention it’s input/output.2. Write the description of the magnitude comparator.3. Create another module referred as test bench to verify the functionality.4. Follow the steps required to simulate the design and compare the obtained output

with the required one.RESULT:

4 bit magnitude comparator is designed using verilog and the results were verified using the cadence simulator

REVIEW QUESTIONS:

1. Design 4 bit magnitude comparator using gate level primitives2. Design 2bit magnitude comparator using behavioral level primitives

OUTCOMES:


1. student will be familiar with the gate level architecture of magnitude comparator by synthesizing in pc installed with cadence NC launch Tool.

2. Students will be able to design for magnitude comparator ‘N’ number of bits.


DESIGN OF DECODERS AND ENCODERS USING VERILOG HDL

PRE LAB

1. Complete idea about the logic diagram and truth table of decoders and encoders.2. Immense knowledge about the structure of verilog design module and pc installed


OBJECTIVE

To design the following decoders and encoders in verilog HDL

1. 2-4 Decoder2. 8-3 Encoder



DESIGN CONSTRAINTS

1. Design 2 -4 decoder module using behaviourmodelling in Verilog. 2. Design 8-3 encoder using behaviour level modelling and gate level modelling.

BLOCK DIAGRAM

1. 2-4 DECODER

PROGRAM

module decoder (a,b,d);

input a,b;

output[3:0]d;

reg[3:0]d;

always @(a or b)

begin

if(a==0&&b==0)

d<=4’b0001;

else if(a==0&&b==1)

d<=4’b0010;

else if(a==1&&b==0)

d<=4’b0100

else

d<=4’b1000

end

endmodule

2. 8-3 ENCODER

TRUTH TABLE

INPUTS OUTPUTSD0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q20 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 10 0 0 0 0 1 0 0 0 1 00 0 0 0 1 0 0 0 1 1 10 0 0 1 0 0 0 0 1 0 00 0 1 0 0 0 0 0 1 0 10 1 0 0 0 0 0 0 1 1 01 0 0 0 0 0 0 0 1 1 1

PROGRAM

module encoder(d,q);

input[7:0]d;

output[3:0]q;

reg[3:0]q;

always @(d)

case(d)

8’b00000001:q=3’b000;

8’b00000010:q=3’b001;

8’b00000100:q=3’b010;

8’b00001000:q=3’b011;

8’b00010000:q=3’b100;

8’b00100000:q=3’b101;

8’b01000000:q=3’b110;

8’b10000000:q=3’b111;

default:q=3’bxxx;

endcase

endmodule

PROCEDURE1. Create a module with required number of variables and mention it’s input/output.2. Write the description of the decoder and encoder.3. Create another module referred as test bench to verify the functionality.4. Follow the steps required to simulate the design and compare the obtained output

with the corresponding truth table.

RESULT:

Decoders and decoder using different styles of verilog and the results were verified using the cadence simulator.

REVIEW QUESTIONS:

1. Implement 3x8 decoder using 2x4 decoder and additional logic. 2. Construct a 4x16 decoder using two 3x8 decoder and additional logic. Show the Schematic diagram neatly?3. Design 2-to-4 decoder using only NOR gates.4. Construct a 5 x 32 decoder with four 3x 8 decoders with enable and one 2 x 4

Decoder5. Write a Verilog code to implement a 8x3 Priority Encoder?6. Write a Verilog code to implement Decimal-to-BCD Encoder?OUTCOMES:


1. Student will be familiar with the gate level architecture of decoders and decoders by synthesizing in pc installed with cadence NC launch Tool.

2. Students will be able to design decoders and encoders for ‘N’ number of bits.


DESIGN OF MULTIPLEXER and DEMULTIPLEXER USING VERILOG HDL

PRELAB

1. Complete idea about the logic diagram and truth table of multiplexers and demultiplexers

2. Immense knowledge about the structure of Verilog design module and pc installed with cadence NC launch Tool

OBJECTIVE

To design the following multiplexer and demultiplexer in Verilog HDL

1. 8 to1 Multiplexers 2. 1 to 4 De multiplexers



DESIGN CONSTRAINTS

1. Design 8 to 1 multiplexer module using behaviourmodelling in Verilog. 2. Design 1 to 4 De multiplexer using behaviour level modelling and gate level

modelling.

1. 8 to1 MULTIPLEXERS

BLOCK DIAGRAM

PROGRAM

module mux (d,sel,y);

input [7:0]d;

input[3:0]sel;

output d;

reg d;

always @(sel or d)

case (sel)

3’b000:y=d[0];

3’b001:y=d[1];

3’b010:y=d[2];

3’b011:y=d[3];

3’b100:y=d[4];

3’b101:y=d[5];

3’b110:y=d[6];

3’b111:y=d[7];

default:y=3’bxxx;

endcase

endmodule

2. 1 TO 4 DEMULTIPLEXER

BLOCK DIAGRAM

PROGRAM

module demux(x,c,y);

input x;

input[1:0]c

output[3:0]y;

reg[3:0]y;

always @(x or c)

case(c)

2’b00:y[0]=x;

2’b01: y[1]=x;

2’b10: y[2]=x;

2’b11: y[3]=x;

default:y=4’bxxxx;

endcase

endmodule

PROCEDURE1. Create a module with required number of variables and mention it’s input/output.2. Write the description of the multiplexer and demultiplexer.3. Create another module referred as test bench to verify the functionality.4. Follow the steps required to simulate the design and compare the obtained output

with the corresponding truth tableRESULT

Multiplexers and Demultiplexers are designed using Verilog and the results were verified using the cadence simulator

REVIEW QUESTIONS

1. Implement a full adder with two 4x1 multiplexers.2. Implement a full subtractor with two 4x1 multiplexers.3. Realize 8x1 mux using 4x1 multiplexer. 4. Implement 2 to 4 decoder using 1x4 demux

OUTCOMES


1. Student will be familiar with the gate level architecture of multiplexers and demultiplexers by synthesizing in pc installed with cadence NC launch Tool.

2. Students will be able to design for multiplexers and demultiplexers ‘N’ number of bits.


DESIGN OF FLIPFLOPS USING VERILOG HDL PRELAB:

1. Complete idea about the logic diagram and truth table of different types of flip-flops.2. Immense knowledge about the structure of Verilog design module and pc installed


OBJECTIVE:

To design the following flip flop in Verilog HDL

1. SR flip-flop2. JK flip-flop3. T flip-flop4. D flip-flop



DESIGN CONSTRAINTS:

Design different types of flip-flop module using behaviourmodelling in Verilog.

BLOCK DIAGRAM:1. SR FLIP-FLOP

PROGRAM:

module srff (q,s,r,clk);

input s,r,clk;

output q;

reg q;

always @(posedgeclk)

begin

if(s==0&&r==0)

q=q;

else if(s==0&&r==1)

q=1’b0;

else if(s==1&&r==0)

q=1’b1;

else

q=1’bz;

endmodule

2. JK FLIP-FLOP:

BLOCK DIAGRAM:

PROGRAM:

module jkff (q,j,k,clk);

input j,k,clk;

output q;

reg q;


begin

if(j==0&&k==0)

q=q;

else if(j==0&&k==1)

q=1’b0;

else if(j==1&&k==0)

q=1’b1;

else

q=~q;

endmodule

3. T FLIP-FLOP:

BLOCK DIAGRAM:

PROGRAM:

module tff (q,t,clk);

input t,clk;

output q;

reg q;


q=~t;

endmodule

4. D FLIP-FLOP:

BLOCK DIAGRAM:

PROGRAM:

module dff (q,d,clk);

input d,clk;

output q;

reg q;


q=d;

endmodule

PROCEDURE:1. Create a module with required number of variables and mention it’s input/output.2. Write the description of the flip-flops.3. Create another module referred as test bench to verify the functionality.4. Follow the steps required to simulate the design and compare the obtained output

with the corresponding truth table

RESULT:

Different types of flip-flops are designed using verilog and the results were verified using the cadence simulator

REVIEW QUESTIONS:

1. Convert a given J-K flip-flop in to a D flip-flop using additional logic if necessary?2. Convert a given J-K flip-flop in to a T flip-flop using additional logic if necessary?3. Convert a given D flip-flop in to a T flip-flop using additional logic if necessary?4. Implement asynchronous reset JK FF.

OUTCOMES:

After completion of this experiment student will be familiar with the gate level architecture of different types of flip-flop by synthesizing in pc installed with cadence NC launch Tool


DESIGN OF COUNTERS USING VERILOG HDL PRELAB:

1. Complete idea about the logic diagram and truth table of decade counter.2. Immense knowledge about the structure of Verilog design module and cadence tool.

OBJECTIVE:

To design decade counter in Verilog HDL



DESIGN CONSTRAINTS:

Design decade counter in behaviourmodelling in Verilog.

BLOCK DIAGRAM:

TRUTH TABLE:

PROGRAM:

module dectr(clk, en, rst, cnt);

input clk, en, rst;

output [3:0] cnt;

reg [3:0] cnt;

always@ (posedgeclk)

if (rst)

cnt<= 4'b0;

else if (en)

cnt<= cnt == 9? 0: (cnt + 1'b1);

endmodule

PROCEDURE:1. Create a module with required number of variables and mention it’s input/output.2. Write the description of the decade counter.

3. Create another module referred as test bench to verify the functionality.4. Follow the steps required to simulate the design and compare the obtained output

with the corresponding truth tableRESULT:

Decade counter is designed using Verilog and the results were verified using the cadence simulator

REVIEW QUESTIONS:1. Design and implement a synchronous 3 – bit up/down counter using J-K flip-flops.2. Implement a ring counter.3. Implement a Johnson counter.4. Design a 4-bit ripple counter and verify its functionality.

OUTCOMES

After completion of this experiment student will be familiar with the gate level architecture of decade counter synthesizing in cadence tool


DESIGN OF SHIFT REGISTERS USING VERILOG HDL PRELAB

1. Complete idea about the logical operation of shift registers.2. Immense knowledge about the structure of Verilog design module and cadence tool.

OBJECTIVE

To the following shift register using Verilog HDL.



DESIGN CONSTRAINTS

1. Design serial in serial out shift register in behaviourmodelling in Verilog. 2. Design universal shift register in behaviourmodelling.

BLOCK DIAGRAM

1. Serial in serial out shift register

2. UNIVERSAL SHIFT REGISTER

PROGRAM

1. SERIAL IN SERIAL OUT SHIFT REGISTER

module shift (CLK, SI, SO); input CLK,SI; output SO; reg [7:0] tmp; always @(posedge CLK) begin tmp = tmp<< 1; tmp[0] = SI; end assign SO = tmp[7]; endmodule

2. UNIVERSAL SHIFT REGISTER

module shift(c,si,lr,so,clk)input si,lr,clk;output so;always @(posedgeclk)begin if(lr==1’b0)begintmp=tmp[6:0],siendelsebegintempsi,tmp[6:0];endassign po=temp;

PROCEDURE:1. Create a module with required number of variables and mention it’s input/output.2. Write the description of the shift register.3. Create another module referred as test bench to verify the functionality.4. Follow the steps required to simulate the design and compare the obtained output with

the corresponding truth table.

RESULT:

Decade counter is designed using Verilog and the results were verified using the cadence simulator

REVIEW QUESTIONS:1. Design parallel in parallel out shift register using behaviourmodelling in Verilog.2. Design parallel in serial out shift register using behaviourmodelling in Verilog.

OUTCOMES:

After completion of this experiment student will be familiar with the gate level architecture of shift registers synthesizing in cadence tool.


DESIGN OF SHIFT REGISTERS USING VERILOG HDL PRELAB:

1. Complete idea about the logical operation of shift registers.2. Immense knowledge about the structure of Verilog design module and cadence tool.

OBJECTIVE:

To the following shift register using Verilog HDL.



DESIGN CONSTRAINTS:

1.Design serial in serial out shift register in behaviourmodelling in Verilog. 2.Design universal shift register in behaviourmodelling.

BLOCK DIAGRAM:


2. Universal shift register

PROGRAM


module shift (CLK, SI, SO); input CLK,SI; output SO; reg [7:0] tmp; always @(posedge CLK) begin tmp = tmp<< 1; tmp[0] = SI; end assign SO = tmp[7]; endmodule

2. Universal shift register

module shift(c,si,lr,so,clk)

input si,lr,clk;output so;always @(posedgeclk)begin if(lr==1’b0)begintmp=tmp[6:0],siendelsebegintempsi,tmp[6:0];endassign po=temp;

PROCEDURE:1. Create a module with required number of variables and mention it’s input/output.2. Write the description of the shift register.3. Create another module referred as test bench to verify the functionality.4. Follow the steps required to simulate the design and compare the obtained output

with the corresponding truth table RESULT:

Shift register is designed using Verilog and the results were verified using the cadence simulator

REVIEW QUESTIONS:1. Design parallel in parallel out shift register using behaviourmodelling in Verilog.2. Design parallel in serial out shift register using behaviourmodelling in Verilog.

OUTCOMES:



DESIGN OF RAM USING VERILOG HDL PRELAB:

1. Complete idea about the Random access memory.2. Immense knowledge about the structure of Verilog design module and cadence tool.

OBJECTIVE:

To design a 16*5 Random Access Memory (RAM).

DESIGN CONSTRAINTS:

Design a 16*5 Random Access Memory (RAM) in Behavioural model.

BLOCK DIAGRAM:

TRUTH TABLE:

PROGRAM:

RAM USING BEHAVIORAL MODEL:

module ram_lab(clk,wr,rd,addr,data_in,data_out);

input clk;

input wr;

input rd;

input[3:0] addr;

input[4:0] data_in;

addr datain clk wr rd dataout

0000 0000 0 1 0 xxxxx

0001 0001 0 1 0 xxxxx

0010 0010 0 1 0 xxxxx

0011 0011 0 1 0 xxxxx

0100 0100 0 0 0 xxxxx

0101 0101 0 0 0 xxxxx

0110 0110 0 0 0 xxxxx

0111 0111 0 0 0 xxxxx

0000 1000 0 0 1 1000

0001 1001 0 0 1 1001

0010 1010 0 0 1 1010

0011 1011 0 0 1 1011

0100 1100 0 0 0 1100

0101 1101 0 0 0 1101

0110 1110 0 0 0 1110

0111 1111 0 0 0 1111

output[4:0] data_out;

reg [4:0] data_out;

reg [4:0] mem[7:0];

always@(posedgeclk)

begin

if(wr)

begin

mem[addr] <= data_in;

end

end

always@(posedgeclk)

begin

if(rd)

begin

data_out<= mem[addr];

end

end

endmodule

PROCEDURE:

1. Create a module with required number of variables and mention it’s input/output.2. Write the description of the Ram.3. Create another module referred as test bench to verify the functionality.4. Follow the steps required to simulate the design and compare the obtained output

with the corresponding truth table RESULT:

RAM is designed using Verilog and the results were verified using the cadence simulator.

OUTCOMES:


IC Applications lab Outcomes:

After completing this course the student must demonstrate the knowledge and ability to:

1. An ability to use an Operational Amplifier in almost all the contests of electronic circuit for implementing various mathematical operations will be known.

2. To design and practically implement the linear applications such as adder, subtractor, integrator and differentiator using Op-Amp.

3. To design and practically implement thenonlinear applications such as schmitt trigger, RC and Wein bridge oscillator using Op-Amp.

4. Able to design multivibratorsfor various timing using IC 555 timer.5. Able to design a sine to square wave converter using IC 555 timer.6. Practically design of real time applications of Analog and Digital ICs will be known.7. Designing of the Digital circuits with the help of Verilog language in Cadence tool will

be known.8. Able to verify/show operation of various Combinational and Sequential digital circuits

will be known.9. At the end of this lab students will be in a position to build small projects using analog

ICs such as IC741, IC555 and IC 565.10. At the end of this lab students will be in a position to build small projects on the

digital concepts using Verilog language in Cadence tool.

Documents

ICA LAB MANUAL - vardhamaneee2k12.files.wordpress.com€¦ · Web viewIC Applications lab Objectives: ... Immense knowledge of Verilog coding language will be obtained to implement