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VALLIAMMAI ENGINEERING COLLEGE

SRM Nagar, Kattankulathur – 603 203

DEPARTMENT OF

ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK

VI SEMESTER

EC6601 – VLSI Design

Regulation – 2013

Academic Year 2018 – 19

Prepared by

Mr. S. Senthilmurugan, Assistant Professor/ECE

Mr. A. Pandian, Assistant Professor/ECE

Mr. M. Selvaraj, Assistant Professor/ECE

Ms. S. Abirami, Assistant Professor/ECE

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VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur – 603 203.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK

SUBJECT : EC6601 – VLSI Design

SEMESTER/YEAR : VI / III

UNIT I – MOS TRANSISTOR PRINCIPLE

NMOS and PMOS transistors, Process parameters for MOS and CMOS, Electrical properties of CMOS circuits and device modelling, Scaling principles and fundamental limits, CMOS inverter scaling, propagation delays, Stick diagram, Layout diagrams.

PART - A

Q. No

Questions BT

Level Competence

1. What is the need for demarcation line? BTL 1 Remembering

2. Compare NMOS and PMOS transistor. BTL 4 Analyzing

3. State propagation delay of CMOS inverter. BTL 1 Remembering

4. Mention the different types of scaling principle. BTL 2 Understanding

5. Why NMOS device conducts strong zero and weak one? BTL 3 Applying

6. Describe the lambda based design rules used for layout. BTL 2 Understanding

7. Demonstrate the stick diagram with an example. BTL 3 Applying

8. Explain the hot carrier effect. BTL 4 Analyzing

9. Draw the DC transfer characteristics of CMOS inverter. BTL 3 Applying

10. Name the different operating modes of transistor? BTL 1 Remembering

11. Classify SPICE models for MOS transistor. BTL 4 Analyzing

12. Outline the steps involved in IC fabrication? BTL 1 Remembering

13. Discuss the limitations of the constant voltage scaling. BTL 2 Understanding

14. Define body effect and write the threshold equation including the body effect.

BTL 1 Remembering

15. Design a 3 input NAND gate. BTL 6 Creating

16. List out second order effects of MOS transistor. BTL 1 Remembering

17. Determine whether an NMOS transistor with a threshold voltage of 0.7v is operating in the saturation region if GSV=2v and DSV=3v.

BTL 5 Evaluating

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18. Summarize the equation for describing the channel length modulation effect in NMOS transistor.

BTL 2 Understanding

19. Justify the tunneling current is higher for NMOS transistors than PMOS transistors with silica gate?

BTL 5 Evaluating

20. Consider the NMOS transistor in 180nm process with a nominal threshold voltage of 0.4v and doping level of 8x1017cm-3. Propose the body voltage.

BTL 6 Creating

PART - B

1. Illustrate with necessary diagrams Electrical properties of MOS

transistor in detail. (13)

BTL 4 Analyzing

2. Describe the CMOS inverter and Derive the DC characteristics. (13) BTL 2 Understanding

3. Narrate in detail about the dynamic behaviour of MOSFET transistor

with neat diagram. (13) BTL 3 Applying

4.

i) Derive the drain current of MOS device in different operating regions.

(8)

ii) With neat diagram formulate the n-well and channel formation in

CMOS process. (5)

BTL 6 Creating

5. Mention in detail about second order effects in MOS transistor. (13) BTL 2 Understanding

6.

Summarize the following:

i) CMOS process enhancements (8)

ii) Layout design rules. (5)

BTL 2 Understanding

7.

i) Examine the equation for threshold voltage of a MOS transistor in

terms of flat band voltage using necessary explanations and derivations.

(8)

ii) State the step by step derivation of threshold voltage equation of

NMOS transistor with and without body effect. (5)

BTL 1 Remembering

8.

i) Explain the design techniques that are used for large fan-in devices to

reduce delay (8)

ii) Evaluate the principle of SOI technology with neat diagram and list

out its advantages and disadvantages. (5)

BTL 5

Evaluating

9.

i) Draw the small signal model of device during cut-off, linear and

saturation region. (8)

ii) Examine a brief note on CMOS fabrication steps with necessary

diagram. (5)

BTL 4 Analyzing

10.

i) Draw the stick diagram and layout diagram using the function

DCBAY ).( of CMOS compound gate. (8)

ii) Label the necessary layout diagram for the design of Universal gates.

(5)

BTL 1 Remembering

11.

i) Analyze the different steps involved in n-well CMOS fabrication process with neat diagrams. (8) ii) Explain the noise margin for a CMOS inverter. (5)

BTL 4 Analyzing

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12.

i) Construct the design rules for a CMOS inverter, in detail with a neat layout. (8) ii) Apply the mathematical equations that can be used to model the drain current and diffusion capacitance of MOS transistors. (5)

BTL 3 Applying

13.

i) List out the goals of CMOS technology scaling. Explain how common electric field scaling is superior than constant voltage scaling. (7) ii) Derive the expression to obtain the minimum delay through the chain of CMOS inverter. (6)

BTL 1 Remembering

14.

i) Define and derive the trans conductance of NMOS transistor. (8) ii) Write down the equations of the small signal model of an NMOS transistor. (5)

BTL 1 Remembering

PART – C

1. With necessary illustrations explain the layout design rules and draw the layout diagram for four input NAND and NOR gate. (15) BTL 5 Evaluating

2. Explain in detail about the need of scaling, scaling principles and effect of scaling on MOSFET device parameters. (15) BTL 5 Evaluating

3.

i. Derive an expression for Vin of a CMOS inverter to achieve the condition Vin=Vout. What should be the relation for βn=βp. (10)

ii. Explain the latch up conditions in CMOS circuits. (5) BTL 6 Creating

4.

Consider the NMOS transistor in a 180nm process with a nominal threshold voltage of 0.4V and doping level of 8 X 1017 cm-3. The body of the transistor is tied to ground with a substrate contact. How much the threshold change at room temperature if the source is at 1.1V instead of 0V? ε si=11.7 X 8.85x10-14F/cm. (15)

BTL 6 Creating

UNIT II – COMBINATIONAL LOGIC CIRCUITS

Examples of Combinational Logic Design, Elmore’s constant, Pass transistor Logic, Transmission gates, static and dynamic CMOS design, Power dissipation – Low power design principles.

PART – A

Q. No

Questions BT

Level Competence

1. Describe path logical effort. BTL 1 Remembering

2. List the methods to reduce dynamic power dissipation. BTL 1 Remembering

3. Calculate logical effort and parasitic delay of n input NOR gate. BTL 3 Applying

4. Distinguish between static and dynamic CMOS design. BTL 2 Understanding

5. Explain pass transistor logic. BTL 4 Analyzing

6. Design an AND gate using pass transistor. BTL 6 Creating

7. Justify why the interconnect increase the circuit delay. BTL 4 Analyzing

8. Define critical path. BTL 1 Remembering

9. What is Elmore constant? BTL 1 Remembering

10. State the advantages of transmission gates. BTL 4 Analyzing

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11.

Determine the discharge time of the circuit shown in below figure when switch A is closed. Assume CL and internal capacitances C1 and C2 are charged initially. Let CL=C1=C2=C.

BTL 5 Evaluating

12. Implement a 2:1 MUX using pass transistor. BTL 6 Creating

13. Realize X=B+C and Y=(A(B+C))using multiple output domino stages. BTL 1 Remembering

14. Summarize the expression for electrical effort of logic circuits. BTL 2 Understanding

15. Illustrate the method for reducing energy consumption of a logic circuit. BTL 3 Applying

16. Discuss the advantages of power reduction in CMOS circuits. BTL 2 Understanding

17. Point out the factors that cause static power dissipation in CMOS circuits.

BTL 2 Understanding

18. Mention the sources of power dissipation.

BTL 1 Remembering

19. Draw the pseudo NMOS logic gate. BTL 3 Applying

20. If load capacitance increases, What will happen to CMOS power dissipation?

BTL 5 Evaluating

PART – B

1.

Analyze the following combinational circuits using the CMOS logic: i) Two input NOR gate. (3) ii) Parity generator (3) iii) Two input NAND gate. (3) iv) Multiplexers (4)

BTL 4

Analyzing

2.

Describe in detail about i) Delay estimation. (5) ii) Logical effort. (4) iii) Transistor sizing. (4)

BTL 2 Understanding

3.

With supporting diagrams, give notes on :

i) Static CMOS (4)

ii) Bubble pushing (4)

iii) Compound gates. (5)

BTL 1 Remembering

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4.

i) Investigate the logical expression in the form of basic gates using

CMOS logic, F= AB + CD. (6)

ii) Estimate least delay and determine input capacitance of each stage for

the logic network shown in figure, which may output of the network is

loaded with a capacitance represent the critical path of a more complex

logic block. The output of the network is loaded with a capacitance

which is 5 times larger than the input capacitance of the first gate, which

is a minimum-sized inverter. (7)

BTL 4

BTL 5

Analyzing Evaluating

5.

i) Formulate the expression for minimum possible delay of multistage

logic networks. (6)

ii) Derive the Elmore constant for NAND and NOR gates. (7)

BTL 6

Creating

6.

Illustrate the expressions using Elmore’s RC delay:

i) Effective resistance (6)

ii) Capacitance estimation. (7)

BTL 3 Applying

7.

i) List out the limitation of pass transistor logic. Explain any two

techniques used to overcome the drawback of pass transistor logic

design. (6)

ii) Explain in detail the signal integrity issues in Dynamic logic design.

Propose any two solutions to overcome it. (7)

BTL 2 Understanding

8. Outline the principle of transmission gate using the design of

multiplexer. (13)

BTL 1 Remembering

9.

i) Relate with Necessary Diagrams the principle of Zipper CMOS Logic.

(6)

ii) Implement AND/NAND gates using Dual-Rail Domino Logic. (7)

BTL 1 BTL 3

Remembering Applying

10.

i) Identify the design issues in dynamic CMOS (6)

ii) Recall the factors that should be considered while designing Dynamic

CMOS. (7)

BTL 3 BTL 1

Applying Remembering

11.

Explain the operation of the following along with necessary diagrams

i) Dynamic CMOS Domino (6) ii) NP Domino logic with necessary diagrams. (7)

BTL 4 Analyzing

12.

i) Examine the characteristics of Pseudo-NMOS Circuits with the help of Inverter, NAND and NOR Gates. (6)

ii) Evaluate the different methods of reducing static and dynamic power dissipation in CMOS circuits and Explain in briefly. (7)

BTL4

BTL 5

Analyzing Evaluating

13.

Write short notes on: i)Ratioed Circuits (3) ii)Dynamic CMOS Circuits (3) iii) Keepers (3) iv) Multiple Ouput Dynamic Logic (4)

BTL 1

Remembering

1a

b c

5

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14.

Discuss with necessary diagrams and expressions:

i)Static power dissipation in CMOS circuits (6)

ii)Dynamic power dissipation in CMOS circuits (7) BTL 2 Understanding

PART – C

Q. No.

Questions BT

Level Competence

1.

i) Implement an EXOR gate using CMOS logic. (7)

ii) Evaluate the delay of the fanout-of-4(FO4) inverter. Assume the

inverter is constructed in180nm process with τ=15ps. (8)

BTL 5 Evaluating

2.

i. Draw the static CMOS logic circuit for the following expression (a) Y= ( A.B.C.D) (5) (b) Y= D(A+BC) (5)

ii. Discuss in detail the characteristics of CMOS transmission

gate. (5)

BTL 5 Evaluating

3.

i. Compose the CMOS logic circuit for the Boolean expression Z= [A (B+C) +DE]’ and explain. (8)

ii. Explain about DCVSL logic with suitable example. (7) BTL 6 Creating

4.

i) Write the expression for minimum possible delay of multistage logic networks. (8)

ii) Design and estimate the frequency of n-stage ring oscillator and construct the ring oscillator from an odd number of inverter. (7)

BTL 6 Creating

UNIT III – SEQUENTIAL LOGIC CIRCUITS

Static and Dynamic Latches and Registers, Timing issues, pipelines, clock strategies, Memory architecture and memory control circuits, Low power memory circuits, Synchronous and Asynchronous design.

PART – A

Q.No Questions BT

Level Competence

1. List the advantages of C2MOS logic based register over pass transistor based master slave register.

BTL 1 Remembering

2. Enumerate about NORA CMOS in brief? BTL 1 Remembering

3. Sketch the characteristic curve of meta stable state in static latch. BTL 3 Applying

4. Distinguish between a latch and flip flop. BTL 2 Understanding

5. Classify the sequential elements in reducing the overhead and skew. BTL 4 Analyzing

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6. Define Clock skew BTL 1 Remembering

7. Summarize the operation modes of NORA logic. BTL 2 Understanding

8. Determine the property of clock overlap in the registers. BTL 5 Evaluating

9. What is Klass semi dynamic flip flop? BTL 1 Remembering

10. Recall the methods of sequencing static circuit. BTL 1 Remembering

11. Write about pipelining? BTL 2 Understanding

12. Compare registers and latches. BTL 4 Analyzing

13. Explain simple synchronizer circuit. BTL 4 Analyzing

14. Formulate hold-time problem which would occur, If a data path circuits uses pulsed latches in place of flip flops.

BTL 6 Creating

15. Justify the advantages and applications of self-time pipelined circuits. BTL 5 Evaluating

16. Design a 1-transistor DRAM cell. BTL 6 Creating

17. Illustrate the merits and demerits of 3 T DRAM over 1 T DRAM BTL 3 Applying

18. Give the properties of TSPC. BTL 2 Understanding

19. Why pipelining is need for of sequential circuits? BTL 1 Remembering

20. Draw the schematic of dynamic edge-triggered register. BTL 3 Applying

PART – B

1. Explain the memory architecture and its control circuits in detail. (13)

BTL 4 Analyzing

2. Discuss about CMOS register concept and design master slave triggered register, explain its operation with overlapping period. (13)

BTL 2 Understanding

3. Write about the latches and flip-flops in design methodology of sequential circuit design. (13)

BTL 1 Remembering

4. i) State and explain the Klass semi dynamic flip flops and differential Flip flops. (7) ii) Illustrate the enabled latches and flip flops. (6)

BTL 1 BTL 3

Remembering Applying

5. i) Design a D-latch using transmission gate. (7) ii) Evaluate a 1-bit dynamic inverting and non-inverting register using pass transistor. (6)

BTL 6 BTL 5

Creating Evaluating

6. i) Draw and explain the operation of conventional CMOS pulsed and resettable latches. (7) ii) Estimate about sequencing dynamic circuits. (6)

BTL 3 BTL 5

Applying Evaluating

7.

i) Compare the sequencing in traditional Domino and Skew tolerant Domino circuit with neat diagrams. (7) ii) Elucidate a floating gate transistor and its programming methodology. (6)

BTL 4

BTL 3

Analyzing Applying

8. Describe about memory architecture and memory control circuits. (13)

BTL 2 Understanding

9. Give a brief note on:

i)CMOS S-RAM cell and Dynamic RAM cell. (7) ii) 4T and 6T SRAM cell structures (6)

BTL 1 Remembering

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10.

i) Consider a flip flop built from a pair of transparent latches using non overlapping clocks. Determine the set-up time, hold time and clock-to-Q-delay of the flip flops in terms of the latch timing parameters and tnonoverlap. (7) ii)Design a 2 input CVSL AND/NAND gate and a 3 input CVSL OR/NOR gate. (6)

BTL 4

BTL 6

Analyzing Creating

11. Write Short notes on :

i)True Single phase clocked register (7) ii) NORA- CMOS pipelined latches (6)

BTL 1 Remembering

12. Illustrate with necessary diagrams the design and organization of CAM. (13)

BTL 2 Understanding

13. i) Explain in detail about Low power circuits. (10) ii) Differentiate between synchronous and asynchronous sequential circuits. (3)

BTL 4 Analyzing

14. Demonstrate the maximum and minimum delay constraints needed to design sequential circuits. (13)

BTL 3 Applying

PART – C

1. Discuss about the design of sequential dynamic circuits and its pipelining concept. (15)

BTL 6 Creating

2. Explain the timing basics and clock distribution techniques in synchronous design in detail. (15)

BTL5 Evaluate

3. Elaborate about various static latches and registers. (15) BTL 6 Creating

4. Interpret the operation of Master Slave edge triggered register. (15) BTL5 Evaluating

UNIT IV DESIGNING ARITHMETIC BUILDING BLOCKS

Data path circuits, Architectures for ripple carry adders, carry look ahead adders, High speed adders, accumulators, Multipliers, dividers, Barrel shifters, speed and area trade-off.

PART – A

Q.No Questions BT

Level Competence

1. Obtain the critical path delay of 4 bit ripple carry adder and draw the circuit.

BTL6 Creating

2. Summarize about carry propagation delay. Mention its effect in circuits.

BTL2 Understanding

3. List out the components of Data path BTL 1 Remembering

4. Why is barrel Shifters very useful in the designing of arithmetic circuits?

BTL2 Understanding

5. Interpret a partial product selection table using modified 3-bit booth’s recoding multiplication.

BTL 5 Evaluating

6. What is latency? BTL 1 Remembering

7. Draw the structure of 4 X 4 barrel shifter. BTL 3 Applying

8. List the advantages and disadvantages of full adder design using static CMOS.

BTL 1 Remembering

9. Analyze the concept of Dynamic voltage scaling and list its advantages.

BTL 4 Analyzing

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10. Define Clock gating. BTL 1 Remembering

11. Create a schematic for Sleep transistors used on both supply and ground.

BTL6 Creating

12. Examine the need of VTCMOS BTL 4 Analyzing

13. Give the applications of high speed adder BTL 2 Understanding

14. Outline the inverting property of full adder. BTL 4 Analyzing

15. How to design a high speed adder? BTL 3 Applying

16. Write the full adders output in terms of propagate and generate. BTL 1 Remembering

17. Classify Power optimization techniques for latency and throughput constrained design.

BTL 3 Applying

18. Write the principle of any one fast multiplier? BTL1 Remembering

19. Sketch a Manchester carry gate. BTL2 Understanding

20. Elaborate the Concept of Transmission gate full adder. BTL 5 Evaluating

PART – B

1. i) Describe ripple carry adder and derive the expression for worst case delay. (10) ii) State the features of Carry Bypass adders. (3)

BTL 1 Remembering

2. Examine the concept of carry look ahead adder and discuss its types. (13)

BTL 4 Analyzing

3. Outline the operation of a basic 4 bit adder. Describe the different approaches of improving the speed of the adder. (13)

BTL 1 Remembering

4. Illustrate the concepts of monolithic and logarithmic look ahead adder. (13)

BTL 3 Applying

5. Define shifter and give a short note on i) Barrel shifter. (7) ii) Logarithmic shifter. (6)

BTL 1 Remembering

6.

i) Demonstrate how to reduce the number of generated partial products by half. (7) ii) Identify and explain the concept of Dynamic Voltage Scaling. (6)

BTL3 Applying

7. Compute the efficiency of carry look ahead adder over normal full adder. Give the comparative study of each. (13)

BTL 6 Creating

8. Summarize the methods involved in run time power management. (13)

BTL2 Understanding

9. Evaluate the steps involved in designing an 8 bit Brent-Kung adder.

BTL5 Evaluating

10. Give a note on linear carry select adder. (13) BTL 2 Understanding

11. Examine the operation of :

i)Static CMOS adders. (7) ii)Mirror adder (6)

BTL 4 Analyzing

12. Analyze the operation of booth multiplication with suitable examples. Justify how booth algorithms speed up the multiplication process. (13)

BTL 4 Analyzing

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13. Discuss the data paths in digital processor architectures. (13) BTL 2 Understanding

14. With neat sketch show the principle of operation of two multiplier circuit (13)

BTL 1 Remembering

PART – C

1.

i) Construct 4 X 4 array type multiplier and find its critical path delay. (8) ii) Implement a 4 input and 4 output barrel shift adder using NMOS logic. (7)

BTL5 Evaluating

2. Design a multiplier for 5 bit by 3 bit. Explain its operation and summarize the number of adders. (15)

BTL6 Creating

3. Explain a Modified Booth algorithm with a suitable example. (15)

BTL5 Evaluating

4. Discuss the steps in designing restoring division circuit. (15) BTL6 Creating

UNIT V IMPLEMENTATION STRATEGIES

Full custom and Semi-custom design, Standard cell design and cell libraries, FPGA building block architectures, FPGA interconnect routing procedures.

PART – A

Q. No Questions BT

Level Competence

1. 1. What is role of cell library in ASIC design? BTL 1 Remembering

2. Classify the implementation approaches for digital integrated circuits.

BTL 4 Analyzing

3. List out the advantages and disadvantages of cell based design methodology.

BTL 1 Remembering

4. Narrate about feed-through cells and state their uses. BTL 3 Remembering

5. Interpret the feature Macro cells. BTL 3 Applying

6. Give a note on Tape out of chip. BTL 2 Understanding

7. State the features of full-custom design. BTL 1 Remembering

8. Differentiate between semi-custom and full custom design. BTL 4 Analyzing

9. Describe about standard cell based ASIC design? BTL 1 Remembering

10. Define Fuse based FPGA. BTL 1 Remembering

11. Name the two different types of routing. BTL 2 Understanding

12. Develop an array based architecture used in Altera MAX series. BTL 6 Creating

13. Design a primitive gate array cell. BTL 6 Creating

14. Compare between Xilinx CLB interconnect and Altera LAB interconnect.

BTL 4 Analyzing

15. Summarize the functions of Programmable Interconnect Points in FPGA.

BTL 5 Evaluating

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16. Identify the issues in implementing Boolean functions on array of cells.

BTL 2 Understanding

17. Show the design steps of Semicustom design flow diagram. BTL 5 Applying

18. Illustrate Composition of generic digital processor. BTL 3 Evaluating

19. Outline the steps for ASIC design flow. BTL 2 Understand

20. Write the various ways of routing procedure. BTL 1 Remembering

PART – B

1. (i) List and explain the components that makeup the cell based

design methodology. (8) (ii) Give a short note on programming of PAL. (5)

BTL 1 Remembering

2. Classify the various types of ASIC with neat diagram. (13) BTL 2 Understanding

3. (i)Summarize the Blocks involved in digital processor. (8) (ii)Define and explain the approaches of programmable wiring. (5)

BTL 1 Remembering

4. (i)Illustrate the concepts of Mask programmable arrays. (10) (ii)Identify the components involved in constructing a voltage Output Macrocell. (3)

BTL 3 Applying

5. Explain CLB of Xilinx 4000 architecture. (13) BTL 4 Analyzing

6. Examine the interconnect architectures of

i) (i)Altera Max series. (7) ii) (ii)Xilinx XC40XX series. (6)

BTL 4 Analyzing

7.

(i)Identify and Explain the FPGA block structure along its components. (7) (ii) Mention in detail the techniques involved in Switch box programmable wiring. (6)

BTL 1 Remembering

8. (i)Discuss the types of FPGA routing techniques. (7) (ii)Demonstrate the types of ASICS. (6)

BTL 2 Understanding

9. (i) (i)Design an LUT-Based Logic Cell. (7) (ii) (ii)Elaborate the Classification of prewired arrays. (6)

BTL 6 Creating

10. (i) Compare two types of Macrocells. (6) (ii) Inspect the data paths in digital processor architectures. (7)

BTL 4 Analyzing

11. Draw and explain the building blocks of FPGA. (13) BTL 2 Understanding

12.

(i)Realize the function F=A.B+(B’.C)+D using ACTEL (ACT-1) FPGA. (5) (ii)Draw the flow chart of digital circuit design techniques. (4) (iii) Differentiate between Hazard Macro and Macro. (4)

BTL 3 Applying

13.

Explain the classification of ASIC with necessary block diagram.

(i) Full Custom ASIC (7) (ii) Semi-Custom ASIC (6)

BTL 5 Evaluating

14.

Write short notes on

(i) Xilinx LCA (6) (ii) Altera Max (7)

BTL 1 Remembering

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PART – C

1. Assess the important of CLB, IOB and programmable interconnects of an FPGA device. (15)

BTL 5 Evaluating

2. Design the building blocks of FPGA and explain the different fusing technologies. (15)

BTL 6 Creating

3.

(i) Evaluate the different internal building block architecture of FPGA. (10) (ii)Summarize the routing procedures involved in FPGA Interconnect. (5)

BTL 5 Evaluating

4. Compile the different types of ASIC Architecture with neat diagram. (15)

BTL 6 Creating

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