Upgrade of the TileCAL LVPS System

Upgrade of the TileCAL LVPS System

Gary Drake

Argonne National Laboratory, USA

In Collaboration with

The University of Chicago

CERN

Feb. 25, 2009

ATLAS

Upgrade Workshop

Upgrade of the TileCAL LVPS System ATLAS Upgrade Workshop – G. Drake – Feb. 25, 2009 – CERN

2

Outline of Talk

I. Goals for the LVPS Upgrade

II. Current Plans & Thinking

III. Primary Issues, Critical Decisions, Required R&D

IV. Summary


3

General System Guidelines and Goals for the LVPS System

1. Primary Motivation: Improve radiation hardness of electronics LVPS bricks must be replaced for sLHC environment…

2. Improve Reliability

a. Connectorsi. Reduce number of connections & interconnectsii. Improve reliability and robustness of connectors

b. Implement redundancy to prevent single-point failures

3. Generally reduce complexity of system where possible

4. Reduce numbers of voltages to be generated

5. Eliminate sensitivities to IR drops

6. Eliminate need for tight regulation by LVPS

Use “point-of-load” regulators CERN rad-hard regulators


4

The Current LVPS System Present System Architecture – 2-Stage System

FE CircuitryIn Drawer On Detector

1 per DrawerUSA15

LVPS

Bulk200 VDC

ToOther

Drawers Spl

itter

Box

On Detector1 per 4 DrawersMother Boards

Digitizers

LocalCKTs

LocalCKTs

LocalCKTs

LocalCKTs

Digitizers

HV Dist. System

ToOther SplitterBoxes

Stage 2

Stage 1

200VDC200VDC

+3DIG, +5DIG,-5MB, +5MB,

+15MB, -15HV, +15HV, +5HVAnd Returns

4

6

4

14


5

The Current LVPS System TileCAL LVPS System – 2-stage system

Main Barrel side70m long cable Extended Barrel sides100m long cable

USA15

BULKSUPPLY

3 240 VAC

200 V dc

200 V dc

200 V dc

sp

litte

r bo

xsp

litte

r bo

xsp

litte

r bo

x

Graphic by I. Hruska, B. Palan

CustomLVPS BoxesOne per Drawer256 Total Commercial

24 HPS1 UnitsEach powers 12 fLVPS

200 V dc in,3V, 5V, 15V Out


6

The Current LVPS System

Current fLVPS configuration Power Daisy Chain

Motherboard Motherboard Motherboard Motherboard

DigitizerDigitizer DigitizerDigitizer DigitizerDigitizer DigitizerDigitizer

HV control and distribution board HV control and distribution board

pm

t 3in

1

pm

t3in

1

LVPS

HV Capton Foil

optical Interface

TTC

datato ROD

Power daisy chain

Flex Foils (data,TTC ) BUS

Hartingconnector

12 8 6

6

44 4

144 44 4 4

100100

Graphic by G. Usai, UC


7

The Current LVPS System Current Configuration of LVPS Box

LVPS Box

8 Bricks/Box

+3DIG & Returns

+5DIG & Returns

+5MB & Returns

-5MB & Returns

+15MB & Returns

+5HV & Returns

-15HV & Returns

+15HV & Returns

200 VDC

+3DIGBrick

+5DIGBrick

+5MBBrick

-5MBBrick

+15MBBrick

+5HVBrick

-15HVBrick

+15HVBrick

ELMBMotherBoard

CAN Bus

200VDist.

Board

4

4

8

4

2

2

2

2

10

6

Ground

6

72 pinHarting

Connector

Range of Voltages: 5:1Range of Currents: 62:1

One Basic Brick Design Different Component Values


8

The Proposed New Power Distribution System

New System Architecture – 3-Stage System

FE CircuitryIn Drawer On Detector

1 per Drawer

LVPS

ToOther

Drawers Spl

itter

Box

On Detector1 per 4 Drawers

POLREGs

LocalCKTs

POLREGs

LocalCKTs

POLREGs

LocalCKTs

ToOther SplitterBoxes

Stage 2

Stage 3 - Point-of-Load Regulators

USA15

Bulk200 VDC

Stage 1

200VDC200VDC

+/-10VDC and Returns

4 (8*)

4 (8*)

4 (8*)

* Numbers in parentheses for implementation of redundancy


9

Point of Load Regulators

Work is in progress at CERN to develop rad-hard DC-DC Converter to be used as local point-of-load regulators

– Use one by every chip, or group of chips, depending on current demand– Primary development is for silicon tracker high radiation environment– TileCAL radiation environment is less demanding, so we can piggyback

Some Parameters:– Radiation hard DC-DC converters with air-core inductors– Low drop voltage regulators in 130nm and below– DC-DC buck converter architecture– Vin: +10 ~ +12V, Vout: +1.8 ~ +5V, 6W, 85 – 90% efficiency– Radiation and magnetic field hard

Contact persons: F. Faccio & G. BlanchotMore info http://indico.cern.ch/conferenceDisplay.py?confId=39721

POLREGs

LocalCKTs

We will be testing prototypes as soon as they become available Caveat: Not working on rad-hard negative voltage regulators (yet)…

+/-10VDC


10


The New LVPS System – 3-stage system

Main Barrel side70m long cable Extended Barrel sides100m long cable

USA15

BULKSUPPLY

3 240 VAC

200 V dc

200 V dc

200 V dc

sp

litte

r bo

xsp

litte

r bo

xsp

litte

r bo

x

Modified from Graphic by I. Hruska, B. Palan

CustomLVPS BoxesOne per Drawer256 Total Commercial

24 HPS1 UnitsEach powers 12 fLVPS

200 V dc in,+/- 10V Out New BricksSame Physical SizeNeed new boxes…

Same Infrastructure


11

The Proposed New Power System New Configuration of LVPS Box

+10V & Returns

200 VDC

+10VBrick

+10VBrick

+10VBrick

+10VBrick

-10VBrick

-10VBrick

-10VBrick

-10VBrick

ControlBoard

Control &Monitoring

GBT?

200VDist.

Board

8 (16)

6

Ground

6

(1) or (2*) 64 pinHarting

Connectors

LVPS Box

8 Bricks/Box

+10V & Returns

+10V & Returns

+10V & Returns

-10V & Returns

-10V & Returns

-10V & Returns

-10V & Returns

8 (16)

8 (16)

8 (16)

8 (16)

8 (16)

8 (16)

8 (16)

* Numbers in parentheses for implementation of redundancy

Range of Voltages: 1:-1Range of Currents: 1:1 (2:1)

Two Brick Designs


12


A possible implementation… Star distribution system:

Readout BdService 4 PMTs

Fro

nt

En

d

LVPS200V

Modified from Graphic by G. Usai, UC












HV control& distribution

board

HV control& distribution

board

24 (1 Drawer) 24 (1 Drawer)

PMT

Fro

nt

En

d

PMT

Fro

nt

En

d

PMT

Fro

nt

En

d

PMT

GBT

GBT GBT

OpticalTo USA15

OpticalTo USA15

4 (8*) 4 (8*) 4 (8*) 4 (8*) 4 (8*) 4 (8*)

4 (8*) 4 (8*) 4 (8*) 4 (8*) 4 (8*) 4 (8*)

4 (8*) 4 (8*)

* Numbers in parentheses for implementing redundancy

+/-10V

PMT HV PMT HV

Each of 8 bricks in LVPS Box services 2 (4*) Readout Bds Nearly balanced loads!

Data, Control, & Timing 1 Link/Board


13

How to implement power supply redundancy: Diode OR

– Greater of (Vs1 – Vd1) or (Vs2 – Vd2) provides current to load– Diodes may share if diode IV characteristics are soft, and/or if 2 paths ~match– No need to bin diodes; Only moderate trim of output voltages needed– On average, power supplies will each share half the total load, within window

Power supplies on average operate at half their rated power aids in longevity Each power supply must be capable of providing full power though

Implementing Redundancy

+-

+-

Load

Vd1

Vd2

Vs1Vs2

PCB

Vload

Technique used successfully for CDF Run 1

Need more experience with current system to decide if this is worth it…


14

Monitoring & Control Probably will want to monitor same quantities as presently:

– 8 input voltages– 8 output voltages– 8 input currents– 8 output currents– Temperatures The difference: only 2 sets of quantities, not 8… No longer need to monitor sense lines, if use POL regulators…

Control– No longer need trim control regulators are insensitive to their Vin– Will want method for turning on & off whole boxes– May want method for turning on & off individual bricks…


15

Primary Issues, Critical Decisions, Required R&D Need to choose a system architecture Need to identify and specify all components in the drawer

– Identify voltages needed– Define currents needed Define total voltage, current, and power consumption for drawer

Point-of-Load Regulators– Based on needs, will CERN regulator be sufficient?

• Obtain prototype samples; performance testing; radiation testing• Is there any circuitry that can’t operate within +/-5V?

– What to do about negative voltage regulator• CERN?• Another IC design group?• Commercial vendor?

Preliminary brick component selection– Radiation testing

Decision on implementing redundancy– Experience with current system will be a good guide…


16

Primary Issues, Critical Decisions, Required R&D (Cont.)

Control & monitoring– GBT?

– New ELMB_MB equivalent?

– Custom chip development? Needs more thought & work…

Prototype brick design– Can begin early, with approximate guesses on current & power

– Will need final specs to complete design• Design for factor of 2 capability if implement redundancy• Design for 80% maximum capacity on a single supply

Connector Decisions– Depends on

• Architecture• Currents• Distribution of loads

– Includes power connections, & all internal connections inside box Possibly the most important decision in the project


17

Summary Advocating 3 stage power distribution system

– Stage 1 – bulk 200V in USA15 OK– Stage 2 – LVPS boxes

• New design• +/- 10V only• Tight regulation not important• Advocating balanced loads

– Stage 3 – Point-of-Load regulators• Relying on CERN development for positive voltage regulator• Still need to identify/develop negative voltage regulator

Primary issues needing to be addressed:– System architecture– Drawer electronics design voltages & currents required– Point of load regulators: test CERN design; address negative voltages– Component selection radiation testing– Address need for redundancy– Choose connectors– Prototype development… Testing… FE tests… Vertical Slice Tests…

Documents

Upgrade of the TileCAL LVPS System