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IMPLEMENTATION OF UART IN VERILOG
A Mini project report
Submitted in partial fulfillment of the
Requirements for the award of the degree
Bachelor of Technology
in
ELECTRONICS& COMMUNICATION Engineering
BY
R.Swathi 08QR1A0449 N.Srilatha 08QR1A0440
Under the guidance of
Y.Ramakrishna
H.O.D of ECE Department
DEPARTMENT OF ELECTRONICS AND COMUNICATIONS ENGINEERING
KITE WOMEN’S COLLEGE OF PROFESSIONAL
ENGINEERING SCIENCES (KPSW)
(Approved By AICTE and Affliated to JNTU, HYD)
SHABAD, Ranga Reddy District – 509217, Tel: 08417-279053
DEPARTMENT OF ELECTRONICS AND COMUNICATIONS ENGINEERING
KITE WOMEN’S COLLEGE OF PROFESSIONAL
ENGINEERING SCIENCES
SHABAD, Ranga Reddy District – 509217, Tel: 08417- 279053
DECLARATION BY THE CANDIDATE
I, hereby declare that the Mini project work entitled
IMPLEMENTATION OF UART IN VERILOG is being submitted in partial fulfillment
of the requirements for the award of the Degree BACHELOR OF TECHNOLOGY in
ELECTRONICS AND COMUNICATIONS ENGINEERING
This is a Mini Project report work carried out by me under the guidance of,
Y.Rama krishna H.O.D Professor of of ECE Department and the results embodied
in this project have not been reproduced or copied from any source. The results
embodied in this project have not been submitted to any other University or
Institute for the award of any other Degree or Diploma.
.
DEPARTMENT OF ELECTRONICS AND COMUNICATIONS ENGINEERING
KITE WOMEN’S COLLEGE OF PROFESSIONAL
ENGINEERING SCIENCES
SHABAD, Ranga Reddy District – 509217, Tel: 08417- 279053
CERTIFICATE
This is to certify that the Mini project report entitled
“IMPLEMENTATION OF UART ALGORITHM CODE IN VERILOG” is record of
bonafide work carried out by R.Swathi bearing 08QR1A0411, and is being
submitted in partial fulfillment of the requirements for the award of the degree
BACHELOR OF TECHNOLOGY in ELECTRONICS AND COMUNICATIONS
ENGINEERING
The results of investigations enclosed in this report have been Verified and found
Satisfactory. The results embodied in this project have not been submitted to any
other University or Institute for the award of any other Degree or Diploma.
Internal Examiner Head of the Department
External Examiner
ACKNOWLEDGEMENTS
First and foremost, we express our sincere thanks for the guidance and encouragement
rendered by Y.Rama krishna H.O.D Professor of ECE Department Department of
Computer Science & Engineering & Information Technology, KITE WOMEN’S COLLEGE OF PROFESSIONAL
ENGINEERING SCIENCES, Shabad. We extend our gratitude for his advice and guidance during the
progress of this Mmini-project.
We express my profound gratitude to our indebtedness to our Management for providing
State of the Art Laboratories and Infrastructure.
We wish to express our profound thanks to our Director- Academics Dr. K.S.R.K. Prasad,
KITE, Shabad, for providing necessary facilities to make this mini-project a success.
We thank all the members of Teaching Staff members, and also who have assisted us directly or
indirectly for successful completion of this mini-project.
Finally, we would like to express our sincere gratitude to our Parents who are constantly encouraging us
throughout our life and completion of this mini-project.
UART
ABSTRACT
Serial communications is the process of sending data one bit at one time, sequentially, over a communication channel or computer bus. Serial communications is used for all long haul communications and most computer networks, where the cost of cable and synchronization difficulties make parallel communications impractical. Serial transmission is commonly used with modems and for non-networked communication between computers, terminals and other devices. The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes.
Introduction
UART - Universal Asynchronous Receiver/Transmitter (UART) An integrated circuit used for serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes.
The CPU communicates with the UART by reading or writing one of eight bytes called ports. A computer system normally has more than one UART, so the port addresses depend on the particular UART being accessed. Each UART is associated with a different base address, and a particular port is specified by adding a specific index to that base address. The index for a particular port is independent of the UART, so we can characterize the ports by indices 0 through 7.
Serial Data Transmission
Why is a UART necessary for a computer modem?
A modem is composed of two basic parts, the UART and the analog modulator-demodulator,which is where the term (Modem) comes from. During transmission of data the UART is responsible for taking the data from the host machine and turning it into a serial bit stream that can be sent by the modem over the phone line. During reception of data the UART takes the serial data from the modem and converts it into parallel data that can be used by the host machine.
The parallel side of a UART's usually connected to the bus of a computer. When the computer writes a byte to the UART's transmit data register (TDR), the UARTs will start to transmit it on the serial line. The UART's status register contains a flag bit which the computer can read to see if the UART is ready to transmit another byte. Another status register bit says whether the UART has received a byte from the serial line, in which case the computer should read it from the receive data register (RDR).
The UART's serial connections usually go via separate line driver and line receiver integrated circuits which provide the power and voltages required to drive the serial line and give some protection against noise on the line.
Data on the serial line is formatted by the UART according to the setting of the UART's control register. This may also determine the transmit and receive baud rates if the UART contains its own clock circuits or "baud rate generators".
UART is the most commonly used host controller interface because of following reasons:
If UART is used software overhead is very less Its highly cost effective. Simple way to send data from one system to another system Add functional to applications
1.General usage of UART is : For our purposes, UART is a relatively simple device that illustrates the nature of device controllers (DCs).
2.Interface of UART:A UART acts as the interface between an I/O bus and a serial device, such as a mouse or modem, which communicate with a computer one bit at a time. On a PC, there are two UARTs that connect to the COM1 and COM2 ports on the back of the computer.
3.The job of a UART is to accept bytes of data from the CPU 8 bits at a time (in parallel) and to transmit them one bit at a time (serially) to whatever device is plugged into its connector on the back of the computer. At the same time, it receives data bits serially from the device, which it assembles into bytes that the CPU reads in parallel.
A Universal Asynchronous Receiver and Transmitter (UART) is used for communication with serial input and serial output devices. Serial transmission reduces the cost and complexity of the wirings at the expense of speed, and for many applications this is a desired trade-off.
UART is a chip used to manage computer serial ports, disk drive interrupts, screen refresh cycles, and any other device that requires timing. With a serial port transmission, the UART converts the bytes into serial bits and transmits those bits through an asynchronous transmission, stripping out the start and stop bits for each character. The 16550 chip series is the most commonly used UART.
Transmitting and receiving serial data
UART transmitter controls transmission by fetching a data word in parallel format and directing the UART to transmit it in a serial format. Likewise, the Receiver must detect transmission, receive the data in serial format, strip of the start and stop bits, and store the data word in a parallel format.
Since the UART is asynchronous in working, the receiver does not know when the data will come, so receiver generate local clock in order to synchronize to transmitter whenever start bit is received.
The UART usually does not directly generate or receive the external signals used between different items of equipment. Separate interface devices are used to convert the logic level signals of the UART to and from the external signaling levels. External signals may be of many different forms. Examples of standards for voltage signaling are RS-232, RS-422 and RS-485 from the EIA. Historically, current (in current loops) was used in telegraph circuits. Some signaling schemes do not use electrical wires. Examples of such are optical fiber, IrDA (infrared), and (wireless) Bluetooth in its Serial Port Profile (SPP). Some signaling schemes use modulation of a carrier signal (with or without wires). Examples are modulation of audio signals with phone line modems, RF modulation with data radios, and the DC-LIN for power line communication.
Communication may be "full duplex" (both send and receive at the same time) or "half duplex" (devices take turns transmitting and receiving).
Character framing
Each character is sent as a logic low start bit, a configurable number of data bits (usually 7 or 8, sometimes 5), an optional parity bit, and one or more logic high stop bits. The start bit signals the receiver that a new character is coming. The next five to eight bits, depending on the code set employed, represent the character. Following the data bits may be a parity bit. The next one or two bits are always in the mark (logic high, i.e., '1') condition and called the stop bit(s). They signal the receiver that the character is completed. Since the start bit is logic low (0) and the stop bit is logic high (1) then there is always a clear demarcation between the previous character and the next one.
Asynchronous Serial Transmission:
Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. Instead, the sender and receiver must agree on timing parameters in advance and special bits are added to each word which are used to synchronize the sending and receiving units.
When a word is given to the UART for Asynchronous transmissions, a bit called the "Start Bit" is added to the beginning of each word that is to be transmitted. The Start Bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter. These two clocks must be accurate enough to not have the frequency drift by more than 10% during the transmission of the remaining bits in the word. (This requirement was set in the days of mechanical teleprinters and is easily met by modern electronic equipment.)
After the Start Bit, the individual bits of the word of data are sent, with the Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly the same amount of time as all of the other bits, and the receiver ``looks'' at the wire at approximately halfway through the period assigned to each bit to determine if the bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the receiver will examine the signal to determine if it is a 1 or a 0 after one second has passed, then it will wait two seconds and then examine the value of the next bit, and so on.The sender does not know when the receiver has ``looked'' at the value of the bit. The sender only knows when the clock says to begin transmitting the next bit of the word.
When the entire data word has been sent, the transmitter may add a Parity Bit that the transmitter generates. The Parity Bit may be used by the receiver to perform simple error checking. Then at least one Stop Bit is sent by the transmitter.
When the receiver has received all of the bits in the data word, it may check for the Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is supposed to, the UART considers the entire word to be garbled and will report a Framing Error to the host processor when the data word is read. The usual
cause of a Framing Error is that the sender and receiver clocks were not running at the same speed, or that the signal was interrupted.
Regardless of whether the data was received correctly or not, the UART automatically discards the Start, Parity and Stop bits. If the sender and receiver are configured identically, these bits are not passed to the host.
If another word is ready for transmission, the Start Bit for the new word can be sent as soon as the Stop Bit for the previous word has been sent.Because asynchronous data is “self synchronizing”, if there is no data to transmit, the transmission line can be idle.
Advantages and disadvantages:
Advantages Disadvantages
Asynchronous transmission
Simple, doesn't require synchronization of both communication sides
Cheap, timing is not as critical as for synchronous transmission, therefore hardware can be made cheaper
Set-up is very fast, so well suited for applications where messages are generated at irregular intervals, for example data entry from the keyboard
Large relative overhead, a high proportion of the transmitted bits are uniquely for control purposes and thus carry no useful information
Synchronous transmission
Lower overhead and thus, greater throughput
Slightly more complex
Hardware is more expensive
UART REGISTERS DESCRIPTION
RBR: Receiver buffer register
The Receiver Buffer Register (RBR) contains the byte received if no FIFO is used, or the oldest unread byte with FIFO's. If FIFO buffering is used, each new read action of the register will return the next byte, until no more bytes are present. Bit 0 in the Line Status Register (LSR) can be used to check if all received bytes have been read. This bit will change to zero if no more bytes are present.
THR: Transmitter holding register
Without FIFO buffering, only one character can be stored. Otherwise the amount of characters depends on the type of UART. To check if new information must be written to THR Bit 5 in the Line Status Register (LSR) can be used. Empty register is indicated by the value 1. If FIFO buffering is used, more than one character can be written to the transmitter holding register when the FIFO is empty.
IER: Interrupt enable register
In interrupt driven configuration, the UART will signal each change by generating a processor interrupt. A software routine must be read interrupt signal to handle the interrupt and to check what state change was responsible for it. Interrupt enable register (IER) is used to enable the interrupt.
IIR: Interrupt identification register
The Interrupt Identification Register (IIR) bits show the current state of the UART and which state change caused the interrupt to occur. Based on bit values of the IIR interrupt can be serviced.
FCR: FIFO control register
The FIFO control register (FCR) is present starting with the 16550 series. The behavior of the FIFOs in the UART is controlled by this register. If a logical value 1 is written to bits 1 or 2, the function attached is triggered. The other bits are used to select a specific FIFO mode.
LCR: Line control register
The Line Control Register (LCR) is used at initialization to set the communication parameters such as parity, number of data bits etc. The register also controls the accessibility of the DLL and DLM registers.
MCR: Modem control register
Handshaking actions with the attached device are accomplished by the Modem Control Register (MCR). In the UART series 16550, setting and resetting of the control signals must be done by software. But in the new 16750, flow control automatically handled.
LSR: Line status register
The Line Status Register (LSR) shows the current state of communication. Errors, the state of the receiver and transmit buffers are available.
MSR: Modem status register
The Modem Status Register (MSR) contains information about the four incoming modem control lines on the device. The four most significant bits contain information about the current state of the inputs. The least four significant bits are used to indicate state changes. Each time the register is read the four LSB's are reset.
DLL and DLM: Divisor latch registers
The communication speed of the UART is changed by using a programmable value stored in Divisor Latch Registers DLL and DLM which contains the least and most significant registers.
Key Functions of a UART
• Serial to Parallel Conversion
• Buffering
• Data Communication Baud Rate Generation
• Communication Handshaking
• Start/Stop Bits
• Parity Generation
Other UART Functions
In addition to the basic job of converting data from parallel to serial for transmission and from serial to parallel on reception, a UART will usually provide additional circuits for signals
That signals can be used to indicate the state of the transmission media, and to regulate the flow of data in the event that the remote device is not prepared to accept more data.
Example:
• When the device connected to the UART is a modem, the modem may report the presence of a carrier on the phone line while the computer may be able to instruct the modem to reset itself or to not take calls by raising or lowering one more of these extra signals.
• The function of each of these additional signals is defined in the EIA RS232-C standard.
UART Errors
Overrun Error:
An "overrun error" occurs when the UART cannot process the byte that just came in before the next one arrives. The host processor must service the UART in order to remove characters from the buffer. If the host processor does not service the UART and the buffer becomes full, then Overrun Error will occur.
Framing Error:
A "Framing Error" occurs when the designated "start" and "stop" bits are not valid. Start bit acts as a reference for the remaining bits. When the "stop" bit is expected if the data line is not in the expected idle state a Framing Error will occur.
Parity Error:
A "Parity Error" occurs when the number of "active" bits does not agree with the specified parity configuration of the UART.
Underrun error:
In "underrun error" occurs when the UART transmitter has completed sending character and the transmit buffer is empty. In asynchronous modes this is treated as an indication that no data remains to be transmitted, rather than an error, since
additional stop bits can be appended. This error indication is commonly found in USARTs, since an underrun is more serious in synchronous systems.
Key Features of UART:
Choice of 1.8V, 2.5-V, 3.3-V, or 5-V supply Single-, dual-, and quad-channel devices available Transmit and Receive FIFOs of either 16-Byte or 64-Byte depth Patented hardware and software auto-flow control Programmable sleep mode and low-power mode. Industrial temperature characterization available
Types of UARTS
8250
The first UART in this line. It doesn't contain any scratch registers. 8250A is a modernized version of 8250, its bus operating speed is very fast.
8250A
The bus operating speed of this UART is greater than 8250's. It is used in the same way as 16450 in the sphere of software.
8250B
Very similar to that of the 8250 UART.
16450
Used in AT's (Improved bus speed over 8250's). Works stable at 38.4KBPS. Widespread today.
16550
This line is the first generation of buffered UART. This line has 16-byte buffer, however it doesn't work and is replaced with the 16550A.
16550A
This line is the most widespread UART version used for high-speed connection of modems with 14.4KBPS and 28.8KBPS rates. They made sure the FIFO buffers worked on this UART.
16650
New generation of UART. Contains 32 bytes of FIFO, programmed register of X-On/X-Off characters and supports power management.
16750
Produced by Texas Instruments. Contains 64-byte FIFO buffer.
Block details
UART Transmitter
Transmission operation is simpler since it is under the control of the transmitting system. As soon as data is deposited in the shift register after completion of the previous character, the UART hardware generates a start bit, shifts the required number of data bits out to the line, generates and appends the parity bit (if used), and appends the stop bits. Since transmission of a single character may take a long time relative to CPU speeds, the UART will maintain a flag showing busy status so that the host system does not deposit a new character for transmission until the previous one has been completed; this may also be done with an interrupt. Since full-duplex operation requires characters to be sent and received at the same time, practical UARTs use two different shift registers for transmitted characters and received characters.
The input signals to the transmitter are provided by the host processor , and the output signals control the movement of data in the UART. The architecture of the transmitter consists of a Controller , a data register (XMT_datareg),a data shift register(XMT_shftreg) and a status register to count the bits that are transmitted.
UART Receiver
All operations of the UART hardware are controlled by a clock signal which runs at a multiple (say, 16) of the data rate - each data bit is as long as 16 clock pulses. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, the spurious pulse is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register is made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processor interrupt to request that the host processor transfers the received data. In some common types of UART, a small first-in, first-out FIFO buffer memory is inserted between the receiver shift register and the host system interface. This allows the host processor more time to handle an interrupt from the UART and prevents loss of received data at high rates.
The UART receiver has the task of receiving the serial bit stream of data ,removing the start bit ,and transferring the data in a parallel format to a storage register connected to the host databus.The data arrives at a standard bit rate , but it is not necessarily synchronized with the internal clock at the host of the receiver and the transmitter’s clock is not available to receiver.This issue of synchronization is resolved by generating a local clock at a higher frequency and using it to sample the received data in a manner that preserves the integrity of the data.
Controller:
1.Definition: A device that controls the transfer of data from a computer to a peripheral device and vice versa is known as controller. For example, disk drives, display screens, keyboards, and printers all require controllers.
2.Controllers must be designed to communicate with the computer's expansion bus. There are three standard bus architectures for PCs -- the AT bus, PCI (Peripheral Component Interconnect), and SCSI. When we purchase a controller, therefore, we must ensure that it conforms to the bus architecture that our computer uses.
USR
This register contains status information bits, the most commonly used being Receive Complete, Transmit Complete, and Data Register Empty.
The UART status register holds status flags such as interrupt flags, overflow and framing error flags:
Bit 7 Bit 0RXC TXC UDRE FE OR --- --- ---
RXC:Receive Complete; This is the interrupt flag that is set when the UART has completely received a character. You can clear it in software by writing a 1 to it. You can either use it to let the AVR execute the interrupt service routine or poll it in a loop with interrupts disabled.
TXC:Transmit Complete; This flag is set when a transmit is completed. It can be used in the same ways as RXC (regarding clearing it in software and polling).
UDRE:UART Data Register Empty; This flag is set while the UDR is empty. This condition occurs when a character is transferred from the UDR to the transmit shift register. If the next character is written to UDR now, it will not be transferred to the UDR until the character currently being transferred is completely shifted out. This flag can be used to ensure maximum throughput by using a software buffer. Consequently, the UDRE ISR has to wite UDR: Otherwise the interrupt will occur again until data has been written to UDR or the UDRIE flag has been cleared.
UDRE is set upon reset to indicate that the transmitter is ready.
FE:Framing Error; This flag is set if the STOP bit is not received correctly. This is the case if it was interpreted to be low by the data recovery logic. And that's wrong. So if the FE bit is read 1 by your software, you must have serious noise problems or another hardware error.
OR:OverRun; The OverRun Flag is very useful for detecting if your code is handling incoming data fast enough: It is set when a character is transferred from the rx shift register to UDR before the previously received character is read. It is cleared again when the next character is read.
UDR – UART Data Register
The UDR register is actually two physically separated registers sharing the same I/O address. Transmitted and received data are written to, and read from this register.
Data shift register
The Shift Register is another type of sequential logic circuit that is used for the storage or transfer of data in the form of binary numbers and then "shifts" the data out once every clock cycle, hence the name shift register.
Shift Registers are used for data storage or data movement and are used in calculators or computers to store data such as two binary numbers before they are added together, or to convert the data from either a serial to parallel or parallel to serial format.
VERILOG
For a long time, programming languages such as C, Pascal & FORTRAN were being used to describe the computer programs that were sequential in nature. Similarly in the digital design field, designers felt the need for a standard language to describe digital circuits. Thus, HDL came into existence. HDL allowed the designers to model the concurrency of processes found in hardware elements.
Importance of HDLs
RTL descriptions, independent of specific fabrication technology can be made an verified.
functional verification of the design can be done early in the design cycle. Better representation of design due to simplicity of HDLs when compared to
gate-level schematics. Modification and optimization of the design became easy with HDLs. Cuts down design cycle time significantly because the chance of a functional
bug at a later stage in the design-flow is minimal.
With the advent of VLSI technology and increased usage of digital circuits, designers has to design single chips with millions of transistors.
It became almost impossible to verify these circuits of high complexity on breadboard. Hence Computer-aided techniques became critical for verification and design of VLSI digital circuits.As designs got larger and more complex, logic simulation assumed an important role in the design process. Designers could ironout functional bugs in the architecture before the chip was designed further. All these factors which led to the evolution of Computer-Aided Digital Design, intern led to the emergence of Hardware Description Languages.
Verilog HDL and VHDL are the popular HDLs. Today Verilog HDL is an accepted IEEE standard. In 1995, the original standard IEEE 1364-1995 was approved. IEEE 1364-2001 is the latest Verilog HDL standard that made significant improvements to the original standard.
Definition
Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of
abstraction. It is the most widely used HDL with a user community of more than 15000 active designers.
Difference between Verilog and VHDL
Verilog is similar to C and VHDL is similar to ADA. Verilog is simple to learn and simple to write code in. VHDL on the other hand takes longer time to learn and is bit complicated for writing code.The initial importance of Verilog is that it supports a hierarchical design sty le coupled with mixed mode simulation.
Importance of HDLs
RTL descriptions, independent of specific fabrication technology can be made an verified.
functional verification of the design can be done early in the design cycle. Better representation of design due to simplicity of HDLs when compared to
gate-level schematics. Modification and optimization of the design became easy with HDLs. Cuts down design cycle time significantly because the chance of a functional
bug at a later stage in the design-flow is minimal.
Verilog HDL
Verilog HDL is one of the most used HDLs. It can be used to describe designs at four levels of abstraction:
1. Algorithmic level.2. Register transfer level (RTL).3. Gate level.4. Switch level (the switches are MOS transistors inside gates).
Why Verilog ?
Easy to learn and easy to use, due to its similarity in syntax to that of the C programming language.
Different levels of abstraction can be mixed in the same design. Availability of Verilog HDL libraries for post-logic synthesis simulation. Most of the synthesis tools support Verilog HDL. The Programming Language Interface (PLI) is a powerful feature that allows
the user to write custom C code to interact with the internal data structures of Verilog. Designers can customize a Verilog HDL simulator to their needs with the PLI.
Hierarchical decomposition in Verilog
module complexModule ( ------- );
--------
Amodule A ( ------- );
Bmodule B( ------- );
Cmodule C ( ------- );
--------
endmodule
module testVecGeneration ( ------- );
--------
complexModule whole ( ------- );
--------
endmodule
The use of Verilog HDL has many advantage compared to the traditional schematic based design.
Designs can be described at very abstract level using HDL. Designers can write their design description without choosing any specific fabrication technology. If a new technology emerges, designers do not need to redesign their circuit. They simply input the design program to the logic synthesis tool and create a new gate level netlist using the new fabrication technology. The logic synthesis tool will optimize the circuit in area and timing for the new technology.
By describing the design in HDL, functional verification of the design can be done early in the design cycle. Since designers work at the high level language, they can optimize and modify the design module until it meets the desired functionality. Most of the design bugs are eliminated at this point.
Verilog has two clear advantages over VHDL:
It allows switch-level modelling - which some designers find useful for exploring new circuits
It ensures that all signals are initialized to "unknown" which ensure s that all designers will produce the necessary logic to initialize their de sign - the base types in VHDL initialize to zero and the "hasty" designer may omit a global reset
Digital design methods
Digital design methods are of two types:
1. Top-down design method : In this design method we first define the top-level block and then we build necessary sub-blocks, which are required to build the top-level block. Then the sub-blocks are divided further into smaller-blocks, and so on. The bottom level blocks are called as leaf cells. By saying bottom level it means that the leaf cell cannot be divided further.
2. Bottom-up design method : In this design method we first find the bottom leaf cells, and then start building upper sub-blocks and building so on, we reach the top-level block of the design.
In general a combination of both types is used. These types of design methods helps the design architects, logics designers, and circuit designers. Design architects gives specifications to the logic designers, who follow one of the design methods or both. They identify the leaf cells. Circuit designers design those leaf cells, and they try to optimize leaf cells in terms of power, area, and speed. Hence all the design goes parallel and helps finishing the job faster.
Modules
A module is the basic building block in Verilog HDL. In general many elements are grouped to form a module, to provide a common functionality, which can be used at many places in the design. Port interface (using input and outputports) helps in providing the necessary functionality to the higher-level blocks. Thus any design modifications at lower level can be easily implemented without affecting the entire design code. The structure of a module is show in the figure below.
module module_nameports, port declarations,parameters
variable declarations(regs , wires, etc) Dataflow segments (assign)Lower level modules Instances
Behavioural blocks(always,intial)
Tasks and Functions
endmodule
Keyword module is used to begin a module and it ends with the keyword endmodule. The syntax is as follows:
module module_name---// internals---endmodule
Multiple modules can be designed in single design file with any order.
PORTS
Modules communicate with external world using ports. They provide interface to the modules. A module definition contains list of ports. All ports in the list of ports must be declared in the module, ports can be one the following types:
Input port, declared using keyword input. Output port, declared using keyword output. Bidirectional port, declared using keyword inout.
All the ports declared are considered to be as wire by default. If a port is intended to be a wire, it is sufficient to declare it as output, input, or inout. If output port
holds its value it should be declared as reg type. Ports of type input and inout cannot be declared as reg because reg variables hold values and input ports should not hold values but simply reflect the changes in the external signals they are connected to..
Block Statements
Block statements are used to group two or more statements together, so that they act as one statement. There are two types of blocks:
Sequential block. Parallel block.
Sequential block:
The sequential block is defined using the keywords begin and end. The procedural statements in sequential block will be executed sequentially in the given order. In sequential block delay values for each statement shall be treated relative to the simulation time of the execution of the previous statement. The control will pass out of the block after the execution of last statement.
Parallel block:
The parallel block is defined using the keywords fork and join. The procedural statements in parallel block will be executed concurrently. In parallel block delay values for each statement are considered to be relative to the simulation time of entering the block. The delay control can be used to provide time-ordering for procedural assignments. The control shall pass out of the block after the execution of the last time-ordered statement.
Tasks and functions
Tasks and functions are introduce in the verilog, to provide the ability to execute common procedures from different places in a description. This helps the designer to break up large behavioral designs into smaller pieces. The designer has to abstract the similar pieces in the description and replace them either functions or tasks. This also improves the readability of the code, and hence easier to debug. Tasks and functions must be defined in a module and are local to the module. Tasks are used when:
There are delay, timing, or event control constructs in the code. There is no input. There is zero output or more than one output argument.
Functions are used when:
The code executes in zero simulation time. The code provides only one output(return value) and has at least one input. There are no delay, timing, or event control constructs.
Various levels of abstraction
In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of abstraction in verilog. They are:
Behavioral or algorithmic level: This is the highest level of abstraction. A module can be implemented in terms of the design algorithm. The designer no need to have any knowledge of hardware implementation.
Data flow level: In this level the module is designed by specifying the data flow. Designer must how data flows between various registers of the design.
Gate level: The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design.
Switch level: This is the lowest level of abstraction. The design is implemented using switches/transistors. Designer requires the knowledge of switch-level implementation details.
BLOCK DIAGRAM:
UART Receiver RCV_shftreg
Serial_in
RCV_datareg
Read_not_ready_in
Read_not_ready_out
Error1
Error2
Sys_Clock Sample_clk
Reset_ Clock
Bit_count
Byte_ready clear clear
T_byte shift
start
Load_XMT_shftreg
XMT_shiftreg
Serial_out 1
1
Load_XMT_datareg
XMT_datareg
Uart_transmitter_arch
RECEIVER CONTROLLER
UART Clock Generator
Transmitter controller
To / From Host
Data Bus
The controller has the following inputs.For simplicity,Load_XMT_datareg is shown connected directly to XMT_datareg:
Byte_ready asserted by host machine to indicate that Data_Bus has valid data
Load_XMT_datareg assertion transfers Data_Bus to the transmitter data storage register,XMT_datareg.
T_byte assertion intiates transmission of a byte of data,includuing the stop,start,and parity bits
Bit_count counts bits in the word during transmission
The state machine of the controller forms the following output signals that
control the datapath of the transmitter
Load_XMT_shftreg assertion loads the contens of XMT_data_reg into XMT_shftreg
Start signals thestart of transmission
Shift directs XMT_shftreg to shift by one bit towards the LSB and to backfill with a stop bit(1)
Clear clears bit_count
UART
Transmitter
Datapath
Controller
Byte_ready
Load_XMT_datareg
T_BYTE
Bit_count Shift
Clear
Load_XMT_shftreg
start
The state machine produces the following inputs:
Read_not_ready_in signals that the host is not ready to receive data
Serial_in serial bit stream received by the unit
Reset active low reset
Sample_counter counts the bits that have been sampled
Read_not_ready_in
UART
Receiver
Datapath
Controller
Serial_in
Sample_Count
Bit_Counter
Read_not_ready_in
Clr_Sample_Counter
Inc_Bit_counter
Clr_Bit_Counter
Inc_Sample_Counter
shift
load
Error1
Error2
The state machine produces the following outputs:
read_not_ready_out signals that the receiver has received 8 bits
inc_Sample_counter increases Sample_counter
clr_Sample_counter clears Sample_counter
inc_Bit_counter increases Bit_counter
clr_Bit_counter clears Bit_counter
shift causes RCV_shftreg to shift towards the LSB
load causes RCV_shftreg to transfer data RCV_datareg
Error1 asserts if host is not ready to receiver data after last bit has been sampled
Error2 asserts if the stop_bit is missing
ASM Chart for the state machine controller for the UART Transmitter
IDLE
Reset_
T_byte
The machine has three states : idle , waiting , and sending . When reset _ is asserted , the machine asynchronously enters idle , bit_count is flushed , XMT_shftreg is loaded with 1s, and the control signals clear ,Load_XMT_shftreg , shift , and start are driven to 0. In idle , if an active edge of Clock occurs while Load_XMT_data_reg is asserted by the external host ,the contents of Data_Bus will transfer XMT_data_reg .The machine remains in idle until start is asserted.
When Byte_ready is asserted Load_XMT_shftreg is asserted and next_state is driven to waiting . The assertion of Load_XMT_shftreg indicates that XMT_datareg now contains data that can be transferred to the internal shift register at the next active edge of Clock , with Load_XMT_shftreg asserted, three activities occur :(1)state transfers from idle to waiting ,(2)the contents XMT_datareg are loaded into the leftmost bits of XMT_shftreg , a (word_size + 1 )- bit shift register whose LSB signals that start and stop of transmission , and (3)the LSB of XMT_shftreg is reloaded with 1,stop bit. The machine remains in waiting until the external processor asserts T_byte .
At the next active edge of Clock , with T_byte asserted, state enters sending, and the LSB of XMT_shftreg is set to 0 to signal the start of transmission .At the same time , shift is driven to 1, and next_state retains the state code corresponding to sending .At subsequent active edges of Clock ,with shift asserted ,state remains in sending and the contents of XMT_shftreg are shifted toward the LSB , which drives the external serial channel .As the data shifts occur , 1s are back-filled in XMT_shftreg ,and bit_count is incremented .With state in sending , shift asserts while bit_count is less than 9.The machine increments bit_count after each movement of data , and when bit_count reaches 9 clear asserts, indicating that all of the bits of the augmented word have been shifted to serial output. At the next active edge of Clock ,the machine returns to idle.
UART receiver ASM chart RESET_
inininInc_sample_counter
IDLE
Serial_in=0
Starting
Serial_in=1
Sample_couter=3
Clr_sample_counter
Receiving/inc_sample_counter
Sample_counter=7
Bit_counter=8
Read_not_ready_in
Shift inc_Bit_counter
Clr_sample_counter
Clr_sample_counter
Error 1
Error 2
Serial_in=0
loadRead_not_ready_out
clr_sample_counter
clr_bit_counter
Inc_Sample_counter
The machine has three states :idle, starting , and receiving .Transitions between states are synchronized by Sample_clk . Assertion of an asynchronous active-low reset puts the machine in the idle state . It remains there until Serial_in is low , then makes a transition to starting . In starting the machine samples Serial_in to determine whether the first bit is a valid start –bit (it must be 0).Depending on the sampled values , inc_Sample_counter and clr_Sample_counter may be asserted to increment or clear the counter at the next active edge of Sample_clock . If the next three samples of Serial_in are 0,the machine concludes that the start-bit is valid and goes to the state receiving . Sample_counter is cleared on the transition to receiving . In this state , eight successive samples are taken (one for each bit of the byte ,at each active edge of Sample_clk ), with inc_Sample_counter asserted . Then Bit-counter is incremented .If the sample bit is not the last bit , inc_Bit_counter and shift are asserted .The assertion of shift will cause the sample value to be loaded into the MSB of RCV_shftreg ,the receiver shift register, and will shift the sudden leftmost bits of the register toward the LSB.
After the last bit has been sampled , the machine will assert read_not_ready_out, a handshake output signal to the processor , and clear the bit counter. At this time the machine also checks the integrity of the data and the status of the host processor . If the read_not_ready_in is asserted , the host processor is not ready to receive the data (Error1).If a stop-bit is not next bit (detected by Serial_in=0),there is an error in the format of the received data(Error2).Otherwise , load is asserted to cause the contents of the shift register to be transferred as a parallel word to RCV_datareg , a data register in host machine , with a direct connection to data_bus .
TOOL DETAILS
XILINX DELIVERS ISE 9.2i WITH LOWER MEMORY REQUIREMENTS AND NEW OPERATING SYSTEM SUPPORT
Latest release allows designers to meet performance goals with greater certainity and reach design closure in less time.
History of XILINX ISE 9.2i :
SAN JOSE, Calif., June 25, 2007 – Xilinx, Inc. (NASDAQ: XLNX) today announced immediate availability of the ISE™ 9.2i (Integrated Software Environment) design tools, the latest release of its widely-used design solution. Improvements in the ISE 9.2i release reduce memory requirements by an average of 27 percent while providing expanded support for Microsoft Windows Vista, Microsoft Windows XP x64, and Red Hat Enterprise WS 5.0 32-bit and 64-bit operating systems. To simplify multi-rate DSP designs with a large number of clocks typically found in wireless and video applications, ISE 9.2i software features breakthrough advancements in place and route and clock algorithms offering up to a 15 percent performance advantage.
ISE 9.2i software is powered by the company’s latest SmartCompile™ technology, which cuts implementation runtimes by up to 6X while maintaining exact design preservation of unchanged logic. The new release also provides the most advanced design solution for the latest line of Xilinx® 65nm Virtex™-5 high-performance FPGAs and 90nm Spartan™-3 generation high volume FPGAs. Xilinx has been delivering the benefits of 65nm FPGAs since May 2006 with production qualified devices available now.
Lower Memory Requirements
Through algorithmic improvements in memory usage, ISE 9.2i design tools radically improve utilization of computing resources, providing users with greater design flexibility. This reduction in memory usage enables users to design with higher density FPGAs with the more widely available 32-bit version of Microsoft Windows XP in lieu of the previously required 64-bit operating system.
“With broad availability of our feature-rich high-performance 65nm Virtex-5 FPGAs, customers are demanding more from their design platform,” said Bruce Talley, vice president of the Design Software Division at Xilinx. “ISE 9.2i, which combines advanced tools like SmartCompile technology with better usage of their computing hardware, provides faster timing closure and higher quality of results for a better time-to-market solution.”
Embedded Processing and Debug Improvements in ISE 9.2i software permit greater flexibility for designs which leverage embedded processors. Tighter integration with Platform Studio (Xilinx integrated development environment for embedded design) allows embedded users improved access to the design closure tools residing within the ISE design environment.
The ISE 9.2i design suite is accompanied by the release of ChipScope Pro™ 9.2 debug and verification software. Available as an add-on option, the ChipScope Pro 9.2 solution reduces verification cycles by up to 50 percent. Also included is the newest release of the ChipScope Pro Serial IO Toolkit, providing simplified debugging of high-speed serial IO designs for Virtex-4 FX and Virtex-5 LXT and SXT FPGAs.
Pricing and AvailabilityISE software delivers programmable logic design solutions to over 300,000 users worldwide with an intuitive, front-to-back design environment for all Xilinx product families, including Virtex-4 and Virtex-5 platform FPGAs, Spartan™-3 generation FPGAs, and CoolRunner™-II CPLDs. All versions of ISE 9.2i software packages support Windows® XP, Windows XP x64, Windows Vista Business and Linux® Red Hat® Enterprise WS. ISE Foundation also supports Solaris® 2.9.
ISE™ 9.2i Foundation™, ChipScope Pro 9.2, and ChipScope Pro Serial I/O Toolkit configurations are immediately available with prices ranging from US$495 to $2495. Full-featured 60-day evaluation versions can be downloaded from the Xilinx web site at no charge.
What's New in Xilinx ISE 9.2i
New Device Support
This release supports the new Spartan™- 3A DSP family.
New Software Features
Operating System Support
Support for Windows® Vista Business 32-bit operating system. Note: This operating system is supported, but has had limited testing.
Support for Windows XP Professional 64-bit operating system.
Support for Red Hat Enterprise WS 5.0 32-bit and 64-bit operating system. Note: This operating system is supported, but has had limited testing.
Project Management
Xilinx Platform Studio (XPS) sources (.xmp files) may now reside at the top-level of hierarchy of an ISE Project .
Ability to create and add sources to VHDL Libraries using Tcl Commands and scripts.
Distributed version of Xilinx Tcl is upgraded to 8.4.14.
XST Synthesis Update
A complete list of the new features in XST 9.2i can be found at the beginning of the XST User Guide, available from the Software Manuals collection.
Improved block RAM power optimization. Automatic support of Synplicity® syn_ramstyle and syn_romstyle
constraints. Capability to automatically rebuild the netlist hierarchy. Improved automatic BRAM resource management.
Implementation Improvements
Enhancements to the SmartCompile (Partitions and SmartGuide) technologies with improved design performance.
Twenty-seven percent improved memory reduction.
Xilinx Simulation Update
ISE Simulator
Ability to save Waveform Settings:o Dividerso Markerso Signal ordering
Improved Printing support:o Multiple page print support.o Ability to print from selected time segments.
Do file emulation support. Middle-mouse-button support. Ability to right-click and add signals to the waveform from the hierarchical
browser.
Bus ordering reversal in the waveform viewer. Stimulus automatically delayed by 100 ns in the waveform editor.
ModelSim Xilinx® Edition III
MXE is updated to ModelSim Xilinx® Edition III Version 6.2g.
HDL Libraries and Compxlib
Support for Master SelectMAP Configuration Simulation Model for Spartan™-3A and Virtex™-5.
VHDL support
Signal Integrity
IBISWriter support for Spartan™-3E and Spartan™-3A product families.
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How does a UART work?
Standard UARTs transmit and receive data in 11-bit packets, of which 8-bits are for the data, there is one bit at the beginning of the packet called the Start bit, which is always a logic 0, and 2 bits at the end called the Stop bits, which are always a logic 1
WORKING OF UART:-
1. The UART takes bytes of data and transmits the individual bits in a sequential fashion.
2. At the destination, a second UART re-assembles the bits into complete bytes.
3. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character.
4. Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors.
5. To a host system, the UART appears as an 8-bit input and output port that it can read from and write to.
6. Whenever the host has data to be sent, it just sends these data to the UART in byte format (8-bit wide), whenever the UART receives data from another serial device it will buffer these data in its FIFO (again 8-bit wide), then it will indicate the availability of these data to the host through an internal register bit, or through a hardware interrupt signal.
CODING:
VERILOG CODE FOR UART TRANSMITTER
module UART_Transmitter_Arch
(Serial_out,Data_Bus,Byte_ready,Load_XMT_datareg,T_byte,Clock,reset_);
parameter word_size=8;
parameter one_hot_count=3;
parameter state_count=one_hot_count;
parameter size_bit_count=3;
parameter idle =3'b001;
parameter waiting =3'b010;
parameter sending =3'b100;
parameter all_ones=9'b1_1111_1111;
output Serial_out;
input [word_size - 1:0] Data_Bus;
input Byte_ready;
input Load_XMT_datareg;
input T_byte;
input Clock;
input reset_;
reg[word_size-1:0]XMT_datareg;
reg[word_size:0] XMT_shftreg;
reg Load_XMT_shftreg;
reg[state_count-1:0] state,next_state;
reg[size_bit_count:0] bit_count;
reg clear;
reg shift;
reg start;
assign serial_out=XMT_shftreg[0];
always@(state or Byte_ready or bit_count or T_byte)begin:Output_and_next_state
Load_XMT_shftreg=0;
clear=0;
shift=0;
start=0;
next_state=state;
case(state)
idle: if(Byte_ready==1)begin
Load_XMT_shftreg=1;
next_state=waiting;
end
waiting:if(T_byte==1)begin
start=1;
next_state=sending;
end
sending :if(bit_count!=word_size+1)
shift=1;
else begin
clear=1;
next_state=idle;
end
default : next_state=idle;
endcase
end
always@(posedge Clock or negedge reset_)begin:State_Transitions
if(reset_==0)state<=next_state;end
always@(posedge Clock or negedge reset_)begin:Register_Transfers
if(reset_==0)begin
XMT_shftreg<=all_ones;
bit_count<=0;
end
else begin
if(Load_XMT_datareg==1)
XMT_datareg<=Data_Bus;
if(Load_XMT_shftreg==1)
XMT_shftreg<={XMT_datareg,1'b1};
if(start==1)
XMT_shftreg[0]<=0;
if(clear==1)bit_count<=0;
else if(shift==1)bit_count<=bit_count+1;
if(shift==1)
XMT_shftreg<={1'b1,XMT_shftreg[word_size:1]};
end
end
endmodule
VERILOG CODE FOR UART RECEIVER
module UART8_Receiver
(RCV_datareg,read_not_ready_out,Error1,Error2,Serial_in_read_not_ready_in,Sample_clk_reset_);
parameter word_size =8;
parameter half_word =word_size/2;
parameter Num_counter_bits =4;
parameter Num_state_bits =2;
parameter idle =2'b00;
parameter startung =2'b01;
parameter receiving =2'b10;
output [word_size - 1:0] RCV_datareg;
output read_not_ready_out,
Error1,Error2;
input Serial_in,
Sample_clk,
reset_,
read_not_ready_in,
reg RCV_datareg
reg [word_size - 1:0] RCV_shftreg
reg [Num_counter_bits - 1:0]Sample_counter;
reg [Num_counter_bits:0] Bit_counter;
reg [Num_state_bits - 1:0] state,next_state;
reg inc_Bit_counter,clr_Bit_counter;
reg inc_Sample_counter,clr_Sample_counter;
reg shift,load,read_not_ready_out;
reg Error1,Error2;
always @ (state or Serial_in or read_not_ready_in or Sample_counter or Bit_counter) begin
read_not_ready_out = 0;
clr_Sample_counter = 0;
clr_Bit_counter = 0;
inc_Sample_counter = 0;
inc_Bit_counter = 0;
shift = 0;
Error1 = 0;
Error2 = 0;
load = 0;
next_state = state;
case (state)
idle: if(Serial_in == 0)next_state = starting;
starting if(Serial_in == 1) begin
next_state = idle;
clr_Sample_counter = 1;
end else
if(Sample_counter == half_word - 1) begin
next_state = receiving
clr_Sample_counter = 1;
end else inc_Sample_counter = 1;
receiving: if(Sample_counter < word_size - 1) inc_Sample_counter = 1;
else begin
clr_Sample_counter = 1;
if(Bit_counter ! =word_size)begin
shift = 1;
inc_Bit_counter = 1;
end
else begin
next_state = idle;
read_not_ready_out = 1;
clr_Bit_counter = 1;
if(read_not_ready_in == 1) Error1 = 1;
ela=se if(Sample_in == 0) Error = 1;
else load = 1;
end
end
default: next_state = idle;
endcase
end
always @ (posedge Sample_clk) begin
if(reset_ == 0)begin state <= idle;
Sample_counter <= 0;
Bit_counter <= 0;
RCV_datareg <= 0;
RCV_shftreg <= 0;
end
else begin
state <= next_state;
if(clr_Sample_counter == 1) Sample_counter <= 0;
else if (inc_Sample_counter ==1) Sample_counter <= Sample_counter + 1;
if(clr_Bit_counter == 1) Sample_counter <= 0;
else if (inc_Bit_counter == 1) Bit_counter <= Bit_counter + 1;
if(shift == 1) RCV_shftreg <= {Serial_in, RCV_shftreg[word_size - 1:1]}
if(load == 1) RCV_datareg <= RCV_shftreg
end
end
endmodule
APPLICATIONS OF UART :
1. Serial data communications applications.
2. Modem interface
3. Embedded microprocessor r boards
4. Serial or modem computer interface
5. Serial interface within modems and other devices
References
1.Advanced Digital Design with the Verilog HDL by Michael D.Ciletti
2. www.edaboard.com
3. www.classle.net/projects/project_ideas
4. www.scribd.com
5.www.asic-world.com
6.www.vlsi.com
7.projectsuniversal.in
8.only-vlsi.blogspot.com
9.www.thesatya.com
10.en.pudn.com
