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Twin Logic Gates – Improved Logic Reliability by Redundancy
concerning Gate Oxide Breakdown
Hagen Sämrow, Claas Cornelius, Frank Sill,Andreas Tockhorn, Dirk Timmermann
03.09.2009, Natal
Institute of Applied Microelectronics
and Computer EngineeringUniversity of Rostock
2
Outline
Motivation and Basics
Approaches for reliability enhancements
Gate oxide breakdown
Redundancy strategies
Redundancy on different levels
Results
Discussion
Conclusion / Outlook
3
Motivation – Known approaches
Yield enhancements
- Layout modifications
- Redundancy
Soft error resilience
- Hardening techniques
- Reusing debug resources
for redundant flipflops [Mitra]
Little effort put into
lifetime reliability
enhancements
Transient failures Permanent failures
Initial failures Failures occuringat runtime
Reliability
4
Basics – Gate oxide breakdown
Gate oxide breakdown – GOB:
Point of time a conducting path between gate and substrate is generated
Mainly dependent on:Gate oxide thicknessElectrical field at the gate
Causes:Sudden extrinsic overvoltage: ESD – Electro-Static DischargeSlow intrinsic destruction over time: TDDB – Time-Dependent Dielectric Breakdown
5
Basics – TDDB
Poly Silicon
Substrate
SiO2
Poly Silicon
Substrate
SiO2
Poly Silicon
Substrate
SiO2
Initial traps
During operation: generation of overlapping traps
Soft breakdown:Creation of aconducting patch
Increasing current flowHeat dissipationThermal damage
Finally: Hard breakdownPhysical mechanism: trap creation
Poly Silicon
Substrate
ISiO2
Poly Silicon
Substrate
SiO2
Poly Silicon
Substrate
SiO2
Poly Silicon
Substrate
R
R -> 0SiO2
R 0
6
Basics – TDDB
Finally: Hard breakdown
Model by Renovell et al.
Follows new research results
Gate oxide breakdown harms an affected transistor and its associated cell
with a modified delay
Whole circuit fails if the timing between the cells is no longer balanced
7
Basics – Scaling issues
Scaling increases the gate oxide breakdown problems:Increasing number of transistors within a die
Decreasing gate oxide thickness
Increase of the electrical field due to non-ideal supply voltage scaling
tox1
l > l1
tox2
2
scaling
l1l2
t > tox1 ox2
tox1
l > l1
tox2
2
scaling
l1l2
t > tox1 ox2
E1 E2
E < E1 2
8
Redundancy strategies
Basic multiplier
Block duplication
Gate duplication
Transistor duplication
9
Simulation setup
Wallace multiplier
Transistor level simulations with HSpice
Industrial 65 nm gate library
Gate oxide breakdown model of Renovell et al.
Implementation of cells with transistors with standard
threshold voltage (SVT) and high threshold voltage (HVT)
10
Results – No defects
Delay Overall power Static Power Area0
50
100
150
200
250
Design parameters
Ra
tio
to
ba
sic
mu
ltip
lier
[%]
De-lay
Over-all power
Static Power
Area
0
Block duplication SVT Block duplication HVT
Twin Logic Gates SVT Twin Logic Gates HVT
Transistor duplication SVT Transistor duplication HVT
11
Results – Reliability with defects
Simulation results
-10 10 30 50 70 90 110 130 1500
20
40
60
80
100
time units t
R(t
) [%
]
-10 10 30 50 70 90 110 130 1500
20
40
60
80
100
time units t
R(t
) [%
]
-10 10 30 50 70 90 110 130 1500
20
40
60
80
100
time units t
R(t
) [%
]
-10 10 30 50 70 90 110 130 1500
20
40
60
80
100
time units t
R(t
) [%
]
-10 10 30 50 70 90 110 130 1500
20
40
60
80
100
time units t
R(t
) [%
]
Duplication MTTFGOB + / -
No 26.72 0 %
Block 21.17 - 21 %
with HVT-Cells 28.42 + 6 %
Transistor 44.34 + 66 %
with HVT-Cells 54.71 + 105 %
Twin Logic Gates 72.52 + 171 %
with HVT-Cells 80.97 + 203 %
Results – Discussion
12
Why is the gate level duplication
(Logic Twin Gates) better than
transistor duplication?
Both implementation only differ in
the duplication of the transistor
stacks
Defect_net 2 is charged to a
voltage related to the GOB Current flow from drain to source of the
middle transitor is rather pinched off due to the defect (higher voltage level between lowest two transistors)
Increased fall time of the defect stack Transistor duplicated stacks are slightly
slower due to the cross links
13
Results – Graceful degradation I
Increase of the delay with rising defects
0 20 40 60 80 1000.6
1.0
1.4
Twin Logic Gates SVT
Twin Logic Gates HVT
Transistor duplication SVT
Transistor duplication HVT
No duplication
Number of defects
De
lay
[n
s]
14
Results – Graceful degradation I
Increase of the delay with rising defects
0 40 80 1200
2
4
6
8
10 HVT overall power
SVT overall power
No duplication
Number of defects
Po
we
r L
og
ic T
win
Ga
tes
[m
A]
due to increased static power consumption
0 40 80 1200
2
4
6
8
10 HVT overall power
SVT overall power
HVT static power
SVT static power
No duplication
Number of defects
Po
we
r L
og
ic T
win
Ga
tes
[m
A]
15
Conclusion
Need of design improvements for lifetime reliability
Logic Twin Gates promises the most improvements
concerning gate oxide breakdown
Simple integration of Logic Twin Gates into existing
design flows and CAD tools
Graceful degradation behavior in the presence of defects
16
Outlook
Partial duplication of most vulnerable gates or transistors
Usage of benchmark circuits
Investigation of the impact of soft breakdowns
