TS3L501E 8-Channel SPDT/16-Bit to 8-Bit Multiplexer and ... · PDF file16-bit to 8-bit multiplexer or demultiplexer LAN switch with a single select (SEL) input and Power-Down Mode

A0

A1

A2

A3

A4

A5

A6

A7

B0

B1

B2

B3

B4

B5

B6

C1

C2

C3

C4

C5

C6

C7

SEL

B7

C0

LED_A0

LED_B1

LED_B0

LED_A1

LED_A2 LED_B2

LED_C1

LED_C0

LED_C2

PD

Control Logic

POWER DOWN

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TS3L501ESCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017

TS3L501E 8-Channel SPDT/16-Bit to 8-Bit Multiplexer and DemultiplexerEthernet LAN Switch With Power-Down Mode

1

1 Features1• Integrated Power-Down Mode• Wide Bandwidth (BW = 600 MHz Typical)• Low Crosstalk (XTALK = –37 dB Typical

at 250 MHz)• Low Bit-to-Bit Skew (tsk(o) = 100 ps Maximum)• Low and Flat ON-State Resistance

(ron = 4 Ω Typical, ron(flat) = 0.5 Ω Typical)• Low Input and Output Capacitance

(CON = 9 pF Typical)• Rail-to-Rail Switching on Data I/O Ports

(0 V to 3.6 V)• VCC Operating Range From 3 V to 3.6 V• Support Power-Down Mode• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II• ESD Performance (A, B, C, LED pins)

– ±4-kV IEC61000-4-2, Contact Discharge– 6-kV Human Body Model Per JESD22-A114E

(Switch I/O pins to GND)• ESD Performance (All pins)

– 2-kV Human Body Model Per JESD22-A114E

2 Applications• 10, 100, and 1000 Base-T Signal Switching• Differential (LVDS, LVPECL) Signal Switching• Audio and Video Switching• Hub and Router Signal Switching

3 DescriptionThe TS3L501E is a 8-channel SPDT analog switch or16-bit to 8-bit multiplexer or demultiplexer LAN switchwith a single select (SEL) input and Power-DownMode input. The device provides additional I/Os forswitching status indicating LED signals and includeshigh ESD protection. SEL input controls the data pathof the multiplexer or demultiplexer. Power-down inputcan put the device into the standby mode forminimizing current consumption per mode selection.

The device provides a low and flat ON-stateresistance (ron) and an excellent ON-state resistancematch. Low input or output capacitance, highbandwidth, low skew, and low crosstalk amongchannels make this device suitable for various LANapplications, such as 10/100/1000 Base-T. Thisdevice can be used to replace mechanical relays inLAN applications. It also can be used to route signalsfrom a 10/100 Base-T Ethernet transceiver to the RJ-45 LAN connectors in laptops or in docking stations.

It is characterized for operation over the free-airtemperature range of –40ºC to 85ºC.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)TS3L501E WQFN (42) 9.00 mm × 3.50 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Functional Block Diagram

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ..................................... 56.2 ESD Ratings.............................................................. 56.3 Recommended Operating Conditions....................... 56.4 Thermal Information .................................................. 66.5 Electrical Characteristics for 1000 Base-T Ethernet

Switching.................................................................... 66.6 Electrical Characteristics for 10/100 Base-T Ethernet

Switching.................................................................... 66.7 Switching Characteristics .......................................... 76.8 Dynamic Characteristics ........................................... 76.9 Typical Characteristics .............................................. 8

7 Parameter Measurement Information .................. 97.1 Enable and Disable Times ........................................ 97.2 Skew ....................................................................... 107.3 HP8753ES Setup.................................................... 117.4 HP8753ES Setup.................................................... 12

7.5 HP8753ES Setup.................................................... 138 Detailed Description ............................................ 14

8.1 Overview ................................................................. 148.2 Functional Block Diagram ....................................... 148.3 Feature Description................................................. 148.4 Device Functional Modes........................................ 14

9 Application and Implementation ........................ 159.1 Application Information............................................ 159.2 Typical Application ................................................. 15

10 Power Supply Recommendations ..................... 1711 Layout................................................................... 17

11.1 Layout Guidelines ................................................. 1711.2 Layout Example .................................................... 18

12 Device and Documentation Support ................. 1912.1 Documentation Support ........................................ 1912.2 Receiving Notification of Documentation Updates 1912.3 Community Resources.......................................... 1912.4 Trademarks ........................................................... 1912.5 Electrostatic Discharge Caution............................ 1912.6 Glossary ................................................................ 19

13 Mechanical, Packaging, and OrderableInformation ........................................................... 19

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (May 2016) to Revision C Page

• Added pin numbers 4, 8, 14, 21, 30, 39 to VDD in the Pin Functions table ............................................................................ 4

Changes from Revision A (September 2010) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementationsection, Power Supply Recommendations section, Layout section, Device and Documentation Support section, andMechanical, Packaging, and Orderable Information section. ................................................................................................. 1

• Removed Ordering Information table .................................................................................................................................... 1


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37

35

33

38

36

34

31

29

30

32

2

4

6

8

12

10

14

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1

3

5

7

11

9

13

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19

17 22

24

21

42

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39

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25

B0

B4

C0

C4

B2

B6

C2

C6

B1

B5

C1

C5

B3

B7

C3

C7

VDD

VDD

A0

A1

VDD

VDD

VDD

PD

A2

A3

A4

A5

A6

A7

SEL

LED_A0

LED_ A1

LED_ B0

VD

D

LE

D_B

1

LE

D_C

0

LE

D_C

1

VD

D

LE

D_A

2

LE

D_ B

2

LE

D_ C

2

ExposedCenter Pad

(GND)

3

TS3L501Ewww.ti.com SCDS307C –SEPTEMBER 2010–REVISED DECEMBER 2017


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5 Pin Configuration and Functions

RUA Package42-Pin WQFN

Top View

The exposed center pad must be connected to GND.

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.A0 2 I/O Port A Common I/O signal pathA1 3 I/O Port A Common I/O signal pathA2 6 I/O Port A Common I/O signal pathA3 7 I/O Port A Common I/O signal pathA4 9 I/O Port A Common I/O signal pathA5 10 I/O Port A Common I/O signal pathA6 11 I/O Port A Common I/O signal pathA7 12 I/O Port A Common I/O signal pathB0 38 I/O Port B I/O signal pathB1 37 I/O Port B I/O signal pathB2 34 I/O Port B I/O signal pathB3 33 I/O Port B I/O signal pathB4 29 I/O Port B I/O signal pathB5 28 I/O Port B I/O signal pathB6 25 I/O Port B I/O signal path


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4




Pin Functions (continued)PIN

I/O DESCRIPTIONNAME NO.B7 24 I/O Port B I/O signal pathC0 36 I/O Port C I/O signal pathC1 35 I/O Port C I/O signal pathC2 32 I/O Port C I/O signal pathC3 31 I/O Port C I/O signal pathC4 27 I/O Port C I/O signal pathC5 26 I/O Port C I/O signal pathC6 23 I/O Port C I/O signal pathC7 22 I/O Port C I/O signal pathGND Exposed Center Pad — Ground

LED_A0 15 I/O Port A LED I/O Common signal path, (may also be used as a generalpurpose signal path)

LED_A1 16 I/O Port A LED Common I/O signal path, (may also be used as a generalpurpose signal path)

LED_A2 42 I/O Port A LED Common I/O signal path, (may also be used as a generalpurpose signal path)

LED_B0 17 I/O Port B LED I/O signal path, (may also be used as a general purposesignal path)



LED_C0 19 I/O Port C LED I/O signal path, (may also be used as a general purposesignal path)



PD 5 Input Power Down Input, Active HighSEL 13 Input Select InputVDD 1, 4, 8, 14, 21, 30, 39 — Power


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5




(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to ground, unless otherwise specified.(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(4) VI and VO are used to denote specific conditions for VI/O.(5) II and IO are used to denote specific conditions for II/O.

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITVDD Supply voltage –0.5 4.6 VVIN Control input voltage (2) (3) –0.5 7 VVI/O Switch I/O voltage (2) (3) (4) –0.5 7 VIIK Control input clamp current VIN < 0 –50 mAII/OK I/O port clamp current VI/O < 0 –50 mAII/O ON-state switch current (5) ±128 mA

Continuous current through VDD or GND ±100 mATstg Storage temperature –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman-body model (HBM), perANSI/ESDA/JEDEC JS-001 (1)

All pins except 1, 4, 5, 8,13, 14, 21, 30, and 39 ±6000

VPins 1, 4, 5, 8, 13, 14, 21,30, and 39 ±2000

Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500

(1) All unused control inputs of the device must be held at VDD or GND to ensure proper device operation. See the TI application report,Implications of Slow or Floating CMOS Inputs, SCBA004.

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITVDD Supply voltage 3 3.6 VVIH High-level control input voltage (SEL) 2 5.5 VVIL Low-level control input voltage (SEL) 0 0.8 VVIN Input voltage (SEL) 0 5.5 VVI/O Input or output voltage 0 VDD VTA Operating free-air temperature –40 85 °C


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6




(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

(2) The package thermal impedance is calculated in accordance with JESD 51-7.

6.4 Thermal Information

THERMAL METRIC (1)

TS3L501E

UNITRUA (WQFN)

42 PINS

RθJA Junction-to-ambient thermal resistance (2) 30.9 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 12.8 °C/W

RθJB Junction-to-board thermal resistance 5.2 °C/W

ψJT Junction-to-top characterization parameter 0.2 °C/W

ψJB Junction-to-board characterization parameter 5 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 1.5 °C/W

(1) VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs.(2) All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C.(3) ron(flat) is the difference of ron in a given channel at specified voltages.(4) Δron is the difference of ron from center (A4, A5) ports to any other port.

6.5 Electrical Characteristics for 1000 Base-T Ethernet Switchingfor 1000 Base-T Ethernet switching over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V(unless otherwise noted)

PARAMETER TEST CONDITIONS (1) MIN TYP (2) MAX UNIT

VIK SEL, PD VDD = 3.6 V, IIN = –18 mA –0.7 –1.2 V

IIH SEL, PD VDD = 3.6 V, VIN = VDD ±2 μA

IIL SEL, PD VDD = 3.6 V, VIN = GND ±1 μA

IOFF SEL, PD VDD = 0 V, VIN = 0 to 3.6 V ±1 μA

ICC VDD = 3.6 V, II/O = 0, switch ON or OFF 250 600 μA

ICC_PD VDD = 3.6 V, VIN = 3.6 V, PD = high 1

CIN SEL, PD f = 1 MHz, VIN = 0 2.6 3 pF

COFF B or C port VI = 0,f = 1 MHz, outputs open, switch OFF 3 4 pF

CON VI = 0,f = 1 MHz, outputs open, switch ON 9 9.8 pF

ron VDD = 3 V, 1.5 V ≤ VI ≤ VDD, IO = –40 mA 4 8 Ω

ron(flat)(3) VDD = 3 V, VI = 1.5 V and VDD, IO = –40 mA 0.7 Ω

Δron(4) VDD = 3 V, 1.5 V ≤ VI ≤ VDD, IO = –40 mA 0.8 1.5 Ω

(1) VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs.(2) All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C.(3) ron(flat) is the difference of ron in a given channel at specified voltages.(4) Δron is the difference of ron from center (A4, A5) ports to any other port.

6.6 Electrical Characteristics for 10/100 Base-T Ethernet Switchingfor 10/100 Base-T Ethernet switching over recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V(unless otherwise noted)

PARAMETER TEST CONDITIONS (1) MIN TYP (2) MAX UNIT

VIK SEL, PD VDD = 3.6 V, IIN = –18 mA –0.7 –1.2 V

IIH SEL, PD VDD = 3.6 V, VIN = VDD ±2 μA

IIL SEL, PD VDD = 3.6 V, VIN = GND ±1 μA

IOFF SEL, PD VDD = 0 V, VIN = 0 to 3.6 V ±1 μA

ICC VDD = 3.6 V, II/O = 0, switch ON or OFF 250 600 μA

ICC_PD VDD = 3.6 V, VIN = 3.6 V, PD = high 1

CIN SEL, PD f = 1 MHz, VIN = 0 2.6 3.0 pF

COFF B or C port VI = 0,f = 10 MHz, outputs open, switch OFF 3 4 pF

CON VI = 0,f = 10 MHz, outputs open, switch ON 9 9.8 pF

ron VDD = 3 V, 1.25 V ≤ VI ≤ VDD, IO = –10 mA to –30 mA 4 6 Ω

ron(flat)(3) VDD = 3 V, VI = 1.25 V and VDD, IO = –10 mA to –30 mA 0.5 Ω

Δron(4) VDD = 3 V, 1.25 V ≤ VI ≤ VDD, IO = –10 mA to –30 mA 0.8 1.5 Ω


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7




(1) All typical values are at VDD = 3.3 V (unless otherwise noted), TA = 25°C.(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load

capacitance when driven by an ideal voltage source (zero output impedance).(3) Output skew between center port (A4 to A5) to any other port(4) Skew between opposite transitions of the same output in a given device |tPHL – tPLH|(5) Device enable/disable time from PD

6.7 Switching Characteristicsover recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V, RL = 200 Ω, CL = 10 pF(unless otherwise noted) (see Figure 5 and Figure 6)

PARAMETER FROM(INPUT)

TO(OUTPUT) MIN TYP (1) MAX UNIT

tpd(2) A or B/C B/C or A 0.3 ns

tPZH, tPZL SEL A or B/C 0.5 15 nstPHZ, tPLZ SEL A or B/C 0.9 9 nstsk(o)

(3) A or B/C B/C or A 50 100 pstsk(p)

(4) A or B/C B/C or A 50 100 pstON/tOFF

(5) PD A or B/C 250 ns

(1) All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.

6.8 Dynamic Characteristicsover recommended operating free-air temperature range, VDD = 3.3 V ± 0.3 V (unless otherwise noted)

PARAMETER TEST CONDITIONS TYP (1) UNITXTALK RL = 50 Ω, f = 250 MHz, see Figure 8 –37 dBOIRR RL = 50 Ω, f = 250 MHz, see Figure 9 –37 dBBW See Figure 7 600 MHz


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3.5

3

2.5

2

1.5

1

0.5

0

0 0.5 1 1.5 2 2.5 3 3.5 4

V - Input Voltage - VI

R-

On

-Re

sis

tan

ce

-O

NW

-19.97

-29.97

-39.97

-49.97

-59.97

-69.97

-79.97

-89.97

-99.97

-109.971.00E+6 10.00E+6 100.00E+6 1.00E+9 10.00E+9

f - Frequency - Hz

Att

en

uati

on

- d

B

-14

-24

-34

-44

-54

-64

-74

-84

-941.00E+6 10.00E+6 100.00E+6 1.00E+9 10.00E+9

f - Frequency - HzA

tte

nu

ati

on

- d

Bf - Frequency - Hz

Ga

in -

dB

-16

-14

-12

-10

-8

-6

-4

-2

0

1.00E+06 10.00E+06 100.00E+06 1.00E+09 10.00E+09

8




6.9 Typical Characteristics

Figure 1. Gain vs Frequency Figure 2. OFF Isolation vs Frequency

Figure 3. Crosstalk vs Frequency Figure 4. ron (Ω) vs Vcom (V)


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CL

(see Note A)

TEST CIRCUIT

S12 × VDD

Open

GND

RL

RL

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

50 W

VG1

VDD

DUT

50 W

VIN

50 W

VG2 50 W

VI

TEST RLS1 VDCLVDD Vin

tPLZ/tPZL 2 × VDD 200 W GND 10 pF 0.3 V

Input Generator

Input GeneratorVO

tPHZ/tPZH

3.3 V

3.3 V GND 200 W VDD 10 pF 0.3 V

tPZL

VOH - 0.3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VDD/2

VDD/2

Output Control

(VIN) 1.25 V

2.5 V

VOH

VOL + 0.3 V

VOH

VOL

0 V

1.25 V

tPZH

tPLZ

tPHZ

Output

Waveform 2

S1 at GND

(see Note B)

Output

Waveform 1

S1 at 2 VDD

(see Note B)

VOL

VO

VI

VO

9




7 Parameter Measurement Information

7.1 Enable and Disable Times

Figure 5. Test Circuit and Voltage Waveforms


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CL

(see Note A)

TEST CIRCUIT

S12 × VDD

Open

GND

RL

RL

VOH

VOL

VOLTAGE WAVEFORMS

OUTPUT SKEW (tsk(o))

Data Out at

YB1 or YB2

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time, with one transition per measurement.

50 W

VG1

VDD

DUT

50 W

VIN

50 W

VG2 50 W

VI

TEST RLS1 CL

3.3 V ± 0.3 V

VDD Vin

tsk(p)

tsk(o)

3.3 V ± 0.3 V

Open

Open

200 W

200 W

VDD or GND

VDD or GND

10 pF

10 pF

Input Generator

Input GeneratorVO

(VOH + VOL)/2

VOH

VOL

Data Out at

XB1 or XB2(VOH + VOL)/2

3.5 V

1.5 V

Data In at

Ax or Ay2.5 V

tPLHx tPHLx

tsk(o) tsk(o)

tPLHy tPHLy

tsk(o) = t PLHy - t PLHx or t PHLy - t PHLx

VOH

VOL

VOLTAGE WAVEFORMS

PULSE SKEW [tsk(p)]

Output (VOH + VOL)/2

Input 2.5 V

tPLH tPHL

tsk(p) = t PHL - t PLH

3.5 V

1.5 V

VO

VI

VO

10




7.2 Skew

Figure 6. Test Circuit and Voltage Waveforms


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Network Analyzer

(HP8753ES)

EXT TRIGGER

BIAS

P1 P2

DUT

A0

SEL

0B1

VSEL

VDD

VBIAS

CL = 10 pF

(see Note A)

11




Skew (continued)

A. CL includes probe and jig capacitance.

Figure 7. Test Circuit for Frequency Response (BW)

Frequency response is measured at the output of the ON channel. For example, when VSEL = 0 and A0 is theinput, the output is measured at 0B1. All unused analog I/O ports are left open.

7.3 HP8753ES SetupAverage = 4RBW = 3 kHzVBIAS = 0.35 VST = 2 sP1 = 0 dBM


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Network Analyzer

(HP8753ES)

RL = 50 W

EXT TRIGGER

BIAS

P1 P2

DUT

A0

SEL

0B1

VSEL

VDD

VBIAS

A1

1B2

1B1

RL = 50 W

2B1

3B1

A2

A3

0B2

3B2

2B2

12




HP8753ES Setup (continued)

A. CL includes probe and jig capacitance.B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.

Figure 8. Test Circuit for Crosstalk (XTALK)

Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VSEL = 0 and A1 is theinput, the output is measured at A3. All unused analog input (A) ports are connected to GND, and output (B)ports are left open.



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Network Analyzer

(HP8753ES)

RL = 50 W

EXT TRIGGER

BIAS

P1 P2

DUT

A0

SEL

0B1

VSEL

VDD

VBIAS

0B2

A1 1B1

1B2

13




HP8753ES Setup (continued)

A. CL includes probe and jig capacitance.B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.

Figure 9. Test Circuit for OFF Isolation (OIRR)

OFF isolation is measured at the output of the OFF channel. For example, when VSEL = GND and A1 is the input,the output is measured at 1B2. All unused analog input (A) ports are connected to ground, and output (B) portsare left open.



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A0

A1

A2

A3

A4

A5

A6

A7

B0

B1

B2

B3

B4

B5

B6

C1

C2

C3

C4

C5

C6

C7

SEL

B7

C0

LED_A0

LED_B1

LED_B0

LED_A1

LED_A2 LED_B2

LED_C1

LED_C0

LED_C2

PD

Control Logic

POWER DOWN


14




8 Detailed Description

8.1 OverviewThe TS3L501E is a 8-channel SPDT analog switch or 16-bit to 8-bit multiplexer/demultiplexer LAN switch with asingle select (SEL) input and Power Down Mode input. The device provides additional I/Os for switching statusindicating LED signals and includes high ESD protection. SEL input controls the data path of themultiplexer/demultiplexer. Power Down input can put the device into the standby mode for minimizing currentconsumption per mode selection.

The device provides a low and flat ON-state resistance (ron) and an excellent ON-state resistance match. Lowinput/output capacitance, high bandwidth, low skew, and low crosstalk among channels make this device suitablefor various LAN applications, such as 10/100/1000 Base-T. This device can be used to replace mechanicalrelays in LAN applications. It also can be used to route signals from a 10/100 Base-T Ethernet transceiver to theRJ-45 LAN connectors in laptops or in docking stations.

8.2 Functional Block Diagram

Figure 10. Logic Diagram (Positive Logic)

8.3 Feature DescriptionThe TS3L501E device switches and pin out are optimized for ethernet application but the device can used formany applications where a multi-channel, 1:2 SPDT, high bandwidth switch is needed.

8.4 Device Functional ModesThe TS3L501E supports a power down mode which reduces the current consumption of the device and placesall the signal paths in a high impedance state. To place the TS3L501E in power down mode, set the PD pin witha logic high voltage as seen in Table 1.

Table 1. Function TablePD SEL FUNCTIONL L An to Bn, LED_An to LED_Bn

L H An to Cn, LED_An to LED_Cn

H X Hi-Z


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RJ45 Port 1

RJ45 Port 2

SEL

PD

Gigabit Ethernet PHY

Processor TS3L501E

VDD

GND

CN

BNAN

GPIO

GPIO

7 7

7

LED 1

LED 2

LED_BN

LED_CN

LED_AN

2

2

2GPIO


15




9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationThere are many Local Area Network (LAN) applications in which the ethernet hubs or controllers have a limitednumber of I/Os or need to route signals from a single ethernet PHY to multiple ethernet jacks. The TS3L501Esolution can effectively expand the limited I/Os by switching between multiple ethernet jacks to interface them toa single ethernet PHY.

The LED_An, LED_Bn,and LED_Cn pins are rated the same as the other signal path pins so you may use thesepins as extra data paths if needed.

9.2 Typical Application

Figure 11. Typical Application Schematic


http://www.ti.com



f - Frequency - Hz

Gain

- d

B

-16

-14

-12

-10

-8

-6

-4

-2

0

1.00E+06 10.00E+06 100.00E+06 1.00E+09 10.00E+09

16




Typical Application (continued)9.2.1 Design RequirementsEnsure that all of the signals passing through the switch are within the recommended operating ranges. Toensure proper performance, see Recommended Operating Conditions.

9.2.2 Detailed Design ProcedureThe TS3L501E can be properly operated without any external components.

TI recommends that the digital control pins SEL and PD be pulled up to VCC or down to GND to avoid undesiredswitch positions that could result from the floating pin.

Connect the exposed thermal pad to ground.

9.2.3 Application Curve

Figure 12. Gain vs Frequency


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Signal 1

GND Plane

Power Plane

Signal 2

17




10 Power Supply RecommendationsPower to the device is supplied through the VDD pins. TI recommends placing a bypass capacitor as close to thesupply pin (VCC) as possible to help smooth out lower frequency noise to provide better load regulation acrossthe frequency spectrum.

All VDD pins are internally connected. One PCB layout option is to connect one of the VDD to the power supplyand leave the other VDD pins open.

Supply the TS3L501E VDD pins with the recommended voltage before appling a signal voltage to the I/O signalpaths to avoid violating the recommended opperating condition I/O voltage 0-VDD

11 Layout

11.1 Layout Guidelines• TI recommends keeping the high-speed signals as short as possible.• Each via introduces discontinuities in the transmission line of the signal and increases the chance of picking

up interference from the other layers of the board. Be careful when designing test points on twisted pair lines;through-hole pins are not recommended.

• When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. Thisreduces reflections on the signal traces by minimizing impedance discontinuities.

• Do not route traces under or near crystals, oscillators, clock signal generators, switching regulators, mountingholes, magnetic devices or ICs that use or duplicate clock signals.

• Avoid stubs on the high-speed signals because they cause signal reflections. If a stub is unavoidable, thenthe stub must be less than 200 mm.

• Route all high-speed signal traces over continuous GND planes, with no interruptions. Avoid crossing overanti-etch, commonly found with plane splits.

• Due to high-frequency signals, a printed-circuit board with at least four layers is recommended; two signallayers separated by a ground and power layer as shown in Figure 13.

• The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layershould be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the groundor power plane. When running across split planes is unavoidable, sufficient decoupling must be used.Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.

Figure 13. Four-Layer Board Stackup


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9

8

6

7

5

4

3

2

1

17

15

16

14

13

12

11

10

30

31

33

32

34

35

36

37

38

22

24

23

25

26

27

28

29

201918 21

404142 39

Exposed Center Pad

(GND)

To System

To System

To System

To System

To System

To System

To System

To

System

To

System

To

System

To System

To System

To System

To System

To System

To System

To System

To System

To System

To

System

To

System

To

System

To System

To System

To System

To System

To System

To System

To System

To System

To System

To System

To System

To System

To System

To System

VDD

0603

18




11.2 Layout Example

Figure 14. Layout Example


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19




12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related DocumentationFor related documentation, see the following:

Implications of Slow or Floating CMOS Inputs, SCBA004

12.2 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

12.3 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.4 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge CautionThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.


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http://www.ti.com/lit/pdf/SCBA004

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http://www.ti.com/lit/pdf/SLYZ022

PACKAGE OPTION ADDENDUM

www.ti.com 14-Dec-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TS3L501ERUAR ACTIVE WQFN RUA 42 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TK501E

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TS3L501ERUAR WQFN RUA 42 3000 330.0 16.4 3.8 9.3 1.0 8.0 16.0 Q1

TS3L501ERUAR WQFN RUA 42 3000 330.0 16.4 3.8 9.3 1.0 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TS3L501ERUAR WQFN RUA 42 3000 367.0 367.0 38.0

TS3L501ERUAR WQFN RUA 42 3000 358.0 335.0 35.0

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 2

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