IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-32, NO. 3 , MARCH 1985 71 7

I

H I G H V O L T A G E P L A T E ? .. -

T O - 3 h e a d e r l o c a l f i e l d p e r t u r b a t i o n s 1 I &

-- m o n i t o r L t o c u r r e n t

Fig. 4. Experimental configuration used to test response of direct gate devices to external electric fields. A macroscopically uniform field is created in the neighborhood of the device by a pair of parallel plate electrodes. Local perturbations of this field by the chip bonding wires and header structure are empirically absorbed in the value of field transconductance.

A i , i * *

-200 A P P L I E D E L E C T R I C F I E L D

0 200

( k V p e r m e t e r )

Fig. 5. Plot of A i o versus applied external field with VDS = 5 V. The field transconductance A iD /E of the device is seen to be about 0.06 wIFV/m.

tion factor. The plot of A io versus applied macroscopic field, shown in Fig. 5 , was taken with VDs = 5 V, and yields a device “transconductance” of about 0.06 pA/kV/m.

Note that although the test procedure of Fig. 4 exposes the device to an electric field created by a fixed voltage source and conducting electrode, the device should perform equally well when exposed to the electric field of a constant charge distribution. Such a field is typically encountered in studies of charged insulating materials and surfaces, and often in industrial applications were electrostatic charge must be moni- tored, Ultimately, it is the magnitude of the field at the sub- strate surface, whether created by a fixed voltage or fixed charge, that is responsible for modulating the channel current.

Fig. 6 shows a plot of A ~ D versus time when a sudden 100- kV/m step of electrostatic field is applied to the device. This plot may be extrapolated, by noting the slope at t = 0, t o yield the relaxation decay time constant, which in this case is equal to about 35 h.

The device is also sensitive to incident light because its chan- nel is directly exposed through the transparent oxide layer. In our tests, normal room light from 40-W fluorescent bulbs caused 120-Hz drain current modulation, with a peak-to-peak i~ variation comparable to that of about a lO-kV/m field ex- citation. The drain current was also observed to drift with temperature by an amount equivalent to a 10-kV/m field signal per degree Celsius of temperature change.

1 i

0:-1 0

T I M E A F T E R S T E P - (hours) 5 I O 15

Fig. 6 . Plot of A i D versus time when device is subjected to a sudden 100 kV/m step in electric field. Decay time, derived from the slope at t = 0, is seen to be on the order of about 35 h with the device in air at room temperature.

IV. CONCLUSION The direct gate field effect transistor has been demonstrated

as a working device which is capable of sustaining electrostatic field measurements over long periods of time. It thus holds promise as a useful sensor in many field sensing applications.

The problem of oxide layer puncture due to electrosta.tic discharge (ESD), always a concern when MOS devices are used, also may not be a significant one in direct gate devices, since no gate electrode is present to sustain the damaging puncture voltage.

One issue that still must be addressed is the effect on device behavior of any stray mobile ions that may ‘exist in the vicinity of the sensor. Such ions, if allowed to land. on the oxide layer surface, would become fixed charges and yield erroneous elec- tric field signals.

ACKNOWLEDGMENT The author would like to thank Dr. T. Heng of onitrode

Corporation for his role in providing the fa’bricated devices de- scribed in this paper and Dr. A. Mavretic 0.f Boston University for his help in procuring them. R. Desrosiers of Boston Uni- versity assisted with the experimental measurements.

REFERENCES [ 1 J A. J. Schwab, High Voltage Measurement Techniques. Cambridge,

MA: M.I.T., 1972. [2] V. C. Negro, M. E. Cassidy, and R. T. Graves, “A guarded insulat-

ing gate field effect electrometer,” IEEE Tvans. Nucl. Sci., vol. NS- 14, pp. 135-142, Feb. 1967.

[ 31 J. B. McCalsin, “Electrometer for ionization chamber using metal- oxide-semiconductor field effect transistors,” Rev. Sei. Instr., vol. 35, no. 11,pp. 1587-1591,Nov. 1964.

[4] M. Horenstein, “Field effect transistor tracking surface field sen- sor,” Rev. Sei. Instr., vol. 55, no. 2, pp. 222-225, Feb. 1984.

[5] P. E. Secker, “Monitoring systems for electrostatic powder coating plant,” in Electrostatics 1979, Conf. Ser. 48, J. Lowell, Ed. Bris- tol, England: Institute of Physics, 1979, pp. 287-293.

Transient Latchup in Bulk CMOS with a Voltage-Dependent Well-Substrate Junction Capacitance

K. Y . FU

Abstract-Transient latchup in bulk CMOS with a voltage-dependent well-substrate junction capacitance under a voltage ramp is analyzed. It is found that even when the external voltage is ramping up, a1 +

Manuscript received November 9, 1983; revised September 13, 1984. The author was with Inmos Corporation, Colorado Springs, CO

80935. He is now with Motorola, Austin, TX 78721.

0018-9383/85/0300-0717$01.00 0 1985 IEEE

7 1 8 IEEE TFi ANSACTIONS ON ELECTRON DEVICES, VOL. ED-32, NO. 3, MARCH 1 9 8 5

a2 > 1, and both bipolar transistors are biased in the forward-:ictive region, the circuit can still dynamically recover internally due ti, the inherently nonlinear character of the voltage-dependent substratc: well junction capacitance. Numerical results for the cases of linearly g11aded and step junctions are presented and some optimal condition;! for preventing transient latchup are briefly discussed.

INTRODUCTION The latchup resulting from parasitic bipolar transisto;s in

bulk CMOS has usually been characterized by using ' (IC" techniques, such as defining holding current and hol iing voltage. These dc parameters often have vague meanings and are usually indicative of only relative goodness of a circ lit's tolerance to latchup. They are not very useful in charad:I:,iz- ing the transient behavior of latchup. T o describe the transilmt behavior of latchup which occurs in the real circuit operalhn, we need a transient model in which criteria as a functioln of some critical parameters can be defined to predict the latchup susceptibility of a CMOS structure.

Recently, Troutman and Zappe [ 11 have pointed out ' 11at the well-substrate junction capacitance plays an important ,.l>le for the transient behavior of bulk CMOS latchup. The translcnt response to a voltage ramp across the p-n-p-n terminals has been extensively studied in [ 11 by considering a constant wdl- substrate junction capacitance. Assuming a linear vol I age ramp, the authors of [ 11 have defined a critical magnitudl: of the product of the well-substratejunction capacitance(assur;~ed to be constant) and the voltage ramping rate such that 1:lclth bipolar transistors are turned on. If the sum of the com~t~ron base transistor gains (alphas) exceeds unity, the turn-OI:I of both transistors guarantees latchup to occur unless the vola,ge ramp terminates before the breakover current (which is ca.led knee current in [ 11 and is identical to the usual holding 8i:ilr- rent expression) is reached. Therefore, the so-called dyna.rric recovery, according to [ I ] , can be accomplished by exte:;nal means only (e.g., terminating externally applied voltage ramp). The well-substrate junction capacitance, however, is not ccn- stant during the transient. Although the effect of a nonlinear capacitance on triggering an SCR has been briefly discusseti by Gentry et al. [ 21, the dynamic recovery due to the juncl .on capacitance was not discovered by the authors. I t will be shown that the nonlinear well-substrate capacitance must oe included for a complete analysis of the dynamic recovery.

I t is well known that the p-n junction capacitance can. ')e approximated by

where V, is the reverse biased voltage across the p-n junctiirn, Co is the zero-bias depletion capacitance, @bi is the juncti c'n built-in potential, and n is a constant ( n = 3 for a step julno- tion, and 3 for a linearly graded junction. The constant cap81:- itance assumption corresponds to n = 0). Since V, chan,i;cs during the transient period, it is interesting to see how 3k1.e SCR structure responds to an external time-dependent exci :I- tion when this voltage-dependent capacitance is incorporated into analysis.

MODEL This paper extends the recent work of Troutman and Zap ?e

[ 11 to include the voltage dependence of the well-substrille junction capacitance on transient latchup in bulk CMOS. T le bipolar transistors are considered to be ideal piecewise 1int:s.r diodes, which implies no reverse saturation current and in abrupt turn-on at forward-active emitter-base bias, wj I:h constant transistor gains a1 and ( ~ 2 . The shunting resistances between bases and emitters are defined by R 1 and R 2 , respcic- tively, as shown in Fig. 1. In our discussion, for simplicity alalj

Fig. 1. Lumped element equivalent circuit of bulk CMOS parasitic bipolar transistors under an external voltage ramp.

without loss of generality, R i > R2 is always assumed. This implies that the transistor Ql is always the first to turn on, When the transient current exceeds11 = Veb/R1 (where Veb is the forward emitter-base bias that the transistor starts to act in the forward-active region), the transistor Ql turns on. When the transient current exceeds 1 2 = Veb/R2, both transis- tors turn on.

Let t = 0 be the time that the voltage sourceE(t) is applied. We then have E( t ) = K t (where K is the ramp rate). Consider- ing the different operation regions with and without the tran- sistors turning on, a differential equation describing the tran- sient behavior of the terminal current can be obtained by inspecting the equivalent circuits

E ( t ) - Ir(R1 +R2 +R,) l - n

1 - n d t @bi 1 = (a1 i + i0)IZ ( 2)

with the quantities a l , r, and io defined in Table I for the three distinct operating regions of the SCR structure. Equa- tion ( 2 ) can be rewritten in terms of dimensionless variables and parameters as

-- 1)o dx 1 - n d T

= a l i +io, (n f 1).

The dimensionless variables are defined by

E(t) - Z ( t ) r(R1 + R2 + R,)

@bi

i = - I ( t> 1 2

t T =

Co(R1 +R2 +Rx)' Since the dimensionless current i is defined in units of Z 2 , when i > 1 both transistors are on. The dimensionless param- eters are defined by

@bi rlo =

12(R1 +R2 +Rx)

COK 1 2

IC=-

For the case when n = 0, (3) can be reduced to a linear ordi- nary differential equation, which can be solved in closed form [ 1 1 . For n # 0, however, no closed-form solution can be ob- tained for (3). A numerical method is, therefore, invoked. Since n, as a parameter, can be installed in the numerical pro- gram as a variable, the different cases corresponding to dif- ferent types of junctions can be treated on an equal footing in the numerical approach.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-32, NO. 3, MARCH 1985 719

TABLE I

When Neither *en Both When Q1 Transistor Is On Transistors Are On "urns On

I I I

a1 I 1

1 I I

0 2 4 6 8 10 DIMENSIONLESS TIME T

Fig, 2. Dimensionless transient terminal current i versus dimensionless time T for curve (1) n = 0; curve (2) n = f ; and curve (3) n = 1. Parameter values used are: a1 = 0.21, a2 =.0.8, K = 1.6, R1 = 10 kn, Rz = 5 kn, R, = 1 kn, and CO = 100 fF.

NUMERICAL RESULTS For comparison, the numerical calculation has been done by

using some circuit parameters for n = 0, 4, and 3, correspond: ing to a constant, linearly graded, and step-junction capaci- tance, respectively. Figs. 2 and 3 show the numerical result by using Veb = 0.4 V, R1 = 10 kL2, R z = 5 kL2, R, = 1 kL2, a1 = 0.21, az = 0.8, Co = 100 fF, and K = 1.6. Fig. 2 illustrates the transient current as a function of time. It can be seen that, at K := 1.6, the current continues to increase exponentially after both transistors turn on (i > 1) for n = 0. For n = 3 and n = i1 however, the current starts to decrease after reaching a maximum (>1) even when the external voltage still pumps. This is because when n # 0 the well-substrate junction capaci- tance decreases as the reverse biased voltage across the junc- tion increases. The transient coupling due to the capacitance is, therefore, reduced and the transient current can decay even if the external voltage continues to ramp up. The dynamic recovery, according to this analysis, can be accomplished in- ternally within the SCR structure itself (i.e., latchup does not necessarily occur under the condition of a1 + a2 > 1 even when the external voltage is still ramping up). The corre- sponding I-V characteristics are shown in Fig. 3. The voltage value of the external voltage source will eventually establish itself across the well-substrate junction for n # 0 as the curfent diminishes.

If the ramp rate of the external supply is large enough, latchup, of course, can still occur for the case of nonlinear junct.ion capacitance. This is illustrate in Figs. 4 and 5 for the case of a step junction ( n = 3). Except for al = 0.03 and az = 0.99, all parameters remain the same as the previous calcula- tion. As K increases from 1.8 to 2.2, the transient current curves are shifting up. The transient current decays eventually for H: < 2.04, while it runs away and latchup occurs for K > 2.12,. Fig. 5 shows when the circuit latches, I-Vcurves "break-

0 5 I O 15 20 DIMENSIONLESS VOLTAGE V(t)/#bi

Fig. 3. Dimensionless transient terminal current i versus dimensionless voltage V/@bi for curve (1) n = 0; curve (2) n = f ; and (3) curve n = 1. Parameter values are identical to those in Fig. 2 .

._ 501 I /

0 2 4 6 8 10

DIMENSIONLESS TIME T

Fig. 4. Dimensionless transient terminal current i versus dimensionless time Tat different ramp rate for a step well-substrate junction (n = 1). Parameter values used are: a1 = 0.03, a2 = 0.99, R1 = 10 kQ, Rz = 5 kn, R, = 1 kn. Curve (1) K = 1.8, curve ( 2 ) K = 1.88, curve (3) K = 1.96, curve (4) K = 2.04, curve ( 5 ) K = 2.12, and curve (6) y = 2.20.

3 8ol 60 v)

9 z 4 0 1

\ '\

0:O 2.5 5.0 . . 7.5 10.0 12.5 15.0

DIMENSIONLESS VOLTAGE V(t'J@bi

Fig. 5 . Dimensionless transient terminal current i versus dimensionless voltage VI&; for conditions identical to those in Fig. 4. over" at-points IK = (a l I1 + azIz)/(al +.az - 1). This can ., . I V '

7 20 IEEE TI! ANSACTIONS ON ELECTRON DEVICES, YOL. ED-32, NO. 3, MARCH 1985

( 5 )

< 0.0 0.2 0.4 0.6 0.8 1 .o

dl

Fig. 6. Region of CoK product defining the internal dynamic reco 7t:ry for a linear graded junction (n = i), Resistance values used are ill3n- tical to those in other figures. Curve (1) 012 = 1.0, curve (2) 012 = S.8, curve (3) a2 = 0.6, curve (4) a2 = 0.4, and curve (5) a2 = 0.2.

be mathematically proven from (3) by using the condiTim d x / d T = 0. This is exactly a same conclusion as that descri jed in [ 1 1 . As I > I k , the current becomes so large that the bi- polar amplification itself is not sufficient to support the I, ur- rent. The depletion region in the junction capacitance be!.ins to discharge in order t o supply the required current. ‘]‘he depletion region, therefore, shrinks and the reverse bislisd voltage across the junction decreases. This is the way that :he “breakover” happens in the transient response of the circuil ,

We have tried to obtain numerically a condition that demin- eates the occurence of internal dynamic recovery as a funcli on of a1 and 0 1 ~ . One typical result for this is shown in Fig. 6 f x the case of a linearly graded junction. The straight line in I ‘lg. 6 shows C o K , the product of zero-biased junction capacita \ne and voltage ramp rate, as a function of a1, above which b a bh transistors turn on. The curves for different values of Ci2 define the values of C o K , below which the internal dynar~ic recovery can occur. When the sum of transistor gains is lar , ;x than but approaching unity (denoted by a1 + a2 + 1 +), th )%e curves approach infinity asymptotically. This implies tha’ it becomes more and more difficult to latch because of intenla1 dynamic recovery as 0 1 ~ -k a2 -+ l+. It is interesting to see tj .,lt as a1 --f 1, no internal dynamic recovery is possible. In Llis situation, once both transistors are turned on, latchup alw; 1’s occurs, no matter what a2 is, unless, of course, the volt;.~:e ramp terminates before the “breakover” point is reached (i, :., due to the external dynamic recovery). From Fig. 6, one 4: In see that it tends to be more advantageous t o decrease the val ~ ; e of a1 and 0 1 ~ in order to prevent latchup. This assertion is supported by evaluating the derivatives of the holding currt r ~ t with respect to cy1 and ff2. Since R 1 > R 2 , it can be prov :d that 1 aI,/aol, 1 > I aIH/aa2 I. The same conclusion can also ‘ : e drawn by carefully examining difdT. A Aa reduction of # . t i tends to result in a smaller transient current increase thar’ a A@ reduction of 0 1 ~ . Therefore, reducing a1 is more effectj tve in inhibiting latchup than reducing a2.

CONCLUSION The transient response of the parasitic SCR structure in bu !k

CMOS with a voltage-dependent well-substrate junction capllc- itance to an external voltage ramp has been analyzed. T It: major conclusions we found are summarized as follows:

1) The bipolar transistors in SCR structures can turn c j l f after they have been turned on under an external voltage ran 1) due to the nonlinear character of the voltage dependent we 1. substrate junction capacitance. We refer to this as the intern 11 dynamic recovery.

2 ) The condition having the internal dynamic recovery i:r dependent on both transistor gains. As cy1 + a2 + 1+, the 111. lowable ramp rate goes to infinity. As a1 + 1, no internal d l s r ”

namic recovery is possible.

3) I t is always more advantageous theoretically to reduce 0 1 ~ than to reduce a2 (note that R 1 > R 2 ) in order to prevent latchup. In practice, however, it may be more difficult to reduce a1 than to reduce 012 due to the circuit layout and/or process constraints.

ACKNOWLEDGMENT The authors wishes to express his gratitude to L. Childs,

G. Derbenwick, F. Gnadinger, and R. Sokel for their careful reading of the original manuscript and their comments which have been incorporated into the present manuscript.

REFERENCES [ 11 R. R. Troutman and H. P. Zappe, “A transient analysis of latchup

in bulk CMOS,” ZEEE Trans. Electron Devices, vol. ED-30, pp. 170-179, Feb. 1983.

[ 2 ] F. E. Gentry, F. W. Gutzwiller, N. H. Holonyak, and E. E. von Zastrow, Semiconductor Controlled Rectifier: Principles and Applications of p-n-p-n Devices. Englewood Cliffs, NJ: Prentice- Hall, 1964,pp. 113-117.

A Procedure for Field Implanting a CMOS Isoglanar Integrated Circuit

FRANCIS HARPER

Abstract-A procedure is given which allows the construction of a CMOS, isoplanar integrated circuit with independent and self-aligned field implants, for both PMOS and NMOS regions. A unique feature of this procedure is that only time-tested processing steps conventional to either PMOS or NMOS are used. After a detailed description of the process has been given, design-layout restrictions and physical results are discussed.

INTRODUCTION The initial steps of the industrially accepted procedure for

constructing N or PMOS isoplanar integrated circuits employs the photoresist pattern at the field-masking step to both define the nitride pattern and to block the field implant. The field implant is, therefore, self-aligned to the field pattern and the nitride layer is not required to block this implant. In this manner, it is possible to set the field-inversion voltage at any reasonable value without compromise and to use a nitride layer whose only task is to allow the growth of a local oxidation.

For CMOS integrated circuits, it is generally not possible to follow this sequence of process steps as two separate field im- plants with different ions implanted into different regions are required: phosphorus for the PMOS regions and boron for the NMOS regions. Unfortunately, it is not possible to perform both field implants if a single field mask is used without intro- ducing some compromise [ 11-[ 51. The value of these com- promises can be debated at length; by contrast, our procedure avoids all of these compromises and uses only the industrially accepted steps common to NMOS or PMOS. The process to be described here splits the usual field mask into two parts: an n-field and a p-field mask. Each masking operation, with a nitride etch and a field implant, is then done separately.

THE SPLIT FIELD-MASKING AND FIELD- IMPLANTING PROCEDURE

After a conventional p-well or n-well has been established and the usual isoplanar oxide-nitride layers have been grown and deposited, our procedure requires the following basic steps to

Manuscript received December 12, 1983;revised May 3, 1984. The author is with Western Digital Corporation, Irvine, CA 92714.

OO18-9383/85/0300-~ 1720501 .OO 0 1985 IEEE