Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 6, JUNE 2011 1597

Toward System on Chip (SoC) Development UsingFinFET Technology: Challenges, Solutions, Process

Co-Development & Optimization GuidelinesMayank Shrivastava, Member, IEEE, Ruchit Mehta, Shashank Gupta, Nidhi Agrawal,

Maryam Shojaei Baghini, Senior Member, IEEE, Dinesh Kumar Sharma, Senior Member, IEEE, Thomas Schulz,Klaus von Arnim, Wolfgang Molzer, Harald Gossner, Member, IEEE, and V. Ramgopal Rao, Senior Member, IEEE

Abstract—In this paper, the impact of process/technologyco-optimization on System-on-Chip (SoC) performance usingdetailed 3-D process/device simulations has been studied fornanoscale FinFET devices. We investigated challenges in FinFETdevice optimization and scaling while using standard ion implan-tation process for both overlap and underlap designs. Moreover,an implant-free (IF) complementary metal–oxide–semiconductorprocess is discussed for better scalability with improved perfor-mance. FinFETs designed using this IF process shows a ∼2×improvement in static random-access memory and digital input/output performance. Additionally, a modification to the IF processis proposed, which further helps in achieving an improved logicand analog performance for overall SoC development.

Index Terms—Extremely thin SOI (ETSOI), FinFET, implant-free process, ion implantation and system-on-chip (SoC), processco-optimization, scaling.

I. INTRODUCTION

ANUMBER of nonplanar devices such as FinFETs andnanowire field-effect transistors (FETs) are widely pro-

posed as technology options for sub-20-nm node gate lengths[1], [2]. However, several challenges still remain for ultralarge-scale integration of these devices [3]–[5]. Underlap FinFETdevices particularly have better short-channel performance andhigher drive currents at gate lengths below 20 nm, comparedwith the overlap devices [6]–[9]. Recently, it was proposedthat system-on-chip (SoC) implementations will be a key re-quirement for reduced cost, size, and power while enjoyingbetter performance in technologies below 20-nm node [10]–[13]. Therefore, novel devices need to meet the logic, sta-tic random access memory (SRAM), analog/radio frequency(RF), high voltage, and input/output (I/O) requirements, which

Manuscript received October 17, 2010; revised January 2, 2011 andFebruary 18, 2011; accepted February 18, 2011. Date of publication April 7,2011; date of current version May 20, 2011. The review of this paper wasarranged by Editor D. Esseni.

M. Shrivastava is with Intel Mobile Communications, Hopewell Junction,NY 12533 USA (e-mail: [email protected]; [email protected]).

R. Mehta is with Purdue University, West Lafayette, IN 47907 USA.T. Schulz, K. von Arnim, W. Molzer, and H. Gossner are with Intel Mobile

Communications, 80336 Munich, Germany (e-mail: [email protected]; [email protected]).

V. R. Rao, S. Gupta, N. Agrawal, M. S. Baghini, and D. K. Sharma arewith the Indian Institute of Technology Bombay, Mumbai 400076, India(e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2011.2123100

Fig. 1. (a) Standard process flow of the 3-D FinFET device with ion implanta-tion [16]. (b) FinFET device realized from 3-D process simulation with MonteCarlo implants. The process parameters after device calibration are given inTable I. A single metal work function was used, as reported in [16]. AR = 3was taken for all studies.

are the key building blocks of any SoC design. Further-more, process co-optimization was also proposed for SoCdevelopment [14], [15], although not much is reported untildate for FinFET devices from a SoC point of view. Keepingthese objectives in mind, for the first time, we have bench-marked different FinFET processes and studied the impactof process/technology co-optimization on SoC performanceusing detailed 3-D process/device simulations. We investigatedthe scaling behavior and challenges in using a standard ionimplantation process for overlap and underlap FinFET devicedesign and have proposed several solutions in this paper.

This paper is arranged as follows: Section II describes 3-Ddevice and process calibration. Design and optimization ofFinFET device using an ion implantation process is discussedin Section III-A, whereas the challenges in designing underlapdevices are discussed in Section III-B. An implant-free (IF)complementary metal–oxide–semiconductor (CMOS) processis discussed for better scalability with improved performancein Section III-C. In Section III-D, we have shown that FinFETsdesigned using this IF process can achieve a ∼2× improvementin SRAM and digital I/O performance. Additionally, a modifi-cation to the IF process (M-IF) is proposed, and its impact onthe overall SoC development is discussed in Section III-D–F.

II. DEVICES AND SIMULATION SETUP

Fig. 1(a) shows a standard process flow for a 3-D FinFETdevice with ion implantation process for source/drain (S/D) and

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1598 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 6, JUNE 2011

Fig. 2. Calibration of TCAD models for 3-D drift diffusion transport (consid-ering quantum corrections) with experimental data [16]. A well-calibrated 3-Dprocess simulation deck was used with Monte Carlo implants. The device’sdimensional parameters were taken from [16]. The process parameters afterdevice design are given in Table I.

TABLE IOPTIMIZED PROCESS, DIMENSIONAL AND ELECTRICAL

PARAMETERS FOR DEVICE CALIBRATION

EXT region doping [16], whereas Fig. 1(b) shows a FinFETdevice realized using 3-D process simulations. A well-calibrated 3-D process simulation deck was used with MonteCarlo implants (atomistic simulations) for this paper [17].Fig. 2 shows the calibration of technology computer-aideddesign (TCAD) model parameters for drift-diffusion transportconsidering quantum corrections at the oxide-silicon channelinterfaces, which are carefully matched with the experimentaldata [16]. Dimensional device parameters were taken from [16].Process, dimensional, and electrical parameters after devicecalibration are given in Table I. The channel in FinFET is onthe sidewall of the fin that lies on a (110) plane if the deviceis fabricated on a wafer having orientation (100). Due to thedissimilar effective mass values along the various axes, holemobility in FinFET gets enhanced, and electron mobility getsdegraded, compared to conventional planar devices with (100)surface orientation [18]. Sidewall roughness, stress, and strainalso affect the mobility. Since the default model parameters of

Fig. 3. Impact of LG and WFIN scaling on IOFF for (a) PMOS and(b) NMOS devices, which were designed using the standard ion implanta-tion process. Aspect Ratio (AR) = 3 was taken for all the process/devicesimulation studies. EXT and S/D implant energy were scaled while scalingWFIN and HFIN, respectively. Common process parameters were dominatedby NMOS while optimizing the process for leakage current considerations(< 100 nA/μm).

the device simulator are for the (100) plane, mobility modelparameters have been modified for the (110) plane. The valuesof model parameters were then extrapolated to 16-nm LG de-vices, as described in [19]. The contact resistivity value chosenfor all simulations is 2.4 × 10−8 Ω cm2. A single metal workfunction was used as reported in [16]. Aspect Ratio (AR) = 3was taken for all 3-D process and device simulation studies. Allthe 3-D and layout parasitics are captured in simulation studies,as discussed in [20] and [21].

III. RESULTS AND DISCUSSION

A. Standard Ion Implantation Process: Challenges in FinFETDevice Scaling Down to 16-nm Node

Before we start the discussion on the process window andoptimization challenges, it is worth mentioning that devices inthis study are designed and scaled based on a constant leakagecurrent criterion. This means that the leakage current is kept inthe same low range, even when devices were scaled from 25 nmdown to 16 nm.

Fig. 3 shows the IOFF trends with a reduction in the finthickness (WFIN) when the channel length (LG) is scaled from

SHRIVASTAVA et al.: TOWARD SOC DEVELOPMENT USING FINFET TECHNOLOGY 1599

Fig. 4. Impact of LG and WFIN scaling on ION for (a) PMOS and (b) NMOSdevices, which were designed using the standard ion implantation process.ION degrades while scaling WFIN, whereas the inset shows that there is noimprovement in ION with LG scaling.

25 nm down to the 16 nm. Aspect Ratio (AR) = 3 was takenfor all the process/device simulation studies. Extension and S/Dimplant energy was scaled in the same proportion while scalingWFIN and HFIN. Fig. 3(a) shows orders-of-magnitude increasein leakage current while scaling the channel length down to16 nm. This behavior is consistent for all the fin widths andfor both n-channel metal–oxide–semiconductor (NMOS) andp-channel metal–oxide–semiconductor PMOS devices. It alsoshows that PMOS has a stronger dependence on WFIN, andIOFF can easily be controlled by a WFIN reduction. However,the effect of fin width on the leakage current in the NMOS[Fig. 3(b)] device is found to be weaker. This behavior wasattributed to a fixed (and below mid gap) metal work function(φm) for both the NMOS and PMOS devices. However, on onehand, this trend can become identical for both devices by usingtwo different metals with different φm. On the other hand, usingtwo different gate metals for NMOS and PMOS will lead to anincreased process complexity. In this paper, we will use a singlegate metal work function for further discussions/optimization.

Moreover, we found that (Fig. 4) the improvement in ON

current significantly drops for shorter channel length deviceswhile scaling WFIN at the same time. The inset of Fig. 4(a)and (b) shows that, for a given IOFF (∼100 nA/μm), thereis no improvement in ION with channel-length scaling. Thisbehavior can be attributed to a tradeoff between the very high

Fig. 5. CBE profile along the channel while VG was increased from 0 → 1 V.One can notice a barrier due to ID drop across the extension region resistance.

S/D extension region resistance (Fig. 5), which degrades theON current and a tight process window available to meet theleakage criterion. Fig. 5 shows that the conduction band energy(CBE) consistently falls in the channel region while increasingVG from 0 → 1 V, showing good control of gate over channel.However, a rise in the drain current at higher values of VG leadsto a potential drop across the source extension region. Thiscauses a barrier at source side, leading to a weak improvementin ION (at high VG).

Furthermore, Fig. 6 shows the delay calculated from (a)C · V/I and (b) propagation delay, i.e., 3-D “inverter-driving-inverter” (Fan-out = 1) simulation. On one hand, it shows a5× higher propagation delay, compared to C · V/I delay. Thishuge difference is due to the inappropriate use of C · V/I forbenchmarking the device performance. This is because C · V/Icalculation cannot capture C and I as a function of VG/VD,overshoot/undershoot effects, and settling time. It is worthmentioning that C · V/I calculation shows a better match whenS/D resistance is negligible, whereas, for the present case wherethe S/D resistance is high, it leads to a 5× difference in thepredicted values. On the other hand, the inset of Fig. 6(b) showsno improvement in propagation delay with channel-length scal-ing (for constant cell leakage current). This is attributed to nochange in 3-D parasitic capacitance and higher S/D extensionresistance, leading to no further improvement in ON currentwhile scaling the channel length of the device.

B. Underlap FinFET Device Design Challenges

It is important to study the process window for design andoptimization of underlap FinFETs. Fig. 7 shows the impact ofintroducing underlap (UND) [6]–[9] on the device’s electricalperformance. This study was done for both NMOS and PMOSdevices for varying dielectric permittivity of high-κ spacer(KHigh−κ) material and for varying values of LG. In Fig. 7, onecan notice a consistent fall in the leakage current (by orders ofmagnitude) and on current (on the linear scale) with increasingunderlap length. This behavior is consistent for both NMOSand PMOS devices, different KHigh−κ, and different chan-nel lengths. Moreover, ON and OFF current trends follow the


Fig. 6. Impact of LG and WFIN scaling on the delay calculated from(a) CV/I and (b) 3-D “inverter-driving-inverter” simulation. (b) Significant im-pact of S/D and EXT region resistance. The inset of (b) shows no improvementin delay while LG scaling.

Fig. 7. Impact of introducing underlap (UND) [6]–[9] on the (a)–(c) NMOSand (d)–(f) PMOS device’s electrical performance using the standard process.For WFIN relaxation, UND = 6 nm was chosen for fin width relaxation.

standard theories about the underlap FinFETs, as discussed in[6]–[9]. However, the ION/IOFF trend is completely differentfrom the trends discussed in previous work [9]. Since leakagecurrent is orders-of-magnitude lower for a given UND, finwidth (WFIN) can be significantly relaxed in order to improvethe ON current while keeping the OFF current in the acceptable

Fig. 8. Impact of fin width relaxation (for UND = 6 nm) on the device’selectrical performance. It shows that the rise in IOFF is faster that ION. Figs. 7and 8 shows that introducing any combination of high-K spacer, underlap, andWFIN relaxation does not give a performance improvement over the overlapdevice designed from the standard ion-implantation FinFET process. This isattributed to high EXT region resistance.

range. For WFIN relaxation, UND = 6 nm was chosen. Fig. 8shows that the WFIN relaxation for a given UND leads to afaster rise in IOFF, compared to ION for both NMOS andPMOS devices. Figs. 7 and 8 show that introducing any com-bination of high-κ spacer, S/D underlap, and WFIN relaxationis not expected to give a significant performance improvementover the overlap device, which was designed from standard ion-implantation FinFET process. Even when the carrier mobilitygets improved due to WFIN relaxation, a weak improvement inION (at high VG) is attributed to high EXT region resistance, asdiscussed in Fig. 5. One can argue that, for the underlap device,another process condition [i.e., Lightly Doped Drain (LDD)dose, energy, and anneal time] may improve its performancewithout showing the trend discussed in Figs. 7 and 8. Atthis stage, it is worth mentioning that further tuning of LDDdose, energy, and anneal time by ±50% improves the underlapdevice’s ION by ∼10%, which, at the same time, leads to a ∼2×higher OFF current (data not shown here).

C. IF Process: Solution Toward a Robust FinFET Design

Until now, we studied the ion implantation process windowfor FinFET devices with its associated challenges. In orderto overcome the FinFET design constraints, for the first time,we propose an ion IF process for FinFET devices. Note thata similar process is previously discussed for extremely thinplaner SOI devices [13], [22]. Fig. 9 shows the IF processflow for the 3-D FinFET device. It is similar to the previ-ously discussed (i.e., ion implantation) process, except the S/Ddoping technique. The IF process consists of an in situ-dopedepitaxial growth after the Spacer-1 formation, followed by arapid thermal processing (RTP). RTP helps in diffusing thedopants from the epitaxial region to the S/D and extension


Fig. 9. IF process flow for the 3-D FinFET device used to realize the IF device.Parameters for optimization are given in Fig. 10.

Fig. 10. DOE for IF FinFET device. Optimized process parameters are shownin the figure. The inset shows that the IF device has very high parasiticcapacitance, compared with the device realized from the standard process.

regions. Moreover, Spacer-2 was not used for this process,unlike the standard ion implantation process.

Fig. 10 shows the design of experiment (DOE) prepared forthe IF FinFET device design for LG = 16 nm. The range ofparameters taken for the optimization (i.e., WFin, RTA time,φm, KSpacer−1, and Spacer-1 thickness) and optimized processparameters are also shown in Fig. 10. The inset shows thatthe IF device has an improved ION (for IOFF ∼ 10 nA/μm)although it suffers from a very high parasitic capacitance,compared to a device realized using a “Standard” (i.e., ionimplantation) process, which is due to the higher gate-to-S/Dcoupling. It is worth mentioning that Spacer-1 was kept (fromthe D.O.E) 4 nm, and there was no Spacer-2 used for thisprocess. This gives rise to an increased coupling between theS/D and gate, eventually leading to a very high contributionof 3-D coupling/parasitic capacitance. A detailed discussionon various 2-D/3-D capacitive components of different planarand nonplanar devices is reported in [20]. In order to reducethe 3-D parasitic capacitance while achieving similar ION

improvements, a modified IF (M-IF) process flow was proposedfor the 3-D FinFET device (Fig. 11). The M-IF process consistsof two epitaxial growths: one for the extension region and theother for the S/D region. Moreover, it also consists of an ad-ditional spacer (Spacer-2) process. The optimized process anddimensional and electrical parameters for all three processes fora LG = 16 nm device are given in Table II.

On one hand, Fig. 12, shows that, compared to a “Standard”process, the devices realized from the IF and M-IF processes

Fig. 11. M-IF process flow proposed for the 3-D FinFET device in order toreduce the 3-D parasitic capacitance while achieving improved ON currents.

TABLE IIOPTIMIZED PROCESS, DIMENSIONAL AND ELECTRICAL PARAMETERS

FOR ALL 3 PROCESSES FOR A DEVICE HAVING LG = 16 nm,EOT = 1.1 nm, WFIN = 7 nm, HFIN = 21 nm, AND TEPI = 20 nm

Fig. 12. I–V characteristics of devices realized from all three processes. Theinset compares the ION, IOFF, and parasitic capacitances for the optimum de-vices realized from all three FinFET processes. CGD−3D is the 3-D overheadcapacitance.

have a 50% and 25% higher ION, respectively. On the otherhand, as can be seen from the inset in Fig. 12, the standardand M-IF processes have similar 3-D parasitic capacitances,whereas the M-IF process has a 3× lower 3-D parasitic ca-pacitance, compared with the IF process. This behavior (i.e.,improved ION and lower 3-D capacitance) can be attributed


Fig. 13. Source-to-drain doping profile in (a) NMOS and (b) PMOS devicesrealized from the Standard, IF, and M-IF processes. The standard process hashigher dopant diffusion due to ion implantation, whereas the IF and M-IFprocesses produce steep junction profile. PMOS shows a slightly graded profiledue to boron diffusion.

to the steep S/D-to-channel junction profile (Fig. 13) and thelower S/D-to-gate coupling capacitance. Fig. 13 compares thesource-to-drain doping profile in (a) NMOS and (b) PMOSdevices realized from the Standard, IF, and M-IF processes. TheStandard process has a higher dopant straggle, whereas the IFand M-IF processes produce steep junction profiles, giving riseto improved device performance. A higher dopant straggle takesplace due to the ion implantation process and thermal anneal fordopant activation. Doping profiles extracted from the IF and M-IF processes show that thermal anneal does not have a signifi-cant contribution to the dopant straggle or out diffusion. Fig. 13shows that it is the ion-implantation-driven dopant diffusion,which is responsible for the narrow process design windowfor the conventional (ion implantation based) FinFET devices.Furthermore, an intrinsic or undoped fin causes a pronouncedeffect of dopant straggle in the channel region. PMOS devicesfrom the IF process [Fig. 13(b)] show a slightly higher dopantstraggle, compared to the NMOS devices, which is becauseof the slightly higher diffusion of boron, compared to arsenicduring the thermal anneal. Moreover, it can also be seen thatthe extension region doping in IF and M-IF devices is higher,compared to the device realized from the Standard process. Thiseventually leads to a lower extension region resistance in IF andM-IF devices, as shown in Figs. 14 and 15.

The CBE profile (Fig. 14) for the M-IF device shows nobarrier at the source side (while increasing VG from 0 → 1 V),which is due to the lower extension region resistance. Similarcharacteristics were observed for the IF device (as well as forthe PMOS devices). Furthermore, Fig. 15 shows the extensionregion resistance extracted using the technique discussed in[23]. It shows a significantly lower S/D resistance for theIF device, compared to the devices realized from a standardprocess. It can also be seen that the gate fringe capacitanceplays a significant role in devices realized from the Standardprocess. However, gate fringe capacitance has no impact ondevices realized from the IF process.

D. Logic and SRAM Performance-

For self-loaded circuits (where CINT is negligible), Fig. 16shows a significantly lower (40%) propagation delay (τD)in the M-IF device, compared to devices realized from theStandard and IF processes. For the case where interconnect

Fig. 14. CBE profile for the M-IF device along the channel while VG

was increased from 0 → 1 V. There is no barrier due to lower EXT regionresistance. Similar characteristics were seen for the IF device (as well as PMOSdevices).

Fig. 15. IF device shows a significantly lower S/D resistance, compared witha device realized from the Standard process.

Fig. 16. M-IF device shows a significantly lower inverter delay, comparedwith the IF device and device realized from the Standard process.

capacitance dominates (CINT = 2 fF), the IF device showsa significant delay improvement (50%), compared to otherdevices, which is due to its higher ION. It was found that, for agiven delay value achieved from the Standard process, VDD canbe scaled by 25% for the interconnect dominant and self-loadedcase by using the IF and M-IF processes, respectively.


Fig. 17. (a) 6T SRAM cell and various capacitive components, which lead toa loading over bit line. (b) Bit-line capacitance calculated for 1024-cell SRAMdesigned using the Standard, IF, and M-IF processes [20].

Fig. 18. Read time comparison. The IF device shows higher (but still accept-able) read times, due to higher bit-line capacitance.

Fig. 17(a) shows a 6T SRAM cell and various capaci-tive components, which contribute to a loading over bit line.Fig. 17(b) shows the bit-line capacitance (calculated from pre-dictive technology model [21]) of a 1024-cell SRAM designedusing the Standard, IF, and M-IF processes [20]. The IF devicewas found to have a higher (but still acceptable) read times(Fig. 18), due to the larger loading over the bit line. However,the IF process was found to have a significantly improved StaticNoise Margin (SNM) performance, compared to other devices.The Standard process leads to a seriously degraded SNM values(below 10% of VDD). Figs. 16–19 show that the M-IF device isan excellent option for self-loaded (CINT ∼ 0) logic circuits,whereas the IF device is an excellent option for SRAMs anddigital I/O’s.

E. Analog Performance

Traditionally, the analog performance of FET devices is pre-dicted by using standard figures of merit such as transconduc-tance/output resistance/cutoff frequency. Fig. 20 compares thetransconductance (GM ) and output resistance (RO) for all thethree devices. On one hand, it shows that the transconductanceof a standard device is lowest, compared to the other two de-vices, mainly because of the higher extension region resistancein these devices. On the other hand, the output resistance ofa standard device is highest, compared to the IF and M-IFtransistors at smaller gate-overdrive voltages, which howeverconverges to the same value for all the devices at higher gate-

Fig. 19. Butterfly curves for the SRAMs designed (β = 1 & 2) from devicesusing the (a) Standard, (b) IF, and (c) M-IF processes. (d) Compares the SNMand VDD scaling trends for SRAMs designed using different processes. TheIF process was found to have the best SNM performance (with acceptable readtime), whereas the standard process lead to seriously degraded SNM values.

Fig. 20. (a) Transconductance: GM and (b) output resistance RO w.r.t. gateoverdrive for devices realized from the standard, IF, and M-IF processes.

overdrive voltages. Because of such dynamic trends, it becomesdifficult to extrapolate the final analog/RF circuit performanceusing figures of merit such as GM or RO. In order to make ac-curate comparisons for the devices’ analog circuit performance,we studied a standard two stage OPMAP circuit. Using such acircuit, one can more easily account for all the dynamic figuresof merit.

Fig. 21(a) shows a two-stage OPAMP designed and studiedto compare the analog performance of each of the three de-vices. The OPAMP was designed for unity gain bandwidths(UGBs) of 200, 400, 600, 800, and 1000 MHz considering aphase margin above 75◦ for all cases. The designed OPAMPSwere compared for performance parameters such as voltagegain, output voltage swing, power dissipation, common-moderejection ratio (CMRR), slew rate, settling time, and area. AllOPAMPS were designed for power supply (VDD) = 2 V, loadcapacitor (CL) = 1 pF. A supply voltage of 2 V was chosento achieve enough UGB. It is worth mentioning here that allthe three devices (both PMOS and NMOS transistors) have ajunction breakdown voltage above 2.75 V. To ensure a highstability and, specifically, a good large signal settling time (noringing at all), compensation capacitor was fixed at a valuesuch that the phase margin for all designs was above 75◦. Thisalso ensures that performance parameters were not affected by


Fig. 21. (a) Two-stage OPAMP designed for different UGBs and studied tocompare the analog performance. (b)–(i) Various figures of merit of an OPAMPcircuit. Overall, the M-IF device was found to have improved performance,compared with the IF device and a standard device.

the load capacitor as it was observed from simulation results.Since the designs are aimed for high-speed applications, a largesignal settling time is of importance. Moreover, OPAMPS weredesigned for a constant input capacitance. Therefore, power andarea were traded for high slew rates and better speeds.

Now, for the preliminary design of the OPAMP, the tailcurrent I5 was approximated on the basis of a nominal slew rate.Based on this value of I5 and UGB requirement, the aspect ratio(or, equivalently, number of fins) of M1 (M2) were calculated.The choice of input common-mode levels then allows us to fixsizes of M3 (M4) and M5. The required phase margin puts upa constraint on the transconductance of M6, which, along withproper mirroring conditions, gives us the size of transistor M6.I6, which is the bias current of M6, in turn, fixes up the aspectratio of M7, thereby completing the design process for a givenUGB. Since the UGB is proportional to I5, it can be increasedby increasing the aspect ratio of M5 and, consequently, M7(keeping the aspect ratio of other transistors constant).

1) Gain, phase margin, and CMRR: Fig. 21(b) and (c) com-pare the small signal gain and the corresponding phasemargins. It was observed that the gain of the standardand M-IF opamp were almost identical for all designs,whereas the IF opamp’s gain was less than the othertwo at lower frequencies, owing to the lower outputimpedance. As far as the phase margin is considered, itsolely depends on CC and CL. Since the two capacitorswere kept unchanged during the complete design process,the phase margin was found to remain constant for alldesigns using standard and M-IF devices. Moreover, thehigher value of parasitics in the IF devices gives riseto additional poles and, hence, a lower phase margin,which changes with UGB. CMRR was found to be similarfor the OPAMPs designed from all the three devices[Fig. 21(d)].

2) Output swing and power dissipation: The maximum andminimum output swings are limited by M6 and M7,

respectively, going into the triode region. It is evidentfrom Fig. 21(e) that the output swing of the standardopamp is the lowest; however, the opamps designed fromthe IF and M-IF devices show an output swing going allthe way up to VDD. Fig. 21(f) reveals that the powerdissipated by opamp designed using the standard devicewas the highest, whereas it is minimal for both the IF andM-IF process-based designs. This can be explained fromthe “GM ” plot, where, for a given “GM ” (or equivalentlyBW), the current requirement is highest in the standardcase, followed by the M-IF and IF designs.

3) Slew rate and area: Fig. 21(g) and (h) suggest thatopamps designed from the Standard process have thehighest rise and fall slew rate; however, it is minimumfor opamps designed from the IF and M-IF processes.This can be attributed to the highest bias current in thestandard device for a given UGB. On the other hand, theIF process has the highest area requirement for the opampdesigned for any UGB value, compared with the othertwo processes. This can be attributed to its high parasiticcapacitances, which eventually requires higher electricalwidth (i.e., number of fins) of M1, M2, and M7, in orderto meet the desired UGB requirement.

Overall, the M-IF device was found to have an improvedOPAMP performance, compared with the devices realized fromthe Standard and IF processes [Fig. 21(b)–(h)]. Furthermore,the M-IF device also requires a significantly lower (equal)area [Fig. 21(i)], compared with the IF (Standard process)device. Improved performance of M-IF device is attributedto its improved gm and ION, compared with the Standardprocess device, and its lower parasitic capacitance, comparedwith the IF device. These observations recommend using theM-IF device for analog/RF circuits.

F. Device Variability

Fig. 22 shows the variability analysis for FinFET devicesrealized from the Standard and IF processes by varying all thesensitive parameters in Table II in the ±5% range. The IF devicewas found to be better in terms of device variability. The M-IFdevice also has similar trends as that of the IF device (data notshown here).

IV. CONCLUSION

We have investigated challenges, solutions, and technologyco-optimization guidelines for achieving robust FinFET devicedesigns. The Standard ion implantation process for S/D dopinghas been found to lead to serious challenges for technologyscaling below the 16-nm node. It has been found that underlapFinFET design is difficult to optimize by using the standard ionimplantation process, even after further process optimizationfor underlap configuration. An IF process has been investi-gated for aggressively scaled FinFET device designs in thiswork. Furthermore, a modification to the IF process has beenproposed in order to reduce the device’s parasitic capacitancewithout sacrificing on the ION improvements over the standardprocess. Since IF is possible by using the M-IF process withthe use of an extra noncritical mask, Fig. 23 shows a proposed


Fig. 22. Variability analysis for FinFET devices realized from the Standardand IF processes, which is done by varying all the sensitive parameters inTable II in the ±5% range.

Fig. 23. Proposed scheme for SOC designs. The M-IF device is highlysuitable for logic and analog/RF applications, whereas the IF device, whichcan be realized using the M-IF process, shows improved SRAM performancewith better interconnect driving capability and is, hence, suitable for digital I/Oand SRAMs. This is possible by using the M-IF process with the use of an extrabut noncritical mask.

scheme for robust SOC designs. While the M-IF device ishighly suitable for logic and analog/RF applications, the IFdevice shows an improved SRAM performance with betterinterconnect driving capability and is therefore highly suitedfor SRAMs and digital I/O.

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Mayank Shrivastava (S’09–M’10) was born inLucknow, India, in 1984. He received the B.S. de-gree in engineering from Rajiv Gandhi TechnicalUniversity, Bhopal, India, in 2006 and the Ph.D.degree from the Indian Institute of Technology (IIT)Bombay, Mumbai, India, in 2010.

From April 2008 to October 2008 and May 2010to July 2010, he was a Visiting Research Scholar withInfineon Technologies AG, Munich, Germany. From2010 to 2011, he worked for Infineon Technologies,East Fishkill, NY, and now with Intel Mobile Com-

munications, Hopewell Junction, NY, as a Senior Electrostatic Discharge (ESD)Engineer for International Semiconductor Development Alliance. He has pub-lished more than 25 papers in international conferences/journals in the field ofESD, input–output (I/O) devices, fin-shaped field-effect transistors (FinFETs),and nonvolatile memory. He is the holder of eight patent applications. Hiscurrent research interests include ESD- and hot-carrier-degradation-aware I/Odevice design, ESD-aware technology development, FinFET and ultrathin-bodyplanar silicon-on-insulator devices, nonvolatile analog memories, electrother-mal modeling, and simulation.

Dr. Shrivastava served as a Reviewer of the IEEE TRANSACTIONS ON

ELECTRON DEVICES, the IEEE ELECTRON DEVICE LETTERS, and the Jour-nal of Microelectronics Reliability. He was the recipient of 2008 Best ResearchPaper Award in circuit design category from Intel Corporation Asia AcademicForum, the Industrial Impact Award from IIT Bombay in 2010, the biographypublication by the International Biographical Center, Cambridge, U.K., in the2000 Outstanding Intellectuals of the 21st Century in 2010, the Excellence inThesis work for his Ph.D. thesis from IIT Bombay in 2010, and the 2010 YoungInnovator Award from the Technology Review 35.

Ruchit Mehta received the B.Tech and M.Tech.(microelectronics) degrees from the Department ofElectrical Engineering, Indian Institute of Technol-ogy Bombay, Mumbai, India, both in August 2010.He is currently working toward the Ph.D. degree inthe School of Electrical and Computer Engineering,Purdue University, West Lafayette, IN.

His research interests include nanoelectronicand bioelectronic device physics, fabrication, andmodeling.

Shashank Gupta was born in Lucknow, India, in 1986. He received the B.Tech.degree in engineering from the Institute of Engineering and Technology,Lucknow, India, in 2009. He is currently working toward the M.Tech degree(graduating in July 2011) in microelectronics in the Department of ElectricalEngineering, Indian Institute of Technology Bombay, Mumbai, India.

His current research interest includes ultralow-power devices such as tunnelfield-effect transistors (FETs), germanium-based devices, and fin-shaped FETs,technology-aware design; circuit design using emerging devices; and beyondcomplementary metal–oxide–semiconductor devices such as graphene andcarbon nanotube.

Nidhi Agrawal was born in 1987 in Tripoli, Libya, and was brought up inRaipur, India. She received the B.S. degree in engineering from the NationalInstitute of Technology, Raipur, in 2009. She is currently working toward theM.Tech degree in microelectronics in the Department of Electrical Engineering,Indian Institute of Technology Bombay, Mumbai, India.

She is keenly interested in the fields of novel emerging device design andstructure in sub-22-nm-node technology such as tunneling field-effect transistor(FET), quantum-well FET, carbon nanotube, graphene; the physics behind thesenovel structures and their modeling; and technology-aware design.

Maryam Shojaei Baghini (M’00–SM’09) receivedthe M.S. and Ph.D. degrees in electrical engineeringfrom Sharif University of Technology, Tehran, Iran,in 1991 and 1999, respectively.

She worked for two years in the industry on thedesign of analog and mixed-signal very large scaleintegration (VLSI) integrated circuits. In 2001, shejoined the Indian Institute of Technology Bombay,Mumbai, India, as a Postdoctoral Fellow, where sheis currently a Faculty Member. She is the author orcoauthor of 67 international journal and conference

papers and the author of one invited book chapter. She is the holder or coholderof nine patents. Her current research interests include device–circuit inter-action in emerging technologies, high-performance low-power analog/mixed-signal/radio frequency (RF) VLSI design and test, analog/mixed-signal/RFelectronic design automation, power management for systems-on-a-chip, high-speed interconnects, and circuit design with organic thin-film components.

Dr. Baghini serves in program committees of several conferences includingIEEE Asian Solid-State Circuits Conference, IEEE International Conferenceon VLSI Design, and the Asia Symposium on Quality Electronic Design.She was a corecipient of several awards, including the IIT Bombay IndustryImpact Award in 2008, the Best Research Award in circuit design from IntelCorporation Asia Academic Forum in 2008, and the Third-Place Award onresearch and development at the 15th International Festival of Kharazmi in2002. Her team of students won the first Cadence Design Systems Inc. DesignContest among South Asian Association for Regional Cooperation countries in2006 and the runner-up project of the same contest in 2010.

Dinesh Kumar Sharma (M’98–SM’01) receivedthe Ph.D. degree from the University of Bombay,Mumbai, India.

He was with the Solid-State Electronics Groupat the Tata Institute of Fundamental Research from1971 to 1991, except between 1976 and 1978,when he was a Visiting Scientist at Laboratoired’électronique des technologies de l’information,Grenoble, France, and between 1985 and 1987, whenhe was with the Microelectronics Center, ResearchTriangle Park, NC. Since 1991, he has been with the

Department of Electronic Engineering, Indian Institute of Technology Bombay,where he is currently a Professor and the Head of the department. Over the last35 years, he has worked in the areas of metal–oxide–semiconductor (MOS)device modeling, very large scale integration (VLSI) technology development,VLSI digital system design, mixed-signal design, and radio frequency (RF)design. He has also contributed to research in process and device simulation,electrothermal modeling, and characterization of MOS devices. He maintainsclose contact with the microelectronics industry in India. He has designedseveral integrated circuits for the industry and has conducted training coursesfor them in the areas of VLSI technology and design. He has published morethan 50 papers in reputed journals and conferences on these subjects. Hiscurrent interests include RF and mixed-signal VLSI, asynchronous design, andthe effect of technology and device scaling on design architectures and tools.

Dr. Sharma is a Fellow of the Institution of Electronics and Telecommu-nication Engineers (IETE) and serves on the editorial board of Pramana,which is the journal of physics of the Indian Academy of Science. Overthe last few years, he has been also working on manpower training in theareas of microelectronics and VLSI design in India. He has served on severalcommittees within the government, which are trying to improve the generallevel of training in this area. He has also collaborated with the industry andcoauthored a widely quoted report with Dr. F.C. Kohli of Tata ConsultancyService on this subject. He was a recipient of the Bapu Sitaram Award of theIETE for Excellence in Research and Development in Electronics in 2001.


Thomas Schulz received the Dipl.-Ing. and Dr.-Ing. degrees in electricalengineering from the Ruhr-University Bochum, Germany, in 1997 and 2001,respectively.

In 2000, he joined the Corporate Research Nano Device Group, InfineonTechnologies AG, Munich, Germany, working on novel device concepts. Hecontributed in device development projects from 2004 to 2006 at the Inter-national SEMATECH/Advanced Technology Development Facility and from2006 to 2009 at Interuniversity Microelectronics Centre as a Senior StaffEngineer of Infineon Technologies. In 2011, he joined the newly formed IntelMobile Communications GmbH. He is the author or coauthor of over 40publications and is the holder of over 40 patents in device design.

Klaus von Arnim was born in Elmshorn, Germany,in 1975. He received the Dipl.-Ing. and Dr.-Ing. de-grees in electrical engineering from the University ofKiel, Kiel, Germany, in 2002 and 2006, respectively.

From 2001 to 2005, he worked with the ResearchLaboratories of Infineon Technologies, Munich,Germany, where he was active in the fields of high-speed and low-power digital circuit techniques. From2005 to 2007, he was with Interuniversity Micro-electronics Centre, Leuven, Belgium, as a Delegatefor Infineon. In that time and in the following two

years at the Technology Innovation Department in Munich, he work on system-related aspects of novel devices and new materials, such as fin-shaped field-effect transistors and high-k/metal gate stacks. Since 2009, he has beenresponsible for standard cell libraries for wireless applications, with the transi-tion of the wireless division. In 2011, he joined Intel Mobile Communications,Munich.

Wolfgang Molzer, photograph and biography not available at the time ofpublication.

Harald Gossner (M’06) received the Dipl.Phys. de-gree from Ludwig Maximilian University, Munich,Germany, in 1990 and the Ph.D. degree in electricalengineering from the Universität der Bundeswehr,Munich, in 1995.

For 15 years, he worked on the development ofelectrostatic discharge (ESD) protection conceptsfor bipolar, bipolar complementary metal–oxide–semiconductor (CMOS), and CMOS technologieswith Siemens and Infineon Technologies. Re-cently, he has joined Intel Mobile Communications,

Munich, as a Senior Principal Engineer overseeing the development of robustmobile systems. He has authored or coauthored more than 80 technical papersand one book in the field of ESD and device physics. He is the holder of 30patents on the topics mentioned.

Dr. Gossner has served in the technical program committees of InternationalElectron Devices Meeting, the Electrical Overstress/Electrostatic Discharge(EOS/ESD) Symposium, and the International ESD Workshop. He is currentlythe Cochair for the Industry Council on ESD Target Levels. He was the recipientof the best paper award from the EOS/ESD Symposium in 2005.

V. Ramgopal Rao (M’98–SM’02) received theM.Tech. degree from the Indian Institute of Tech-nology (IIT) Bombay, Mumbai, India, in 1991and the Dr.-Ing. degree from the Universitaet derBundeswehr, Munich, Germany, in 1997.

From 1997 to 1998 and again in 2001, he was aVisiting Scholar with the Department of ElectricalEngineering, University of California, Los Angeles.He is currently a Professor with the Department ofElectrical Engineering and the Chief Investigator forthe Center of Excellence in Nanoelectronics, IIT

Bombay. He has over 280 publications in the area of electron devices andnanoelectronics in refereed international journals and conference proceedingsand has 15 patents issued or pending.

Dr. Rao is a Fellow of the Indian National Academy of Engineering, theIndian Academy of Sciences, and the National Academy of Sciences in India.He is a Distinguished Lecturer of the IEEE Electron Devices Society and hasserved on the program/organizing committees of a large number of internationalconferences in the area of electron devices. He was the Chairman of IEEEAP/ED Bombay Chapter from 2002 to 2003 and currently serves on theexecutive committee of the IEEE Bombay Section, aside from being the ViceChair for IEEE Asia-Pacific Regions/Chapters Subcommittee. He is an Editorfor the IEEE TRANSACTIONS ON ELECTRON DEVICES in the complementarymetal–oxide–semiconductor devices and technology area and serves on theEditorial boards of various other international journals. He was the recipient ofthe coveted Shanti Swarup Bhatnagar Prize in Engineering Sciences awardedby the Honorable Prime Minister of the Government of India in 2005 for hiswork on Electron Devices. He was also a recipient of the 2004 SwarnajayantiFellowship Award from the Department of Science and Technology, the 2007IBM Faculty Award, the 2008 Materials Research Society of India AnnualPrize, and the 2009 TechnoMentor Award from the Indian SemiconductorAssociation.

Documents

Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines