5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ALTERA Cyclone V SoC Development & Education Board (DE1-SoC)

CONTENT1 Cover Page

PAGE PAGE CONTENT

23456789

1011121314

Block DiagramFPGA BANK 3, BANK 4FPGA BANK 5, BANK 6FPGA BANK 7, BANK 8FPGA Clocks, GNDFPGA ConfigurationFPGA DecouplingFPGA PowerUSB Blaster IIJTAG ChainGPIO 0GPIO 1SDRAM, HPS QSPI FlashHPS DDR3 SDRAM15

161718192021222324252627282930

ADV7123 VGAADV7180 Video DecoderAudio CODEC7-Segment Display, LEDFPGA BUTTON, SwitchADC, PS2, IR Tx, IR Rx2-port USB Host1 Gigabit EthernetUART to USB, SD CARDAccelerometer, LTC ConnectorI2C Multiplexer, HPS BUTTON, HPS LEDPower - 1.1VPower - 5V, 3.3VPower - 9V, 2.5V, 1.5VPower - 1.2V, 1.8V, DDR3 VREF, DDR3 VTT

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Cover Page F

DE1-SoC BoardB

1 30Thursday, March 09, 2017

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Cover Page F

DE1-SoC BoardB

1 30Thursday, March 09, 2017

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Cover Page F

DE1-SoC BoardB

1 30Thursday, March 09, 2017

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Block Diagram F

DE1-SoC BoardB

2 30Friday, December 19, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Block Diagram F

DE1-SoC BoardB

2 30Friday, December 19, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Block Diagram F

DE1-SoC BoardB

2 30Friday, December 19, 2014

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCCIO = 3.3V

VCCIO = 3.3V

USB_B2_DATA1

USB_B2_DATA2USB_B2_DATA3

USB_B2_DATA4

USB_B2_DATA6

USB_B2_DATA7

GPIO_012GPIO_015GPIO_018GPIO_032LEDR0LEDR1GPIO_013GPIO_014GPIO_09GPIO_04GPIO_031GPIO_022GPIO_011GPIO_010GPIO_034GPIO_020GPIO_08GPIO_05LEDR2LEDR4GPIO_07GPIO_06GPIO_021GPIO_035GPIO_030GPIO_033GPIO_123GPIO_111GPIO_129GPIO_128GPIO_026GPIO_027GPIO_01GPIO_016GPIO_023GPIO_126

GPIO_028GPIO_029GPIO_03GPIO_017GPIO_124GPIO_122GPIO_121GPIO_120GPIO_131GPIO_130GPIO_019GPIO_024GPIO_117GPIO_118GPIO_19GPIO_119GPIO_132GPIO_15LEDR3LEDR5GPIO_113GPIO_116GPIO_115GPIO_114GPIO_025GPIO_133LEDR6GPIO_134GPIO_110GPIO_112GPIO_17GPIO_18GPIO_135GPIO_13GPIO_11GPIO_12

GPIO_125GPIO_127

GPIO_14GPIO_16

SW0

SW1

SW2

SW5

DRAM_ADDR10

DRAM_ADDR12DRAM_ADDR0

DRAM_DQ0

DRAM_DQ2DRAM_DQ3

DRAM_DQ12

DRAM_DQ4

DRAM_DQ9

DRAM_DQ6DRAM_DQ7

DRAM_DQ8

DRAM_DQ5

DRAM_DQ10

DRAM_DQ11

DRAM_DQ1

DRAM_DQ13

DRAM_DQ14

DRAM_DQ15

DRAM_ADDR6

DRAM_ADDR4

DRAM_ADDR8

DRAM_ADDR1DRAM_ADDR11

DRAM_ADDR9

DRAM_ADDR2

DRAM_ADDR3

DRAM_ADDR5

KEY1KEY0

DRAM_DQ[15..0] 14

KEY[3..0] 6,20

DRAM_ADDR[12..0] 6,14

USB_SDA 10

USB_B2_DATA[7..0] 7,10

USB_B2_CLK 10

USB_RESET_n 10

USB_EMPTY 10

USB_FULL 10USB_WR_n 10

USB_RD_n 10USB_OE_n 10

USB_SCL 10

GPIO_0[35..0] 6,12

GPIO_1[35..0] 6,13

SW[9..0] 7,20

LEDR[9..0] 4,19

FAN_CTRL 7

DRAM_CAS_N14DRAM_CS_N14

DRAM_RAS_N14DRAM_BA014

DRAM_UDQM14DRAM_CKE14

DRAM_WE_N14DRAM_LDQM14ADC_SCLK21ADC_DOUT21

ADC_DIN21ADC_CONVST21

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BANK 3, BANK 4 F

DE1-SoC BoardB

3 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BANK 3, BANK 4 F

DE1-SoC BoardB

3 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BANK 3, BANK 4 F

DE1-SoC BoardB

3 30Thursday, November 20, 2014

Bank 4A

5CSEMA5F31

U20-10

IO_4A/RZQ_0/DIFFIO_TX_B41NAG17

IO_4A/DIFFIO_RX_B42N/DQ6B/B_DQ_0AF18

IO_4A/DIFFIO_TX_B41P/DQ6B/B_DQ_2AG16

IO_4A/DIFFIO_RX_B42P/DQ6B/B_DQ_1AE17

IO_4A/DIFFIO_RX_B43N/DQSN6B/B_DQSN_0W16

IO_4A/DIFFIO_TX_B44N/DQ6B/B_DQ_3AF16

IO_4A/DIFFIO_RX_B43P/DQS6B/B_DQS_0V16

IO_4A/DIFFIO_TX_B44P/B_ODT_0AE16

IO_4A/DIFFIO_TX_B45N/DQ6B/B_ODT_1AK16

IO_4A/DIFFIO_RX_B46N/DQ6B/B_DQ_4AH20

IO_4A/DIFFIO_TX_B45P/DQ6B/B_DQ_6AJ16

IO_4A/DIFFIO_RX_B46P/DQ6B/B_DQ_5AG21

IO_4A/DIFFIO_TX_B48N/DQ6B/B_DQ_7AH18 IO_4A/DIFFIO_TX_B48P/DQ6B/B_DM_0AH17

IO_4A/DIFFIO_TX_B49N/GNDAH19

IO_4A/DIFFIO_RX_B50N/DQ7B/B_DQ_8AK18

IO_4A/DIFFIO_TX_B49P/DQ7B/B_DQ_10AG18

IO_4A/DIFFIO_RX_B50P/DQ7B/B_DQ_9AJ17

IO_4A/DIFFIO_RX_B51N/DQSN7B/B_DQSN_1W17

IO_4A/DIFFIO_TX_B52N/DQ7B/B_DQ_11AK19

IO_4A/DIFFIO_RX_B51P/DQS7B/B_DQS_1V17

IO_4A/DIFFIO_TX_B52P/B_CKE_1AJ19

IO_4A/DIFFIO_TX_B53N/DQ7B/B_CKE_0AJ21

IO_4A/DIFFIO_RX_B54N/DQ7B/B_DQ_12AG20

IO_4A/DIFFIO_TX_B53P/DQ7B/B_DQ_14AJ20

IO_4A/DIFFIO_RX_B54P/DQ7B/B_DQ_13AF19

IO_4A/DIFFIO_TX_B56N/DQ7B/B_DQ_15AH24 IO_4A/DIFFIO_TX_B56P/DQ7B/B_DM_1AG23

IO_4A/DIFFIO_TX_B57N/GNDAH22

IO_4A/DIFFIO_RX_B58N/DQ8B/B_DQ_16AE19

IO_4A/DIFFIO_TX_B57P/DQ8B/B_DQ_18AG22

IO_4A/DIFFIO_RX_B58P/DQ8B/B_DQ_17AE18

IO_4A/DIFFIO_RX_B59N/DQSN8B/B_DQSN_2AA18

IO_4A/DIFFIO_TX_B60N/DQ8B/B_DQ_19AK22

IO_4A/DIFFIO_RX_B59P/DQS8B/B_DQS_2Y17

IO_4A/DIFFIO_TX_B60P/B_RESETNAK21

IO_4A/DIFFIO_TX_B61N/DQ8B/GNDAJ22

IO_4A/DIFFIO_RX_B62N/DQ8B/B_DQ_20AF21

IO_4A/DIFFIO_TX_B61P/DQ8B/B_DQ_22AH23

IO_4A/DIFFIO_RX_B62P/DQ8B/B_DQ_21AF20

IO_4A/DIFFIO_RX_B63N/GNDAA19

IO_4A/DIFFIO_TX_B64N/DQ8B/B_DQ_23AK24

IO_4A/DIFFIO_RX_B63P/GNDY18

IO_4A/DIFFIO_TX_B64P/DQ8B/B_DM_2AK23

IO_4A/DIFFIO_TX_B65N/GNDAJ25

IO_4A/DIFFIO_RX_B66N/DQ9B/B_DQ_24AF24

IO_4A/DIFFIO_TX_B65P/DQ9B/B_DQ_26AJ24

IO_4A/DIFFIO_RX_B66P/DQ9B/B_DQ_25AF23

IO_4A/DIFFIO_RX_B67N/DQSN9B/B_DQSN_3AD19

IO_4A/DIFFIO_TX_B68N/DQ9B/B_DQ_27AK26

IO_4A/DIFFIO_RX_B67P/DQS9B/B_DQS_3AC20

IO_4A/DIFFIO_TX_B68P/GNDAJ26

IO_4A/DIFFIO_TX_B69N/DQ9B/GNDAH25

IO_4A/DIFFIO_RX_B70N/DQ9B/B_DQ_28AE23

IO_4A/DIFFIO_TX_B69P/DQ9B/B_DQ_30AG25

IO_4A/DIFFIO_RX_B70P/DQ9B/B_DQ_29AE22

IO_4A/DIFFIO_RX_B71N/GNDW19

IO_4A/DIFFIO_TX_B72N/DQ9B/B_DQ_31AK27

IO_4A/DIFFIO_RX_B71P/GNDV18

IO_4A/DIFFIO_TX_B72P/DQ9B/B_DM_3AJ27

IO_4A/DIFFIO_TX_B73N/GNDAK29

IO_4A/DIFFIO_RX_B74N/DQ10B/B_DQ_32AD21

IO_4A/DIFFIO_TX_B73P/DQ10B/B_DQ_34AK28

IO_4A/DIFFIO_RX_B74P/DQ10B/B_DQ_33AD20

IO_4A/DIFFIO_RX_B75N/DQSN10B/B_DQSN_4AA20

IO_4A/DIFFIO_TX_B76N/DQ10B/B_DQ_35AH27

IO_4A/DIFFIO_RX_B75P/DQS10B/B_DQS_4Y19

IO_4A/DIFFIO_TX_B76P/GNDAG26

IO_4A/DIFFIO_TX_B77N/DQ10B/GNDAF26

IO_4A/DIFFIO_RX_B78N/DQ10B/B_DQ_36AC23

IO_4A/DIFFIO_TX_B77P/DQ10B/B_DQ_38AF25

IO_4A/DIFFIO_RX_B78P/DQ10B/B_DQ_37AC22

IO_4A/DIFFIO_RX_B79N/GNDAB21

IO_4A/DIFFIO_TX_B80N/DQ10B/B_DQ_39AE24

IO_4A/DIFFIO_RX_B79P/GNDAA21

IO_4A/DIFFIO_TX_B80P/DQ10B/B_DM_4AD24

Bank 3Bank 3A Bank 3B

5CSEMA5F31

U20-9

IO_3A/PR_DONE/DIFFIO_RX_B7NAF5

IO_3A/PR_READY/DIFFIO_TX_B8N/DQ1BAG8

IO_3A/PR_ERROR/DIFFIO_RX_B7PAF4

IO_3A/DIFFIO_TX_B8P/DQ1BAF9

IO_3A/DIFFIO_TX_B9NAG7

IO_3A/DIFFIO_RX_B10N/DQ2BAH2

IO_3A/DIFFIO_TX_B9P/DQ2BAF8

IO_3A/DIFFIO_RX_B10P/DQ2BAG1

IO_3A/DIFFIO_RX_B11N/DQSN2BAB12

IO_3A/DIFFIO_TX_B12N/DQ2BAG6

IO_3A/DIFFIO_RX_B11P/DQS2BAA12

IO_3A/DIFFIO_TX_B12PAF6

IO_3A/DIFFIO_TX_B13N/DQ2BAH5

IO_3A/DIFFIO_RX_B14N/DQ2BAJ2

IO_3A/DIFFIO_TX_B13P/DQ2BAG5

IO_3A/DIFFIO_RX_B14P/DQ2BAJ1

IO_3A/DIFFIO_RX_B15NAD12

IO_3A/DIFFIO_TX_B16N/DQ2BAH3

IO_3A/DIFFIO_RX_B15PAC12

IO_3A/DIFFIO_TX_B16P/DQ2BAG2

IO_3B/DIFFIO_TX_B17NAH9

IO_3B/DIFFIO_RX_B18N/DQ3BAG11

IO_3B/DIFFIO_TX_B17P/DQ3BAG10

IO_3B/DIFFIO_RX_B18P/DQ3BAF11

IO_3B/DIFFIO_RX_B19N/DQSN3BAB13

IO_3B/DIFFIO_TX_B20N/DQ3BAK3

IO_3B/DIFFIO_RX_B19P/DQS3BAA13

IO_3B/DIFFIO_TX_B20PAK2

IO_3B/DIFFIO_TX_B21N/DQ3BAK4

IO_3B/DIFFIO_RX_B22N/DQ3BAF13

IO_3B/DIFFIO_TX_B21P/DQ3BAJ4

IO_3B/DIFFIO_RX_B22P/DQ3BAE13

IO_3B/DIFFIO_RX_B23NAE14

IO_3B/DIFFIO_TX_B24N/DQ3BAK6

IO_3B/DIFFIO_RX_B23PAD14

IO_3B/DIFFIO_TX_B24P/DQ3BAJ5

IO_3B/DIFFIO_TX_B25N/GNDAJ7

IO_3B/DIFFIO_RX_B26N/DQ4B/B_A_15AG13

IO_3B/DIFFIO_TX_B25P/DQ4B/B_WENAJ6

IO_3B/DIFFIO_RX_B26P/DQ4B/B_A_14AG12

IO_3B/DIFFIO_RX_B27N/DQSN4B/B_CSN_1AC14

IO_3B/DIFFIO_TX_B28N/DQ4B/B_A_13AK8

IO_3B/DIFFIO_RX_B27P/DQS4B/B_CSN_0AB15

IO_3B/DIFFIO_TX_B28P/B_A_12AK7

IO_3B/DIFFIO_TX_B29N/DQ4B/B_A_11AK9

IO_3B/DIFFIO_RX_B30N/DQ4B/B_A_9AH14

IO_3B/DIFFIO_TX_B29P/DQ4B/B_A_10AJ9

IO_3B/DIFFIO_RX_B30P/DQ4B/B_A_8AH13

IO_3B/DIFFIO_TX_B32N/DQ4B/B_RASNAH8IO_3B/DIFFIO_TX_B32P/DQ4B/B_CASNAH7

IO_3B/DIFFIO_TX_B33N/GNDAJ10

IO_3B/DIFFIO_RX_B34N/DQ5B/B_BA_2AK11

IO_3B/DIFFIO_TX_B33P/DQ5B/B_BA_0AH10

IO_3B/DIFFIO_RX_B34P/DQ5B/B_BA_1AJ11

IO_3B/DIFFIO_RX_B35N/DQSN5B/B_CKNAA15

IO_3B/DIFFIO_TX_B36N/DQ5B/B_A_7AK13

IO_3B/DIFFIO_RX_B35P/DQS5B/B_CKAA14

IO_3B/DIFFIO_TX_B36P/B_A_6AK12

IO_3B/DIFFIO_RX_B38N/DQ5B/B_A_5AH15IO_3B/DIFFIO_RX_B38P/DQ5B/B_A_4AG15

IO_3B/DIFFIO_TX_B40N/DQ5B/B_A_1AK14IO_3B/DIFFIO_TX_B40P/DQ5B/B_A_0AJ14

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCCIO = 3.3V

VCCIO = 1.5V

VCCIO = 1.5V

VCCIO = 3.3V VCCIO = 3.3V

HPS_DDR3_RZQ

HPS_DDR3_DQ24HPS_DDR3_DQ25HPS_DDR3_DQ26HPS_DDR3_DQ27HPS_DDR3_DQ28HPS_DDR3_DQ29HPS_DDR3_DQ30HPS_DDR3_DQ31

HPS_DDR3_DM3HPS_DDR3_DQS_P3HPS_DDR3_DQS_N3

HPS_DDR3_ADDR11HPS_DDR3_ADDR12HPS_DDR3_ADDR13HPS_DDR3_ADDR14

HPS_DDR3_BA1HPS_DDR3_BA0

HPS_DDR3_BA2

HPS_DDR3_ADDR7HPS_DDR3_ADDR8HPS_DDR3_ADDR9HPS_DDR3_ADDR10

HPS_DDR3_ADDR3HPS_DDR3_ADDR4HPS_DDR3_ADDR5HPS_DDR3_ADDR6

HPS_DDR3_ADDR0HPS_DDR3_ADDR1HPS_DDR3_ADDR2

HPS_DDR3_DQ16HPS_DDR3_DQ17HPS_DDR3_DQ18HPS_DDR3_DQ19HPS_DDR3_DQ20HPS_DDR3_DQ21HPS_DDR3_DQ22HPS_DDR3_DQ23

HPS_DDR3_DM2HPS_DDR3_DQS_P2HPS_DDR3_DQS_N2

HPS_DDR3_DQ8HPS_DDR3_DQ9HPS_DDR3_DQ10HPS_DDR3_DQ11HPS_DDR3_DQ12HPS_DDR3_DQ13HPS_DDR3_DQ14HPS_DDR3_DQ15

HPS_DDR3_DM1HPS_DDR3_DQS_P1HPS_DDR3_DQS_N1

HPS_DDR3_DQ0HPS_DDR3_DQ1HPS_DDR3_DQ2HPS_DDR3_DQ3HPS_DDR3_DQ4HPS_DDR3_DQ5HPS_DDR3_DQ6HPS_DDR3_DQ7

HPS_DDR3_DM0HPS_DDR3_DQS_P0HPS_DDR3_DQS_N0

LEDR7

LEDR8

LEDR9

HEX12

HEX11

HEX06

HEX13

HEX05

HEX03

HEX15HEX14

HEX04

HEX02HEX01

HEX30HEX31

HEX54

HEX35

HEX20HEX40

HEX36

HEX56

HEX42HEX41

HEX44

HEX43

HEX45

HEX24

HEX23HEX25

HEX26

HEX34HEX51

HEX46HEX50

GND

HPS_DDR3_CK_P 15HPS_DDR3_CK_N 15

HPS_DDR3_CAS_N 15HPS_DDR3_RAS_N 15

HPS_DDR3_CS_N 15

HPS_DDR3_RESET_N 15

HPS_DDR3_WE_N 15

HPS_DDR3_CKE15

HPS_DDR3_ODT15

LEDR[9..0] 3,19

HEX0[6..0] 7,19HEX1[6..0] 7,19HEX2[6..0] 6,19HEX3[6..0] 7,19HEX4[6..0] 19HEX5[6..0] 6,19

IRDA_TXD21IRDA_RXD21

HPS_DDR3_DQS_N[3..0] 15

HPS_DDR3_DQS_P[3..0] 15

HPS_DDR3_DQ[31..0] 15

HPS_DDR3_DM[3..0] 15

HPS_DDR3_BA[2..0] 15

HPS_DDR3_ADDR[14..0] 15

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BANK 5, BANK 6 F

DE1-SoC BoardB

4 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BANK 5, BANK 6 F

DE1-SoC BoardB

4 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BANK 5, BANK 6 F

DE1-SoC BoardB

4 30Thursday, November 20, 2014

R236 100

Bank 5Bank 5A Bank 5B

5CSEMA5F31

U20-11

IO_5A/RZQ_1/DIFFIO_TX_R1P/DQ1RAG27

IO_5A/PR_REQUEST/DIFFIO_TX_R1N/DQ1RAH28

IO_5A/DIFFIO_RX_R4P/DQ1RW20

IO_5A/CVP_CONFDONE/DIFFIO_TX_R3N/DQ1RAH29 IO_5A/DIFFIO_RX_R4N/DQ1R

Y21

IO_5A/DIFFIO_RX_R6P/DQS1RW21

IO_5A/DIFFIO_RX_R6N/DQSN1RW22

IO_5A/DIFFIO_TX_R7P/DQ1RAA25

IO_5A/DIFFIO_RX_R8P/DQ1RAB22 IO_5A/DIFFIO_TX_R7NAB26

IO_5A/DIFFIO_RX_R8N/DQ1RAB23

IO_5A/DIFFIO_RX_R9PAA24

IO_5A/DIFFIO_TX_R10P/DQ2RAE27 IO_5A/DIFFIO_RX_R9NAB25

IO_5A/DIFFIO_TX_R10N/DQ2RAE28

IO_5A/DIFFIO_RX_R11P/DQ2RY23

IO_5A/DIFFIO_TX_R12P/DQ2RAG28 IO_5A/DIFFIO_RX_R11N/DQ2R

Y24

IO_5A/DIFFIO_TX_R12N/DQ2RAF28

IO_5A/DIFFIO_RX_R13P/DQS2RV23

IO_5A/DIFFIO_TX_R14PAF29 IO_5A/DIFFIO_RX_R13N/DQSN2RW24

IO_5A/DIFFIO_TX_R14N/DQ2RAF30

IO_5A/DIFFIO_RX_R15P/DQ2RAD26

IO_5A/DIFFIO_TX_R16P/DQ2RAH30 IO_5A/DIFFIO_RX_R15N/DQ2RAC27

IO_5A/DIFFIO_TX_R16NAG30

IO_5B/DIFFIO_RX_R17PW25

IO_5B/DIFFIO_TX_R18P/DQ3RAC28IO_5B/DIFFIO_RX_R17NV25

IO_5B/DIFFIO_TX_R18N/DQ3RAC29

IO_5B/DIFFIO_RX_R19P/DQ3RAB30

IO_5B/DIFFIO_TX_R20P/DQ3RAB28IO_5B/DIFFIO_RX_R19N/DQ3RAA30

IO_5B/DIFFIO_TX_R20N/DQ3RAA28

IO_5B/DIFFIO_TX_R24P/DQ3RAD30

IO_5B/RZQ_2/DIFFIO_TX_R24NAC30

Bank 6Bank 6B

Bank 6A

5CSEMA5F31

U20-12

HPS_DDR/HPS_DM_4W27

HPS_DDR/HPS_DQ_39Y29

HPS_DDR/HPS_DQ_37U25 HPS_DDR/HPS_DQ_38V27

HPS_DDR/HPS_DQ_36T25

HPS_DDR/HPS_DQS_4T24

HPS_GPI13Y28

HPS_DDR/HPS_DQSN_4T23

HPS_DDR/HPS_DQ_35V28

HPS_DDR/HPS_DQ_33R24 HPS_DDR/HPS_DQ_34U27

HPS_DDR/HPS_DQ_32W26

HPS_GPI12V29

HPS_GPI11U20

HPS_DDR/HPS_DM_3W30

HPS_GPI10T21

HPS_DDR/HPS_DQ_31W29

HPS_DDR/HPS_DQ_29R26 HPS_DDR/HPS_DQ_30V30

HPS_DDR/HPS_DQ_28R27

HPS_DDR/HPS_DQS_3R22

HPS_GPI9U28

HPS_DDR/HPS_DQSN_3R21

HPS_DDR/HPS_DQ_27T28

HPS_DDR/HPS_DQ_25P25 HPS_DDR/HPS_DQ_26T29

HPS_DDR/HPS_DQ_24P24

HPS_GPI8T30

HPS_GPI7V20

HPS_DDR/HPS_DM_2R28

HPS_GPI6P22

HPS_DDR/HPS_DQ_23R29

HPS_DDR/HPS_DQ_21P27HPS_DDR/HPS_DQ_22N27

HPS_DDR/HPS_DQ_20P26

HPS_GPI5P29

HPS_DDR/HPS_DQS_2R19

HPS_DDR/HPS_RESETNP30

HPS_DDR/HPS_DQSN_2R18

HPS_DDR/HPS_DQ_19N28

HPS_DDR/HPS_DQ_17T26HPS_DDR/HPS_DQ_18N29

HPS_DDR/HPS_DQ_16U26

HPS_GPI4N30

HPS_GPI3M22

HPS_DDR/HPS_DM_1M28

HPS_GPI2N23

HPS_DDR/HPS_DQ_15M30

HPS_DDR/HPS_DQ_13M27HPS_DDR/HPS_DQ_14L28

HPS_DDR/HPS_DQ_12M26

HPS_DDR/HPS_CKE_0L29

HPS_DDR/HPS_DQS_1N25

HPS_DDR/HPS_CKE_1L30

HPS_DDR/HPS_DQSN_1N24

HPS_DDR/HPS_DQ_11K27

HPS_DDR/HPS_DQ_9L26HPS_DDR/HPS_DQ_10K29

HPS_DDR/HPS_DQ_8K26

HPS_GPI1J26

HPS_GPI0M25

HPS_DDR/HPS_DM_0K28

HPS_DDR/HPS_DQ_7J29

HPS_DDR/HPS_DQ_5L24HPS_DDR/HPS_DQ_6J30

HPS_DDR/HPS_DQ_4L25

HPS_DDR/HPS_ODT_1H29

HPS_DDR/HPS_DQS_0N18

HPS_DDR/HPS_ODT_0H28

HPS_DDR/HPS_DQSN_0M19

HPS_DDR/HPS_DQ_3G28

HPS_DDR/HPS_DQ_1K22HPS_DDR/HPS_DQ_2H30

HPS_DDR/HPS_DQ_0K23

HPS_DDR/HPS_A_0F26 HPS_DDR/HPS_A_1G30

HPS_DDR/HPS_A_4J25

HPS_DDR/HPS_A_2F28

HPS_DDR/HPS_A_5J27

HPS_DDR/HPS_A_3F30

HPS_DDR/HPS_CKM23

HPS_DDR/HPS_A_6F29

HPS_DDR/HPS_CKNL23

HPS_DDR/HPS_A_7E28

HPS_DDR/HPS_BA_1J24

HPS_DDR/HPS_BA_0E29

HPS_DDR/HPS_BA_2J23

HPS_DDR/HPS_CASNE27

HPS_DDR/HPS_RASND30

HPS_DDR/HPS_A_8H27

HPS_DDR/HPS_A_10D29

HPS_DDR/HPS_A_9G26

HPS_DDR/HPS_A_11C30

HPS_DDR/HPS_CSN_0H24

HPS_DDR/HPS_A_12B30

HPS_DDR/HPS_CSN_1K21

HPS_DDR/HPS_A_13C29 HPS_DDR/HPS_A_14H25

HPS_DDR/HPS_WENC28

HPS_DDR/HPS_A_15G25

HPS_RZQ_0D27

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCCIO = 3.3V

VCCIO = 3.3V

VCCIO = 3.3V

VCCIO = 3.3V

VCCIO = 3.3V

(BOOTSEL0)(BOOTSEL1)(BOOTSEL2)

Default Setting: BOOTSEL[2:0]=101 (Boot from SD CARD) CLKSEL[1:0]=0

(CLOCKSEL0)(CLOCKSEL1)

(BOOTSEL0)(BOOTSEL1)(BOOTSEL2)(CLOCKSEL0)(CLOCKSEL1)

HPS_CLOCK1_25HPS_CLOCK2_25

HPS_BOOTSEL0HPS_FLASH_NCSOHPS_BOOTSEL2HPS_SPIM_SSHPS_CLOCKSEL1

HPS_BOOTSEL0HPS_FLASH_NCSOHPS_BOOTSEL2HPS_SPIM_SSHPS_CLOCKSEL1

HPS_CLOCKSEL1

HPS_BOOTSEL2

HPS_BOOTSEL0

HPS_ENET_TX_DATA0HPS_ENET_TX_DATA1HPS_ENET_TX_DATA2HPS_ENET_TX_DATA3HPS_ENET_RX_DATA0

HPS_ENET_RX_DATA1HPS_ENET_RX_DATA2HPS_ENET_RX_DATA3

HPS_FLASH_DATA2HPS_FLASH_DATA1HPS_FLASH_DATA0

HPS_FLASH_DATA3

HPS_USB_DATA0HPS_USB_DATA1HPS_USB_DATA2HPS_USB_DATA3

HPS_USB_DATA4

HPS_USB_DATA5HPS_USB_DATA6

HPS_USB_DATA7

HPS_CLK_25

VGA_R0VGA_B0

VGA_R1VGA_R3

VGA_R4

VGA_R5

VGA_R2

VGA_R6

VGA_B5VGA_B3

VGA_B4

VGA_B2

VGA_B1

VGA_R7

VGA_G5

VGA_G2

VGA_G7VGA_G6

VGA_G4

VGA_G1VGA_G0

TD_DATA7

TD_DATA6

TD_DATA5TD_DATA4

TD_DATA3

TD_DATA2

TD_DATA1

TD_DATA0

VGA_G3

VCC3P3

VCC3P3

HPS_CLK_25 6

HPS_FLASH_NCSO14

HPS_SPIM_SS25

HPS_TDO 11HPS_TDI 11

HPS_TMS 11HPS_TCK 11

HPS_SPIM_CLK25HPS_SPIM_MOSI25HPS_SPIM_MISO25

HPS_UART_TX24HPS_UART_RX24

HPS_I2C2_SCLK25HPS_I2C2_SDAT25

HPS_LED26HPS_KEY26

HPS_I2C1_SCLK25,26HPS_I2C1_SDAT25,26

HPS_ENET_GTX_CLK 23

HPS_ENET_TX_EN 23

HPS_ENET_MDC 23HPS_ENET_MDIO 23

HPS_ENET_RX_CLK 23

HPS_ENET_RX_DV 23

HPS_ENET_INT_N23HPS_FLASH_DCLK14

HPS_ENET_RX_DATA[3..0] 23

HPS_ENET_TX_DATA[3..0] 23

HPS_FLASH_DATA[3..0] 14

HPS_ENET_RESET_N23,26HPS_USB_RESET22

HPS_SD_DATA0 24HPS_SD_DATA1 24

HPS_SD_CMD 24HPS_SD_DATA224HPS_SD_DATA324

HPS_SD_CLK24

HPS_LTC_GPIO 25

HPS_USB_STP 22HPS_USB_DIR 22HPS_USB_NXT 22

HPS_USB_CLKOUT22

HPS_CONV_USB_N24

AUD_ADCDAT18AUD_ADCLRCK18

AUD_BCLK18

AUD_DACLRCK 18

AUD_XCK18

AUD_DACDAT18

VGA_SYNC_N 16

VGA_HS 16VGA_VS 16

VGA_R[7..0] 16

VGA_G[7..0] 16

VGA_B[7..0] 6,16

TD_RESET_N17

TD_HS 17

TD_VS 17

TD_DATA[7..0] 17

FPGA_I2C_SCLK26FPGA_I2C_SDAT26

HPS_GSENSOR_INT25

HPS_I2C_CONTROL26

VGA_BLANK_N16

HPS_USB_DATA[7..0] 22

HPS_WARM_RST_N10,11,26

HPS_RESET_N 10,26

JTAG_TRST 10,11

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BANK 7, BANK 8 F

DE1-SoC BoardB

5 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BANK 7, BANK 8 F

DE1-SoC BoardB

5 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BANK 7, BANK 8 F

DE1-SoC BoardB

5 30Thursday, November 20, 2014

R104 1K

R87 0DNI

R107 10K DNI

R85 0DNI

R108 10K

Bank 7Bank 7A

Bank 7B

Bank 7C

Bank 7D

5CSEMA5F31

U20-13

HPS_NRSTC27

HPS_NPORF23

HPS_TDOB28

HPS_TMSA29 HPS_TCKH22

HPS_TRSTA28

HPS_TDIB27

HPS_PORSELF24

HPS_CLK1D25

HPS_CLK2F25

TRACE_CLK/HPS_GPIO48B26TRACE_D0/SPIS0_CLK/UART0_RX/HPS_GPIO49B25TRACE_D1/SPIS0_MOSI/UART0_TX/HPS_GPIO50C25TRACE_D2/SPIS0_MISO/I2C1_SDA/HPS_GPIO51A25TRACE_D3/SPIS0_SS0/I2C1_SCL/HPS_GPIO52H23TRACE_D4/SPIS1_CLK/CAN1_RX/HPS_GPIO53A24TRACE_D5/SPIS1_MOSI/CAN1_TX/HPS_GPIO54G21TRACE_D6/SPIS1_SS0/I2C0_SDA/HPS_GPIO55C24TRACE_D7/SPIS1_MISO/I2C0_SCL/HPS_GPIO56E23SPIM0_CLK/I2C1_SDA/UART0_CTS/HPS_GPIO57A23SPIM0_MOSI/I2C1_SCL/UART0_RTS/HPS_GPIO58C22SPIM0_MISO/CAN1_RX/UART1_CTS/HPS_GPIO59B23SPIM0_SS0,BOOTSEL0/SPIM0_SS0/CAN1_TX/UART1_RTS/HPS_GPIO60H20UART0_RX/CAN0_RX/SPIM0_SS1/HPS_GPIO61B22UART0_TX,CLKSEL1/UART0_TX/CAN0_TX/SPIM1_SS1/HPS_GPIO62G22I2C0_SDA/UART1_RX/SPIM1_CLK/HPS_GPIO63C23I2C0_SCL/UART1_TX/SPIM1_MOSI/HPS_GPIO64D22CAN0_RX/UART0_RX/SPIM1_MISO/HPS_GPIO65E24CAN0_TX,CLKSEL0/CAN0_TX/UART0_TX/SPIM1_SS0/HPS_GPIO66D24

NAND_ALE/RGMII1_TX_CLK/QSPI_SS3/HPS_GPIO14H19

NAND_CE/RGMII1_TXD0/USB1_D0/HPS_GPIO15F20

NAND_CLE/RGMII1_TXD1/USB1_D1/HPS_GPIO16J19

NAND_RE/RGMII1_TXD2/USB1_D2/HPS_GPIO17F21

NAND_RB/RGMII1_TXD3/USB1_D3/HPS_GPIO18F19

NAND_DQ0/RGMII1_RXD0/HPS_GPIO19A21

NAND_DQ1/RGMII1_MDIO/I2C3_SDA/HPS_GPIO20E21

NAND_DQ2/RGMII1_MDC/I2C3_SCL/HPS_GPIO21B21

NAND_DQ3/RGMII1_RX_CTL/USB1_D4/HPS_GPIO22K17

NAND_DQ4/RGMII1_TX_CTL/USB1_D5/HPS_GPIO23A20

NAND_DQ5/RGMII1_RX_CLK/USB1_D6/HPS_GPIO24G20

NAND_DQ6/RGMII1_RXD1/USB1_D7/HPS_GPIO25B20

NAND_DQ7/RGMII1_RXD2/HPS_GPIO26B18

NAND_WP/RGMII1_RXD3/QSPI_SS2/HPS_GPIO27D21

NAND_WE,BOOTSEL2/NAND_WE/QSPI_SS1/HPS_GPIO28D20

QSPI_IO0/USB1_CLK/HPS_GPIO29C20QSPI_IO1/USB1_STP/HPS_GPIO30H18QSPI_IO2/USB1_DIR/HPS_GPIO31A19QSPI_IO3/USB1_NXT/HPS_GPIO32E19QSPI_SS0,BOOTSEL1/QSPI_SS0/HPS_GPIO33A18QSPI_CLK/HPS_GPIO34D19QSPI_SS1/HPS_GPIO35C19

SDMMC_CMD/USB0_D0/HPS_GPIO36F18

SDMMC_PWREN/USB0_D1/HPS_GPIO37B17

SDMMC_D0/USB0_D2/HPS_GPIO38G18

SDMMC_D1/USB0_D3/HPS_GPIO39C17

SDMMC_D4/USB0_D4/HPS_GPIO40H17

SDMMC_D5/USB0_D5/HPS_GPIO41C18

SDMMC_D6/USB0_D6/HPS_GPIO42G17SDMMC_D7/USB0_D7/HPS_GPIO43E18SDMMC_FB_CLK_IN/USB0_CLK/HPS_GPIO44E17SDMMC_CCLK_OUT/USB0_STP/HPS_GPIO45A16SDMMC_D2/USB0_DIR/HPS_GPIO46D17SDMMC_D3/USB0_NXT/HPS_GPIO47B16

RGMII0_TX_CLK/HPS_GPIO0F16

RGMII0_TXD0/USB1_D0/HPS_GPIO1E16

RGMII0_TXD1/USB1_D1/HPS_GPIO2G16

RGMII0_TXD2/USB1_D2/HPS_GPIO3D16

RGMII0_TXD3/USB1_D3/HPS_GPIO4D14

RGMII0_RXD0/USB1_D4/HPS_GPIO5A15

RGMII0_MDIO/USB1_D5/I2C2_SDA/HPS_GPIO6C14RGMII0_MDC/USB1_D6/I2C2_SCL/HPS_GPIO7D15

RGMII0_RX_CTL/USB1_D7/HPS_GPIO8M17

RGMII0_TX_CTL/HPS_GPIO9B15

RGMII0_RX_CLK/USB1_CLK/HPS_GPIO10N16

RGMII0_RXD1/USB1_STP/HPS_GPIO11C15

RGMII0_RXD2/USB1_DIR/HPS_GPIO12E14

RGMII0_RXD3/USB1_NXT/HPS_GPIO13A14

R99 1K

R95 1K R97 10K DNI

R110 1K

R234 4.7K

Bank 8A

5CSEMA5F31

U20-14

IO_8A/DIFFIO_TX_T2P/DQ1TB13

IO_8A/DIFFIO_TX_T2N/DQ1TA13

IO_8A/DIFFIO_RX_T3P/DQ1TC13

IO_8A/DIFFIO_RX_T3N/DQ1TB12

IO_8A/DIFFIO_RX_T5P/DQS1TF15

IO_8A/DIFFIO_TX_T6PC12 IO_8A/DIFFIO_RX_T5N/DQSN1TF14

IO_8A/DIFFIO_TX_T6N/DQ1TB11

IO_8A/DIFFIO_RX_T7P/DQ1TD11

IO_8A/DIFFIO_TX_T8P/DQ1TA9 IO_8A/DIFFIO_RX_T7N/DQ1T

D10

IO_8A/DIFFIO_TX_T8NA8

IO_8A/DIFFIO_TX_T10P/DQ2TC7

IO_8A/DIFFIO_TX_T10N/DQ2TB7

IO_8A/DIFFIO_RX_T11P/DQ2TE9

IO_8A/DIFFIO_TX_T12P/DQ2TC8 IO_8A/DIFFIO_RX_T11N/DQ2TD9

IO_8A/DIFFIO_TX_T12N/DQ2TB8

IO_8A/DIFFIO_RX_T13P/DQS2TH14

IO_8A/DIFFIO_TX_T14PC10 IO_8A/DIFFIO_RX_T13N/DQSN2TG13

IO_8A/DIFFIO_TX_T14N/DQ2TC9

IO_8A/DIFFIO_RX_T15P/DQ2TF13

IO_8A/DIFFIO_TX_T16P/DQ2TA6 IO_8A/DIFFIO_RX_T15N/DQ2T

E13

IO_8A/DIFFIO_TX_T16NA5

IO_8A/DIFFIO_RX_T17PH8

IO_8A/DIFFIO_TX_T18P/DQ3TA4 IO_8A/DIFFIO_RX_T17NG8

IO_8A/DIFFIO_TX_T18N/DQ3TA3

IO_8A/DIFFIO_RX_T19P/DQ3TE12

IO_8A/DIFFIO_TX_T20P/DQ3TD6 IO_8A/DIFFIO_RX_T19N/DQ3T

D12

IO_8A/DIFFIO_TX_T20N/DQ3TC5

IO_8A/DIFFIO_RX_T21P/DQS3TH13

IO_8A/DIFFIO_TX_T22PD5

IO_8A/DIFFIO_RX_T21N/DQSN3TH12

IO_8A/DIFFIO_TX_T22N/DQ3TC4

IO_8A/DIFFIO_RX_T23P/DQ3TF11

IO_8A/DIFFIO_TX_T24P/DQ3TE8IO_8A/DIFFIO_RX_T23N/DQ3TE11

IO_8A/DIFFIO_TX_T24ND7

IO_8A/DIFFIO_RX_T25PJ7

IO_8A/DIFFIO_TX_T26P/DQ4TB2IO_8A/DIFFIO_RX_T25NH7

IO_8A/DIFFIO_TX_T26N/DQ4TB1

IO_8A/DIFFIO_RX_T27P/DQ4TB6

IO_8A/DIFFIO_TX_T28P/DQ4TC3IO_8A/DIFFIO_RX_T27N/DQ4TB5

IO_8A/DIFFIO_TX_T28N/DQ4TB3

IO_8A/DIFFIO_RX_T29P/DQS4TK12

IO_8A/DIFFIO_TX_T30PD2IO_8A/DIFFIO_RX_T29N/DQSN4TJ12

IO_8A/DIFFIO_TX_T30N/DQ4TC2

IO_8A/DIFFIO_RX_T31P/DQ4TG12

IO_8A/DIFFIO_TX_T32P/DQ4TE4IO_8A/DIFFIO_RX_T31N/DQ4TG11

IO_8A/DIFFIO_TX_T32ND4

IO_8A/DIFFIO_RX_T33PK7

IO_8A/DIFFIO_TX_T34P/DQ5TE3IO_8A/DIFFIO_RX_T33NK8

IO_8A/DIFFIO_TX_T34N/DQ5TE2

IO_8A/DIFFIO_RX_T35P/DQ5TG10

IO_8A/DIFFIO_TX_T36P/DQ5TE1IO_8A/DIFFIO_RX_T35N/DQ5TF10

IO_8A/DIFFIO_TX_T36N/DQ5TD1

IO_8A/DIFFIO_RX_T37P/DQS5TJ10

IO_8A/DIFFIO_TX_T38PE7IO_8A/DIFFIO_RX_T37N/DQSN5TJ9

IO_8A/DIFFIO_TX_T38N/DQ5TE6

IO_8A/DIFFIO_RX_T39P/DQ5TF9

IO_8A/DIFFIO_TX_T40P/DQ5TG7IO_8A/DIFFIO_RX_T39N/DQ5TF8

IO_8A/DIFFIO_TX_T40NF6

R96 1K R98 10K DNI

R105 1K

R103 1K

R100 1K

1

ON

SW16

SW-DIP12

DNI1234

121110987

56

R109 1KDNI

R106 10K

R111 1KDNI

R237 4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCCIO = 3.3V

VCCIO = 3.3V

VCCIO = 3.3V

VCCIO = 3.3V

CLOCK_50

CLOCK2_50

CLOCK3_50

CLOCK4_50

CLOCK_50CLOCK2_50

CLOCK4_50

VGA_B6

VGA_B7

DRAM_ADDR7

KEY3KEY2

GPIO_00GPIO_02

GPIO_10

HEX21HEX22

HEX53

HEX52HEX55

CLOCK3_50

VCC3P3

VCC3P3

VCC3P3

ENET_CLK_2523

USBPHY_CLK_2422USBHUB_CLK_2422

VGA_CLK16

TD_CLK27 17

VGA_B[7..0] 5,16

DRAM_CLK14

KEY[3..0] 3,20

GPIO_0[35..0] 3,12

GPIO_1[35..0] 3,13

HEX5[6..0] 4,19HEX2[6..0] 4,19

DRAM_ADDR[12..0] 3,14

HPS_CLK_255

DRAM_BA114

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Clocks & GND F

DE1-SoC BoardB

6 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Clocks & GND F

DE1-SoC BoardB

6 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Clocks & GND F

DE1-SoC BoardB

6 30Thursday, November 20, 2014

C53

0.1u

C187

0.47u

GND

5CSEMA5F31

U20-7

GNDL19

GNDL22

GNDL3

GNDL4

GNDL6

GNDM1

GNDM10

GNDM12

GNDM14

GNDM16

GNDM18

GNDM2

GNDM20

GNDM29

GNDM5

GNDM7

GNDM8

GNDN11

GNDN13

GNDN15

GNDN17

GNDN19

GNDN26

GNDN3

GNDN4

GNDN6

GNDN8

GNDN9

GNDP1

GNDP10

GNDP12

GNDP14

GNDP16

GNDP18

GNDP2

GNDP20

GNDP5

GNDP7

GNDR11

GNDR13

GNDR15

GNDR17

GNDR3

GNDR30

GNDR4

GNDR6

GNDR8

GNDR9

GNDT1

GNDT10

GNDT12

GNDT14

GNDT15

GNDT16

GNDT2

GNDT20

GNDT27

GNDT5

GNDT7

GNDU11

GNDU13

GNDU15

GNDU17

GNDU24

GNDU29

GNDU3

GNDU4

GNDU6

GNDU9

GNDV1

GNDV10

GNDV12

GNDV14

GNDV19

GNDV2

GNDV21

GNDV5

GNDV7

GNDW11

GNDW13

GNDW18

GNDW28

GNDW3

GNDW4

GNDW6

GNDW9

GNDY1

GNDY10

GNDY12

GNDY14

GNDY15

GNDY2

GNDY20

GNDY25

GNDY30

GNDY5

GNDY7

GNDY8

GNDU22

GNDT18

DNU_1F1

DNU_2G2

DNU_3H3

DNU_4H4

DNU_5K3

DNU_6K4

DNU_7M3

DNU_8M4

DNU_9P3

DNU_10P4

DNU_11T3

DNU_12T4

DNU_13V3

DNU_14V4

DNU_15Y3

DNU_16Y4

DNU_17AB3

DNU_18AB4

DNU_19AD3

DNU_20AD4

DNU_21AA7

DNU_22AD15

DNU_23E26

DNU_24J15

R2402K

U12

Si5350C-B02330-GM

XA1

XB2

CLK013

CLK112

CLK29

CLK38

CLK419

CLK517

CLK616

CLK715

VDD

OA

11

VDD

OB

10

VDD

OC

18

VDD

OD

14

VDD

20G

ND

_EP

21

GND3

GND4

GND5

CLKIN6

GND7

C179

0.47u

C185

0.47u

GND

5CSEMA5F31

U20-6

GNDJ22

GNDD26

GNDA26

GNDJ6

GNDJ2

GNDJ1

GNDL2

GNDL1

GNDN2

GNDN1

GNDP9

GNDP8

GNDT8

GNDT9

GNDR2

GNDR1

GNDU2

GNDU1

GNDW2

GNDW1

GNDAA2

GNDAA1

GNDAC2

GNDAC1

GNDAE2

GNDAE1

GNDW8

GNDW7

GNDA12

GNDA17

GNDA2

GNDA22

GNDA27

GNDAA11

GNDAA22

GNDAA3

GNDAA4

GNDAA6

GNDAA9

GNDAB1

GNDAB19

GNDAB2

GNDAB29

GNDAB5

GNDAB7

GNDAC16

GNDAC26

GNDAC3

GNDAC4

GNDAC6

GNDAC8

GNDAD1

GNDAD2

GNDAD23

GNDAD5

GNDAE10

GNDAE20

GNDAE3

GNDAE4

GNDAF1

GNDAF12

GNDAF17

GNDAF2

GNDAF27

GNDAF3

GNDAG14

GNDAG24

GNDAG9

GNDAH1

GNDAH11

GNDAH21

GNDAH6

GNDAJ18

GNDAJ28

GNDAJ3

GNDAJ30

GNDAK15

GNDAK25

GNDAK5

GNDB14

GNDB19

GNDB24

GNDB29

GNDB9

GNDC1

GNDC16

GNDC21

GNDC26

GNDC6

GNDD13

GNDD23

GNDD3

GNDE10

GNDE25

GNDE30

GNDF17

GNDF2

GNDF27

GNDF5

GNDF7

GNDG24

GNDG3

GNDG4

GNDH1

GNDH11

GNDH2

GNDH5

GNDJ18

GNDJ28

GNDJ3

GNDJ4

GNDJ8

GNDK1

GNDK10

GNDK15

GNDK2

GNDK20

GNDK25

GNDK5

GNDL11

GNDL13

GNDL15

GNDL17

Reference pin

5CSEMA5F31

U20-8

RREF_TLG1

C173

0.47u

ClocksBank 3B

Bank 4A

Bank 5B

Bank 8A

5CSEMA5F31

U20-2

IO_3B/CLK0N,FPLL_BL_FBN/DIFFIO_RX_B31NAF15 IO_3B/CLK0P,FPLL_BL_FBP/DIFFIO_RX_B31PAF14

IO_3B/FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTN/DIFFIO_TX_B37N/DQ5B/B_A_3AJ12IO_3B/FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTP,FPLL_BL_FB/DIFFIO_TX_B37P/DQ5B/B_A_2AH12

IO_3B/CLK1N/DIFFIO_RX_B39NY16 IO_3B/CLK1P/DIFFIO_RX_B39P

W15

IO_4A/CLK2N/DIFFIO_RX_B47NAB17 IO_4A/CLK2P/DIFFIO_RX_B47PAA16

IO_4A/CLK3N/DIFFIO_RX_B55NAD17 IO_4A/CLK3P/DIFFIO_RX_B55PAC18

IO_5B/CLK5P/DIFFIO_RX_R21P/DQS3RAA26

IO_5B/FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTP,FPLL_BR_FB/DIFFIO_TX_R22PAE29

IO_5B/CLK5N/DIFFIO_RX_R21N/DQSN3RAB27

IO_5B/FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTN/DIFFIO_TX_R22N/DQ3RAD29IO_5B/CLK4P,FPLL_BR_FBP/DIFFIO_RX_R23P/DQ3R

Y26

IO_5B/CLK4N,FPLL_BR_FBN/DIFFIO_RX_R23N/DQ3RY27

IO_8A/CLK7P/DIFFIO_RX_T1PH15

IO_8A/CLK7N/DIFFIO_RX_T1NG15

IO_8A/FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTP,FPLL_TL_FB/DIFFIO_TX_T4P/DQ1TA11

IO_8A/FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTN/DIFFIO_TX_T4N/DQ1TA10IO_8A/CLK6P,FPLL_TL_FBP/DIFFIO_RX_T9P

K14

IO_8A/CLK6N,FPLL_TL_FBN/DIFFIO_RX_T9NJ14

C186

0.47u

R60 0

Y2

25.00MHz

VCC4

OUT3

GND2

EN1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Fix MSEL[4:0]=10010 in AS Fast Mode

USB Blaster

Design Note:Optional termination resistorfor DCLK

CAD Note:Place near FPGA DCLK pin

3.3V200W

VCCIO = 3.3V VCCIO = 3.3V

EPCQ_NCSOEPCQ_DCLK

EPCQ_AS_DATA0EPCQ_AS_DATA1EPCQ_AS_DATA2EPCQ_AS_DATA3

MSEL0MSEL1MSEL2MSEL3MSEL4

MSEL0MSEL1MSEL2MSEL3MSEL4

MSEL0MSEL1MSEL2MSEL3MSEL4

JTAG_TCKJTAG_TMSFPGA_TDOFPGA_TDI

EPCQ_DCLK

EPCQ_AS_DATA0EPCQ_AS_DATA1EPCQ_AS_DATA2EPCQ_AS_DATA3EPCQ_NCSO

JTAG_TCK

FPGA_CONF_DONEFPGA_NSTATUSFPGA_NCONFIG

USB_B2_DATA0

USB_B2_DATA5

SW3SW4

SW6SW7

SW8

SW9

HEX10

HEX00

HEX16

HEX32

HEX33

VCC3P3

VCC3P3

VCC3P3_PGM

VCC3P3

VCC3P3_PGM

VCC12

FPGA_TDI 11

FPGA_TDO 11

JTAG_TMS 11JTAG_TCK 11

USB_B2_DATA[7..0] 3,10

SW[9..0] 3,20

PS2_DAT 21

PS2_CLK 21

PS2_DAT2 21

PS2_CLK2 21

HEX0[6..0] 4,19HEX1[6..0] 4,19HEX3[6..0] 4,19

FAN_CTRL 3

FPGA_NCONFIG 10

FPGA_CONF_DONE 10

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Configuration F

DE1-SoC BoardB

7 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Configuration F

DE1-SoC BoardB

7 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Configuration F

DE1-SoC BoardB

7 30Thursday, November 20, 2014

R117 10K

R137 0 DNI

ConfigurationBank 3A Bank 5A

Bank 9A

5CSEMA5F31

U20-1

TDOAB9

NCSO/DATA4AB8

TMSV9

AS_DATA3/DATA3AC7 AS_DATA2/DATA2AE8

TDIU8

AS_DATA1/DATA1AE5

DCLKU7

AS_DATA0,ASDO/DATA0AE6

IO_3A/DATA6/DIFFIO_RX_B1N/DQ1BAE12 IO_3A/DATA5/DIFFIO_TX_B2N

AE9

IO_3A/DATA8/DIFFIO_RX_B1P/DQ1BAD11 IO_3A/DATA7/DIFFIO_TX_B2P/DQ1B

AD9

IO_3A/DATA10/DIFFIO_RX_B3N/DQSN1BAD10 IO_3A/DATA9/DIFFIO_TX_B4N/DQ1BAF10

IO_3A/DATA12/DIFFIO_RX_B3P/DQS1BAC9 IO_3A/DATA11/DIFFIO_TX_B4P

AE11

IO_3A/DATA14/DIFFIO_RX_B5N/DQ1BAE7 IO_3A/DATA13/DIFFIO_TX_B6N/DQ1BAH4

IO_3A/CLKUSR/DIFFIO_RX_B5P/DQ1BAD7 IO_3A/DATA15/DIFFIO_TX_B6P/DQ1BAG3

IO_5A/INIT_DONE/DIFFIO_RX_R2PAD25

IO_5A/CRC_ERROR/DIFFIO_RX_R2NAC25

IO_5A/NCEO/DIFFIO_TX_R3P/DQ1RAJ29

IO_5A/DEV_OE/DIFFIO_TX_R5PAE26

IO_5A/DEV_CLRN/DIFFIO_TX_R5N/DQ1RAD27

MSEL0L8

CONF_DONEF3

MSEL1K6

NSTATUSF4

NCEG5 MSEL2

G6

MSEL3L7NCONFIG

J5

MSEL4L9

TCKAC5

R1451KDNI

R1421K

R122 1K

R118 10K

R138 0 DNI

C1050.1u10V

R123 0 DNI

R14610KDNI

1

ON

SW10

SW-DIP12

1234

121110987

56

J16

Power - FAN

DNI

123

U40

S25FL128SAGMFI011

VCC

2

NC013

NC024

NC035

NC046

nCS7

DATA18

DCLK16

DATA015

NC0511

NC0612

NC0713

NC0814

GN

D10

DATA29

DATA31

Q5FDV305NDNI

1

23

R124 0 DNI

R120 1K

R141 0DNI

R121 1K

C8212p

DNI50V

R125 0 DNI

R119 10K

R147 0DNI

R136 1KR135 1K

D99

SM2T3V3ADNI

12

C7333p

DNI50V

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HPS VCC3P3(BANK 7)

FPGA VCC3P3(BANK 3, 4, 5, 8)

HPS VCC2P5(BANK 6)

HPS 1.5V(BANK 6)

FPGA VCCINT

Place C394 close to J20/G23 pin

Panasonic6TPE100MPB

Panasonic6TPE100MPB

Panasonic6TPE100MPB

Panasonic6TPE100MPB

Panasonic6TPE100MPB

Panasonic2R5TPE330MAZB

VCCA_FPLL

VCCINT_FPGA

VCCINT_FPGA

VCCINT_FPGA

VCCINT_FPGA

VCCINT_FPGA

VCC1P1_HPS

VCCINT_FPGA

VCC3P3_PGM

VCCINT_FPGA

VCCINT_FPGA

VCCINT_FPGA

VCC1P5_DDR3

VCCINT_FPGA

VCCBAT

VCC_AUX

VCC3P3

VCC3P3

VCC2P5

VCC_AUX_SHARED

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Decoupling F

DE1-SoC BoardB

8 30Wednesday, May 27, 2015

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Decoupling F

DE1-SoC BoardB

8 30Wednesday, May 27, 2015

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Decoupling F

DE1-SoC BoardB

8 30Wednesday, May 27, 2015

C375

47n

C281

4.7n

C369

0.01u

C267

0.22u

C363

0.01u

C276

0.01u

C279

4.7n

C370

1u

C268

0.01u

C290

0.01u

C329

0.47u

C351

4.7n

C197

1u

C282

0.01u

C381

22n C328

4.7u

C265

4.7n

C285

4.7n

C349

4.7n

C271

0.1u

C337

0.01u

C291

4.7n

C309

4.7n

C289

4.7n

C386

4.7n

C341

0.01uC319

0.01u

C350

0.1u

C277

4.7n

C321

0.01u

C322

0.01u

C196

0.47u

C315

4.7n

C379

22n

C387

47n

C348

0.01u

C316

4.7n

C333

0.1u

C304

22n

C272

0.01u

C344

0.01u

C286

0.01u

C283

4.7n

C198

4.7u

C332

4.7n

C308

4.7n

C334

0.01u

C365

0.22u

C227

0.22u

C284

0.01u

C239

0.47u

C343

0.01u

C255

0.1u

C252

0.01uC388

2.2u

C346

0.01u

C389

100u6.3V

C336

4.7n

C361

22n

C313

4.7n

C364

47n

C200

100u6.3V

C237

0.01u

C338

0.01u

C311

4.7n

C310

0.01u

C294

0.01u

C195

22n

C340

0.01u

C274

0.01u

C269

47n

C383

100u6.3V

C211

47n

C206

10u

C342

0.01u

C373

100u6.3V

C330

47n

C261

0.1u

C305

0.1u

C362

4.7n

C208

0.1u

C295

0.01u

C331

0.1u

C262

4.7n C360330u2.5V

C378

100u6.3V

C288

0.01u

C317

4.7n

C367

0.47u

C380

0.1u

C318

4.7n

C263

10u

C258

22n

C345

4.7n

C366

1u

C201

47n

C204

22n

C296

100u6.3V

C210

47n

C203

22n

C278

0.01u

C371

100u6.3V

C280

4.7n

C205

47n

C270

0.01u

C266

22n

C335

4.7n

C359

4.7u

C384

4.7n

C253

0.01u

C292

0.01u

C254

4.7n

C207

100u6.3V

C273

4.7n

C199

1u

C339

0.01u

C376

0.22u

C385

22n

C382

10u

C264

1u

C257

0.1u

C377

2.2u

C306

0.01u

C287

4.7n

C202

22n

C240

22n

C259

0.1u

C320

0.01u

C314

4.7n

C256

22n

C368

4.7n

C251

0.01u

C312

4.7n

C347

0.01u

C275

4.7n

C238

0.01u

C209

0.1u

C372

0.1u

C307

0.01u

C260

22n

C226

0.47u

C293

0.01u

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCCINT_FPGA

VCC2P5 VCCBAT

VCC3P3_PGMVCC3P3

VCC_AUX_SHARED VCC2P5

VCC_AUX VCC2P5

VCCA_FPLL VCC2P5

VCC3P3 VCC3P3

VCC3P3

VCC1P1_HPS

DDR3_VREF_HPS

VCC1P5_DDR3 VCC3P3

VCC3P3

VCC2P5

VCC3P3

VCC_AUX

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Power F

DE1-SoC BoardB

9 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Power F

DE1-SoC BoardB

9 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA Power F

DE1-SoC BoardB

9 30Thursday, November 20, 2014

Power

5CSEMA5F31

U20-4

VCCM11

VCCM13

VCCM9

VCCN10

VCCN12

VCCN14

VCCP11

VCCP13

VCCR10

VCCR12

VCCR14

VCCT11

VCCT13

VCCU10

VCCU12

VCCU14

VCCV11

VCCV13

VCCV15

VCCW10

VCCW12

VCCW14

VCCY11

VCCY13

VCCY9

VCCL5

VCCR5

VCCW5

VCCAA5

VCCM6

VCCN5

VCCT6

VCCU5

VCCY6 VCC

U21

VCCPD3AAA10

VCCPD3AAC10

VCCPD3B4AAB18

VCCPD3B4AAB20VCCPD3B4AAC13

VCCPD3B4AAC15

VCCPD3B4AAC17

VCCPD3B4AAC19

VCCPD3B4AAD16

VCCPD3B4AAE21

VCCPD5AV22

VCCPD5AV24

VCCPD5BU23

VCCPD8AK11

VCCPD8AK13

VCCPD8AL10

VCCPD8AL12

VCCPD8AL14

VCCA_FPLLN7

VCCA_FPLLR7

VCCA_FPLLV8

VCCA_FPLLAA8

VCCA_FPLLK9

VCCA_FPLLY22

VCCA_FPLLAB6

VCCA_FPLLP6

VCCA_FPLLV6

VCC_AUXAB11

VCC_AUXAB16

VCC_AUXAD22

VCC_AUXH10

VCC_AUXJ16

VCC_AUX_SHAREDJ21

VCCPGMJ11

VCCPGMAA23

VCCPGMAB10

VCCBATH9

Power - VCCIO

5CSEMA5F31

U20-5

VCCIO3AAC11

VCCIO3AAD8

VCCIO3AAF7

VCCIO3AAG4

VCCIO3BAB14

VCCIO3BAD13

VCCIO3BAE15

VCCIO3BAJ13

VCCIO3BAJ8

VCCIO3BAK10

VCCIO4AAA17

VCCIO4AAC21

VCCIO4AAD18

VCCIO4AAE25

VCCIO4AAF22

VCCIO4AAG19

VCCIO4AAH16

VCCIO4AAH26

VCCIO4AAJ23 VCCIO4AAK20

VCCIO5AAB24 VCCIO5AAD28 VCCIO5AAG29 VCCIO5AW23

VCCIO5BAA27

VCCIO5BAE30

VCCIO8AA7

VCCIO8AB4

VCCIO8AC11

VCCIO8AD8

VCCIO8AE5

VCCIO8AF12

VCCIO8AG14

VCCIO8AG9

VCCIO8AH6

VCCIO8AJ13

VREFB3AN0AD6

VREFB3BN0AJ15

VREFB4AN0AK17

VREFB5AN0AC24

VREFB5BN0AA29

VREFB8AN0B10

HPS Power

5CSEMA5F31

U20-3

VCCRSTCLK_HPSG23

VCCIO6A_HPSD28

VCCIO6A_HPSG29

VCCIO6A_HPSH26

VCCIO6A_HPSK24

VCCIO6A_HPSK30

VCCIO6A_HPSL27

VCCIO6A_HPSM24

VCCIO6A_HPSN21

VCCIO6B_HPSP23

VCCIO6B_HPSP28

VCCIO6B_HPSR25

VCCIO6B_HPST22

VCCIO6B_HPSU19

VCCIO6B_HPSV26

VCCIO7A_HPSF22VCCIO7A_HPSH21

VCCIO7B_HPSE20VCCIO7B_HPSG19

VCCIO7C_HPSD18

VCCIO7D_HPSE15VCCIO7D_HPSH16

VCCPD6A6B_HPSM21

VCCPD6A6B_HPSN22

VCCPD6A6B_HPSP21

VCCPD6A6B_HPSR20

VCCPD6A6B_HPSR23

VCCPD7A_HPSK19

VCCPD7B_HPSK18

VCCPD7C_HPSJ17

VCCPD7D_HPSK16

VCCRSTCLK_HPSJ20

VCCPLL_HPSL21

VCC_HPSU18 VCC_HPSL16 VCC_HPSL18 VCC_HPSL20 VCC_HPSM15 VCC_HPSN20 VCC_HPSP15 VCC_HPSP17 VCC_HPSP19 VCC_HPSR16 VCC_HPST17 VCC_HPST19 VCC_HPSU16

VREFB6BN0_HPSU30

VREFB6AN0_HPSG27

VREFB7A7B7C7DN0_HPSE22

L26 BEAD

L25 BEAD

R2460

L23 BEADL24 BEAD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Place near MAX II

Place Near CY7C68013A

JTAG INTERFACE

CPLD ISP

JTAG Control for USB Blaster II

JTAG_RX

JTAG_TX

SC_RX

SC_TX

USB_OE_nUSB_RD_nUSB_WR_n

USB_B2_DATA0USB_B2_DATA1USB_B2_DATA2USB_B2_DATA3USB_B2_DATA4

USB_B2_DATA7USB_B2_DATA5USB_B2_DATA6

USB_FULLUSB_EMPTY

USB_SCLUSB_SDA

USB_RESET_n

CLK_24M

C_USB_MAX_TDOC_USB_MAX_TMS

C_USB_MAX_TCK

C_USB_MAX_TDI

FX2_D_NFX2_D_P

FX2_WAKEUPVBUS_VCC5

JTAG_RX

FX2_PD4FX2_PD3

FX2_PD0FX2_PD1FX2_PD2

FX2_PD5FX2_PD6FX2_PD7

CLK_24M

FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7

FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7

USB_B2_CLK

FX2_FLAGCFX2_FLAGB

FX2_WAKEUP

FX2_SLWRnFX2_SLRDn

FX2_FLAGA

FX2_SCLFX2_SDA

FX2_RESETn

C_USB_MAX_TDI

C_USB_MAX_TMS

C_USB_MAX_TCK

C_USB_MAX_TDO

JTAG_TX

USB_B2_CLK

FX2_PD0FX2_PD2FX2_PD3FX2_PD1

SC_TXSC_RX

VBUS_VCC5

FX2_D_PFX2_D_N C_USB_MAX_TCK

C_USB_MAX_TDI

C_USB_MAX_TMSC_USB_MAX_TDO

USB_B2_CLK

FX2_RESETn

FX2_FLAGC

FX2_PA3

FX2_PA2

FX2_PA4

FX2_PA7FX2_FLAGA

FX2_PB4

USB_DISABLE_nFX2_PB5

FX2_FLAGB

FX2_PA1FX2_PB0

FX2_PA6FX2_PB2

FX2_PB6

FX2_SCL

FX2_PB1FX2_PB3

FX2_PD4FX2_PD6

FX2_SLWRnFX2_SLRDn

FX2_PA5

FX2_PD7FX2_PD5

JTAG_Blaster_TDO

JTAG_Blaster_TDIJTAG_Blaster_TMS

JTAG_Blaster_TCK

FX2_PB7

FX2_SDA MAX_SDAMAX_SDA

FX2_RESETn

CLK_24M

FPGA_NCONFIGFPGA_CONF_DONE

HPS_RESET_N

QSPI_RESET_N

VCC3P3

VCC3P3

VCC3P3VCC3P3

VCC3P3

VCC3P3VCC3P3

VCC3P3VCC3P3 VCC1P8

VCC1P8

VCC3P3

VCC3P3

VCC3P3

VCC3P3

JTAG_Blaster_TCK11

JTAG_Blaster_TDI11

JTAG_Blaster_TMS11JTAG_Blaster_TDO11

USB_DISABLE_n11

USB_B2_DATA[7..0] 3,7

USB_SDA 3

HPS_WARM_RST_N5,11,26

USB_B2_CLK 3USB_RESET_n 3USB_OE_n 3USB_RD_n 3USB_WR_n 3

USB_SCL 3USB_FULL 3USB_EMPTY 3

FPGA_NCONFIG7

FPGA_CONF_DONE7

HPS_RESET_N5,26

QSPI_RESET_N14

JTAG_TRST5,11

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

USB Blaster II F

DE1-SoC BoardB

10 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

USB Blaster II F

DE1-SoC BoardB

10 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

USB Blaster II F

DE1-SoC BoardB

10 30Thursday, November 20, 2014

C2280.1u

R94 0DNI

C2450.1u

C66

0.1u

R287 0DNI

R288 0

R132 2K

R297 0DNI

R78 0

R1130DNI

R231 120DNI

R289 0

C2320.1u

D5 LEDG2 1

R230 120DNI

R91 1M

R77 0

C2140.1u

R233 120

C192 0.1u

R232 120

R130 0

U39

TPD2EUSB30D-

2D+1

GND3

R134 2K

C2300.1u

R1121K

D6 LEDGDNI2 1

C2420.1u

R286 0DNI

C2290.1u

C2440.1u

R79 0

U17D

EPM570GF100C5N

GCLK2pF8

GCLK3pE10

DEV_CLRnK9

DEV_OEJ7

GCLK0pE2

GCLK1pE1

TCKH3 TDIH2

TMSJ1

TDOJ2

C60 4.7n

R80 0

U14

ADM6711SAKSZ

GND1

RST_n2

MR_n3

VCC4

U17C

EPM570GF100C5N

IO_B2_A1A1

IO_B2_A10A10

IO_B2_A2A2

IO_B2_A3A3

IO_B2_A4A4

IO_B2_A5A5

IO_B2_A6A6

IO_B2_A7A7

IO_B2_A8A8

IO_B2_A9A9

IO_B2_B10B10

IO_B2_B2B2

IO_B2_B3B3

IO_B2_B4B4

IO_B2_B5B5

IO_B2_B6B6

IO_B2_B7B7

IO_B2_B8B8

IO_B2_B9B9

IO_B2_C10C10

IO_B2_C3C3

IO_B2_C4C4

IO_B2_C7C7

IO_B2_C8C8 IO_B2_C9C9

IO_B2_D10D10

IO_B2_D8D8IO_B2_D9

D9 IO_B2_E8E8

IO_B2_E9E9

IO_B2_F10F10

IO_B2_F9F9

IO_B2_G10G10

IO_B2_G8G8

IO_B2_G9G9

IO_B2_H10H10IO_B2_H9H9

IO_B2_J10J10

C2120.1u

R285 0DNI

R229 100K

C2310.1u

C68

33pDNI

J18

CPLD ISPDNI

1 23 45 67 89 10

R115 2K

R102 0

DNI

C610.1u

R75 1K

R116 0

R131 2K

C2150.1u

R76 1K

D7 LEDGDNI2 1

C67

0.1u

Y3

OSC_24MHz

OE/FS1

GND2

CLK3

VDD4

C2130.1u

R93 10K

R114 2K

D4 LEDG2 1

R9220K

R133 2K

U16

CY7C68013A-56BAXC

RDY0A1

RDY1B1

XTALINC1

AVCCD1

DMINUSE1

AGNDF1

VCCG1

GNDH1

PD7A2

CLKOUTB2

XTALOUTC2

AVCCD2

DPLUSE2

AGNDF2

IFCLKG2

RESERVEDH2

PD5A3PD4B3

PD6C3

SCLF3

SDAG3

PB0H3

GNDA4

GNDB4

GNDC4

PB1F4

PB3G4PB2H4

VCCA5

VCCB5

PB6F5PB5G5PB4H5

PD3A6PD2B6

PA7C6

PA4F6

PA1G6

PB7H6

PD1A7

WAKEUPB7

PA6C7

GNDD7

VCCE7

PA3F7

CTL1G7CTL0H7

PD0A8

RESETB8

PA5C8

GNDD8

VCCE8

PA2F8

PA0G8

CTL2H8

VCCC5

C2410.1u

U17A

EPM570GF100C5N

GNDINTC5

GNDINTF5 GNDINTE6

GNDIOD5

GNDIOG7

GNDIOD7

GNDIOG5 GNDIOF6 GNDIOE5

GNDINTH5

VCCINTC6

VCCINTE7

VCCINTH6VCCINTF4

VCCIO2F7VCCIO2D6VCCIO2D4

VCCIO1E4

VCCIO1G4

VCCIO1G6

VBUS GND

D- D+

J13

USB B-TYPE4

32

1

56

C2430.1u

U17B

EPM570GF100C5N

IO_B1_B1B1

IO_B1_C1C1

IO_B1_C2C2

IO_B1_D1D1

IO_B1_D2D2

IO_B1_D3D3

IO_B1_E3E3

IO_B1_F1F1

IO_B1_F2F2

IO_B1_F3F3

IO_B1_G1G1

IO_B1_G2G2

IO_B1_G3G3

IO_B1_H1H1

IO_B1_H4H4

IO_B1_H7H7

IO_B1_H8H8

IO_B1_J3J3

IO_B1_J4J4

IO_B1_J5J5

IO_B1_J6J6

IO_B1_J8J8

IO_B1_J9J9

IO_B1_K1K1

IO_B1_K10K10

IO_B1_K2K2

IO_B1_K3K3

IO_B1_K4K4

IO_B1_K5K5

IO_B1_K6K6

IO_B1_K7K7

IO_B1_K8K8

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FPGA JTAG INTERFACE

USB Blaster

HPS JTAG INTERFACE

JTAG Chain

HPS_TDIFPGA_TDO

JTAG_TCK

JTAG_TDI

HPS_TCK

JTAG_TMS HPS_TMS

HPS_TDO

JTAG_TCKJTAG_Blaster_TDI

JTAG_Blaster_TDO

JTAG_TMS

USB_DISABLE_n

JTAG_Blaster_TDO FPGA_TDI

JTAG_Blaster_TMS JTAG_TMS

JTAG_Blaster_TCK JTAG_TCK

JTAG_Blaster_TDI JTAG_TDI

JTAG_Blaster_TDO

FPGA_TDI

JTAG_Blaster_TDI

VCC3P3VCC3P3VCC3P3

USB_DISABLE_n10

FPGA_TDO 7

FPGA_TDI 7JTAG_TMS 7JTAG_TCK 7

HPS_TDO 5

HPS_TCK 5HPS_TMS 5HPS_TDI 5

HPS_WARM_RST_N5,10,26

JTAG_Blaster_TCK 10

JTAG_Blaster_TDI 10

JTAG_Blaster_TMS 10JTAG_Blaster_TDO 10

JTAG_TRST5,10

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

JTAG Chain F

DE1-SoC BoardB

11 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

JTAG Chain F

DE1-SoC BoardB

11 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

JTAG Chain F

DE1-SoC BoardB

11 30Thursday, November 20, 2014

R126 0DNI

R127 0

R61K

J5

JTAG Header

DNI

1 23 45 67 89 10

R128 0

DNI

R298 0

DNI

R71K

R129 0

R295 0

R244 0

R296 0

R294 0

R242 0

R110K

R241 0

DNI

R2 0

R243 0DNI

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Clock_inClock_in

GPIO 0

GPIO 0

GPIO_0_D30

GPIO_0_D0

GPIO_0_D1

GPIO_0_D2

GPIO_0_D3

GPIO_0_D4

GPIO_0_D5

GPIO_0_D6

GPIO_0_D7

GPIO_0_D8

GPIO_0_D9

GPIO_0_D10

GPIO_0_D11

GPIO_0_D12

GPIO_0_D13

GPIO_0_D14

GPIO_0_D15

GPIO_0_D16

GPIO_0_D17

GPIO_0_D18

GPIO_0_D19

GPIO_0_D20

GPIO_0_D21

GPIO_0_D22

GPIO_0_D23

GPIO_0_D24

GPIO_0_D25

GPIO_0_D26

GPIO_0_D27

GPIO_0_D28

GPIO_0_D29

GPIO_0_D30

GPIO_0_D31

GPIO_0_D32

GPIO_0_D33

GPIO_0_D34

GPIO_0_D35

GPIO_0_D0GPIO_0_D2GPIO_0_D4GPIO_0_D6GPIO_0_D8

GPIO_0_D1GPIO_0_D3GPIO_0_D5GPIO_0_D7GPIO_0_D9

GPIO_0_D14GPIO_0_D12GPIO_0_D10

GPIO_0_D18GPIO_0_D16

GPIO_0_D22GPIO_0_D20

GPIO_0_D24

GPIO_0_D15GPIO_0_D13GPIO_0_D11

GPIO_0_D19GPIO_0_D17

GPIO_0_D23GPIO_0_D21

GPIO_0_D25

GPIO_0_D26GPIO_0_D28

GPIO_0_D32GPIO_0_D34

GPIO_0_D33GPIO_0_D31GPIO_0_D29GPIO_0_D27

GPIO_0_D35

GPIO_014GPIO_015

GPIO_08GPIO_09GPIO_010

GPIO_032GPIO_033GPIO_034GPIO_035

GPIO_017

GPIO_022

GPIO_020

GPIO_023

GPIO_021

GPIO_011

GPIO_012GPIO_013

GPIO_00

GPIO_06

GPIO_04

GPIO_02GPIO_01

GPIO_03

GPIO_018

GPIO_016

GPIO_019

GPIO_07

GPIO_05

GPIO_025

GPIO_030

GPIO_028

GPIO_026

GPIO_024

GPIO_031

GPIO_029

GPIO_027

GPIO_0_D0GPIO_0_D1GPIO_0_D2GPIO_0_D3

GPIO_0_D4GPIO_0_D5GPIO_0_D6GPIO_0_D7

GPIO_0_D8GPIO_0_D9GPIO_0_D10GPIO_0_D11

GPIO_0_D12GPIO_0_D13GPIO_0_D14GPIO_0_D15

GPIO_0_D20GPIO_0_D21

GPIO_0_D16GPIO_0_D17GPIO_0_D18GPIO_0_D19

GPIO_0_D22GPIO_0_D23

GPIO_0_D24GPIO_0_D25GPIO_0_D26GPIO_0_D27

GPIO_0_D28GPIO_0_D29GPIO_0_D30GPIO_0_D31

GPIO_0_D32GPIO_0_D33GPIO_0_D34GPIO_0_D35

VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3

VCC3P3

VCC5

GPIO_0[35..0] 3,6

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

GPIO 0 F

DE1-SoC BoardB

12 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

GPIO 0 F

DE1-SoC BoardB

12 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

GPIO 0 F

DE1-SoC BoardB

12 30Thursday, November 20, 2014

D61

BAT54S

1

23

D85

BAT54S

1

23

D69

BAT54S

1

23

D57

BAT54S

1

23

D81

BAT54S

1

23

RN16

47

1234 5

678

D53

BAT54S

1

23

D73

BAT54S

1

23

D10

BAT54S

1

23

RN11

47

1234 5

678

D17

BAT54S

1

23

D33

BAT54S

1

23

D22

BAT54S

1

23

D27

BAT54S

1

23

D12

BAT54S

1

23

D20

BAT54S

1

23

RN4

47

1234 5

678

RN18

47

1234 5

678

D77

BAT54S

1

23

D36

BAT54S

1

23

D65

BAT54S

1

23

D94

BAT54S

1

23

JP1

BOX Header 2X20M

1 23 45 67 89 10

1113

1214161820222426

27

151719212325

28293133353739

303234363840

D25

BAT54S

1

23

D82

BAT54S

1

23

D90

BAT54S

1

23

D62

BAT54S

1

23

D50

BAT54S

1

23

D66

BAT54S

1

23

D78

BAT54S

1

23

D15

BAT54S

1

23

D46

BAT54S

1

23

RN15

47

1234 5

678

RN9

47

1234 5

678

D91

BAT54S

1

23

RN2

47

1234 5

678

D8

BAT54S

1

23

D74

BAT54S

1

23

D49

BAT54S

1

23

D58

BAT54S

1

23

D70

BAT54S

1

23

RN13

47

1234 5

678

D30

BAT54S

1

23

D86

BAT54S

1

23

RN7

47

1234 5

678

D54

BAT54S

1

23

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GPIO 1

GPIO 1

Clock_in

GPIO_1_D30

GPIO_1_D0

GPIO_1_D1

GPIO_1_D2

GPIO_1_D3

GPIO_1_D4

GPIO_1_D5

GPIO_1_D6

GPIO_1_D7

GPIO_1_D8

GPIO_1_D9

GPIO_1_D10

GPIO_1_D11

GPIO_1_D12

GPIO_1_D13

GPIO_1_D14

GPIO_1_D15

GPIO_1_D16

GPIO_1_D17

GPIO_1_D18

GPIO_1_D19

GPIO_1_D20

GPIO_1_D21

GPIO_1_D22

GPIO_1_D23

GPIO_1_D24

GPIO_1_D25

GPIO_1_D26

GPIO_1_D27

GPIO_1_D28

GPIO_1_D29

GPIO_1_D30

GPIO_1_D31

GPIO_1_D32

GPIO_1_D33

GPIO_1_D34

GPIO_1_D35

GPIO_1_D0GPIO_1_D2GPIO_1_D4GPIO_1_D6GPIO_1_D8

GPIO_1_D1GPIO_1_D3GPIO_1_D5GPIO_1_D7GPIO_1_D9

GPIO_1_D14GPIO_1_D12GPIO_1_D10

GPIO_1_D18GPIO_1_D16

GPIO_1_D22GPIO_1_D20

GPIO_1_D24

GPIO_1_D15GPIO_1_D13GPIO_1_D11

GPIO_1_D19GPIO_1_D17

GPIO_1_D23GPIO_1_D21

GPIO_1_D25

GPIO_1_D26GPIO_1_D28

GPIO_1_D32GPIO_1_D34

GPIO_1_D33GPIO_1_D31GPIO_1_D29GPIO_1_D27

GPIO_1_D35

GPIO_114GPIO_115

GPIO_18GPIO_19GPIO_110

GPIO_132GPIO_133GPIO_134GPIO_135

GPIO_117

GPIO_122

GPIO_120

GPIO_123

GPIO_121

GPIO_111

GPIO_112GPIO_113

GPIO_10

GPIO_16

GPIO_14

GPIO_12GPIO_11

GPIO_13

GPIO_118

GPIO_116

GPIO_119

GPIO_17

GPIO_15

GPIO_125

GPIO_130

GPIO_128

GPIO_126

GPIO_124

GPIO_131

GPIO_129

GPIO_127

GPIO_1_D0GPIO_1_D1GPIO_1_D2GPIO_1_D3

GPIO_1_D4GPIO_1_D5GPIO_1_D6GPIO_1_D7

GPIO_1_D8GPIO_1_D9GPIO_1_D10GPIO_1_D11

GPIO_1_D12GPIO_1_D13GPIO_1_D14GPIO_1_D15

GPIO_1_D20GPIO_1_D21

GPIO_1_D16GPIO_1_D17GPIO_1_D18GPIO_1_D19

GPIO_1_D22GPIO_1_D23

GPIO_1_D24GPIO_1_D25GPIO_1_D26GPIO_1_D27

GPIO_1_D28GPIO_1_D29GPIO_1_D30GPIO_1_D31

GPIO_1_D32GPIO_1_D33GPIO_1_D34GPIO_1_D35

VCC3P3

VCC5

VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3

GPIO_1[35..0] 3,6

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

GPIO 1 F

DE1-SoC BoardB

13 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

GPIO 1 F

DE1-SoC BoardB

13 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

GPIO 1 F

DE1-SoC BoardB

13 30Thursday, November 20, 2014

D16

BAT54S

1

23

D21

BAT54S

1

23

D52

BAT54S

1

23

D9

BAT54S

1

23

RN8

47

1234 5

678

D93

BAT54S

1

23

D59

BAT54S

1

23

D71

BAT54S

1

23

JP2

BOX Header 2X20M

1 23 45 67 89 10

1113

1214161820222426

27

151719212325

28293133353739

303234363840

D48

BAT54S

1

23

RN10

47

1234 5

678

D67

BAT54S

1

23

D47

BAT54S

1

23

D26

BAT54S

1

23

D72

BAT54S

1

23

D56

BAT54S

1

23

D89

BAT54S

1

23

D83

BAT54S

1

23

RN12

47

1234 5

678

D34

BAT54S

1

23

D68

BAT54S

1

23

D51

BAT54S

1

23

D13

BAT54S

1

23

RN14

47

1234 5

678

D28

BAT54S

1

23

D18

BAT54S

1

23

D64

BAT54S

1

23

D37

BAT54S

1

23

D23

BAT54S

1

23

RN17

47

1234 5

678

D60

BAT54S

1

23

D88

BAT54S

1

23

RN3

47

1234 5

678

D31

BAT54S

1

23

D75

BAT54S

1

23

D55

BAT54S

1

23

D76

BAT54S

1

23

D80

BAT54S

1

23

RN5

47

1234 5

678

D79

BAT54S

1

23

D45

BAT54S

1

23

RN19

47

1234 5

678

D63

BAT54S

1

23

D11

BAT54S

1

23

RN6

47

1234 5

678

D84

BAT54S

1

23

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Note: place a pull down resistor on the FLASH_DCLK wire at the Master

HPS_FLASH_DATA0

HPS_FLASH_DATA2HPS_FLASH_DATA1

HPS_FLASH_DATA3 HPS_FLASH_DCLK

HPS_FLASH_NCSO

HPS_FLASH_NCSO

HPS_FLASH_DATA0

HPS_FLASH_DATA1

HPS_FLASH_DATA2

HPS_FLASH_DATA3

HPS_FLASH_DCLK

DRAM_CKE

DRAM_CAS_N

DRAM_RAS_N

DRAM_CS_N

DRAM_WE_N

DRAM_ADDR0

DRAM_ADDR3

DRAM_ADDR1DRAM_ADDR2

DRAM_ADDR10

DRAM_DQ0

DRAM_DQ5

DRAM_DQ3

DRAM_DQ6DRAM_DQ7

DRAM_DQ4

DRAM_DQ2DRAM_DQ1

DRAM_ADDR5

DRAM_ADDR12

DRAM_ADDR8

DRAM_ADDR6DRAM_ADDR7

DRAM_ADDR9

DRAM_ADDR4

DRAM_ADDR11 DRAM_DQ11

DRAM_DQ15

DRAM_DQ8

DRAM_DQ13

DRAM_DQ10DRAM_DQ9

DRAM_DQ12

DRAM_DQ14

QSPI_RESET_N VCC3P3

VCC3P3

VCC3P3

DR_VCC3P3 DR_VCC3P3

DR_VCC3P3

DR_VCC3P3

VCC3P3

VCC3P3

HPS_FLASH_DCLK 5HPS_FLASH_NCSO 5

HPS_FLASH_DATA[3..0] 5

DRAM_ADDR[12..0] 3,6

DRAM_DQ[15..0] 3

DRAM_CLK 6DRAM_CKE 3DRAM_LDQM 3DRAM_UDQM 3

DRAM_WE_N 3DRAM_CAS_N 3DRAM_RAS_N 3DRAM_CS_N 3DRAM_BA0 3DRAM_BA1 6

QSPI_RESET_N 10

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

SDRAM & HPS QSPI Flash F

DE1-SoC BoardB

14 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

SDRAM & HPS QSPI Flash F

DE1-SoC BoardB

14 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

SDRAM & HPS QSPI Flash F

DE1-SoC BoardB

14 30Thursday, November 20, 2014

C397

10u

R61 DNI

C106

10u

R254 4.7K

R221 10K

C405

0.1u

C184

0.1u

R257 4.7K

R170 0

C398

0.1u

U27

SDRAM 32Mx16

A023

A124

A225

A326

A429

A530

A631

A732

A833

A934

nCAS17

nRAS18

LDQM15

nWE16

nCS19

CKE37 CLK38

UDQM39

D02

D14

D25

D37

D48

D510

D611

D713

D842

D944

D1045

D1147

D1248

D1350

D1451

D1553

A1236

BA020

VDD

1

VDD

27VS

S28

VSS

41

A1022

VDD

Q3

VDD

Q9

VDD

Q43

VDD

Q49

VSSQ

6

VSSQ

12

VSSQ

46

VSSQ

52

A1135

BA121

VSS

54VD

D14

C404

0.1u

R225 330DNI

R224 DNI

R226 DNI

C392

0.1u

R2902K

C396

0.1u

C399

0.1u

R255 4.7K

C393

0.1u

R256 4.7K

U13

N25Q512A83GSF40F

DNI

HOLD_n/DQ31

VCC2

RESET3

DNU_24

DNU_35

DNU_46

S_n7

DQ18

W_n/Vpp/DQ29VSS10DNU_511DNU_612DNU_713DNU_814DQ015C16

R251 4.7K

R220 DNI

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

place close to DDR3 chip

Note:you can swap the signals on the OCT resistor array(include NC pin) Note:you can only swap the DQ signals within x8 group (e.g. 0-7,8-15,16-23,24-31) on the DDR3 chips

HPS_DDR3_ADDR0HPS_DDR3_ADDR1HPS_DDR3_ADDR2HPS_DDR3_ADDR3HPS_DDR3_ADDR4HPS_DDR3_ADDR5HPS_DDR3_ADDR6HPS_DDR3_ADDR7HPS_DDR3_ADDR8HPS_DDR3_ADDR9HPS_DDR3_ADDR10HPS_DDR3_ADDR11HPS_DDR3_ADDR12HPS_DDR3_ADDR13HPS_DDR3_ADDR14

HPS_DDR3_ADDR14HPS_DDR3_RAS_NHPS_DDR3_CAS_NHPS_DDR3_WE_NHPS_DDR3_ADDR9HPS_DDR3_ADDR13HPS_DDR3_ADDR2HPS_DDR3_ADDR0

HPS_DDR3_DQ31HPS_DDR3_DQ30HPS_DDR3_DQ29HPS_DDR3_DQ28HPS_DDR3_DQ27

HPS_DDR3_ADDR10

HPS_DDR3_DQ26HPS_DDR3_DQ25HPS_DDR3_DQ24HPS_DDR3_DQ23HPS_DDR3_DQ22HPS_DDR3_DQ21HPS_DDR3_DQ20HPS_DDR3_DQ19

HPS_DDR3_ADDR12HPS_DDR3_BA1HPS_DDR3_ADDR1

HPS_DDR3_DQ18HPS_DDR3_DQ17HPS_DDR3_DQ16

HPS_DDR3_ADDR4HPS_DDR3_ADDR6HPS_DDR3_ADDR8HPS_DDR3_ADDR11

HPS_DDR3_ADDR7HPS_DDR3_ADDR5HPS_DDR3_ADDR3HPS_DDR3_BA2HPS_DDR3_BA0HPS_DDR3_CS_NHPS_DDR3_ODT

HPS_DDR3_BA0HPS_DDR3_BA1HPS_DDR3_BA2

HPS_DDR3_DM2HPS_DDR3_DM3

HPS_DDR3_CK_NHPS_DDR3_CKE

HPS_DDR3_CK_P

HPS_DDR3_CS_NHPS_DDR3_RESET_NHPS_DDR3_WE_NHPS_DDR3_RAS_NHPS_DDR3_CAS_N

HPS_DDR3_BA0HPS_DDR3_BA1HPS_DDR3_BA2

HPS_DDR3_DM0HPS_DDR3_DM1

HPS_DDR3_ODT

HPS_DDR3_CK_NHPS_DDR3_CK_P

HPS_DDR3_RESET_N

HPS_DDR3_CKE

HPS_DDR3_DQ15HPS_DDR3_DQ14HPS_DDR3_DQ13HPS_DDR3_DQ12HPS_DDR3_DQ11HPS_DDR3_DQ10HPS_DDR3_DQ9HPS_DDR3_DQ8HPS_DDR3_DQ7HPS_DDR3_DQ6HPS_DDR3_DQ5HPS_DDR3_DQ4HPS_DDR3_DQ3HPS_DDR3_DQ2HPS_DDR3_DQ1HPS_DDR3_DQ0

HPS_DDR3_DQS_P0HPS_DDR3_DQS_N0HPS_DDR3_DQS_P1HPS_DDR3_DQS_N1

HPS_DDR3_DQS_P2HPS_DDR3_DQS_N2HPS_DDR3_DQS_P3HPS_DDR3_DQS_N3

HPS_DDR3_ZQ1 HPS_DDR3_ZQ0

HPS_DDR3_ADDR0HPS_DDR3_ADDR1HPS_DDR3_ADDR2HPS_DDR3_ADDR3HPS_DDR3_ADDR4HPS_DDR3_ADDR5HPS_DDR3_ADDR6HPS_DDR3_ADDR7HPS_DDR3_ADDR8HPS_DDR3_ADDR9HPS_DDR3_ADDR10HPS_DDR3_ADDR11HPS_DDR3_ADDR12HPS_DDR3_ADDR13HPS_DDR3_ADDR14

VCC1P5_DDR3

DDR3_VTT_HPSDDR3_VTT_HPS DDR3_VTT_HPS DDR3_VTT_HPS DDR3_VTT_HPS

DDR3_VTT_HPS

DDR3_VREF_HPS

VCC1P5_DDR3

DDR3_VREF_HPS

VCC1P5_DDR3

VCC1P5_DDR3

VCC1P5_DDR3

VCC1P5_DDR3

DDR3_VREF_HPS

VCC1P5_DDR3

DDR3_VREF_HPS

HPS_DDR3_CK_P 4HPS_DDR3_CK_N 4HPS_DDR3_CKE 4

HPS_DDR3_CS_N 4HPS_DDR3_RESET_N 4HPS_DDR3_WE_N 4HPS_DDR3_RAS_N 4HPS_DDR3_CAS_N 4

HPS_DDR3_ODT 4

HPS_DDR3_BA[2..0] 4

HPS_DDR3_DQS_N[3..0] 4

HPS_DDR3_DQS_P[3..0] 4

HPS_DDR3_DM[3..0] 4

HPS_DDR3_DQ[31..0] 4

HPS_DDR3_ADDR[14..0] 4

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

HPS DDR3 SDRAM F

DE1-SoC BoardB

15 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

HPS DDR3 SDRAM F

DE1-SoC BoardB

15 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

HPS DDR3 SDRAM F

DE1-SoC BoardB

15 30Thursday, November 20, 2014

V18

RN32

51

123456789

10111213141516

C301

0.01u

C234

2.2n

V26

C303

2.2n

C218

3.3n

V25

C357

0.47uC355

0.1u

C325

3.3n

C246

0.1u

V17

C358

0.47u

V1

CN3

0.1u

1 2 3 45678

V5

V20V11

R143 2K

C352

2.2n

V8

V4

C217

0.47u

V9

C236

0.1u

V21

V19R239 100

C354

0.1u

V27V23

C222

0.1u

C324

0.1u

CN1

0.1u

1 2 3 45678

C225

0.01u

C327

0.01u

C247

2.2n

CN2

0.1u

1 2 3 45678

C353

2.2n

C248

4.7n

V3

V10

C297

0.1u

C233

2.2n

C300

4.7n

C235

2.2n

V7

C221

2.2n

R235240

RN33

51

123456789

10111213141516

C299

0.47u

U21

IS43TR16256A-15HBL

VSSA9

VDDB2

NC3L1

UDMD3

VSSB3

VDDD9

VSSE1

VSSQB1

DQ0E3

LDME7

VSSQB9

VDDQA1

VDDQA8

DQ2F2

LDQSF3

DQ3F8

DQ1F7

VSSQD8VSSQD1

DQ6G2

LDQSnG3

VDDG7

VSSG8

VSSQE2

VREFDQH1

VDDQC1

DQ4H3

DQ7H7

DQ5H8

VDDQC9

VSSJ8

RASJ3

CLKJ7

VSSJ2

ODTK1

VDDK8

CASK3

CLK_nK7

CKEK9

CSL2

WEL3

A10/APL7

ZQL8

VSSM1

BA0M2

BA2M3

NC4L9

VREFCAM8

VSSM9

A3N2

A0N3

A12/BC_nN7

BA1N8

VSSP1

A5P2

A2P3 A1P7

A4P8

VSSP9

A7R2

A9R3

A11R7

A6R8

VSST1

A13T3

A8T8

VSST9

A14T7

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VDDQH9

VDDK2

VDDN1

VDDN9

VDDR1

VDDR9

VSSQE8

VSSQF9

VSSQG1

VSSQG9

NC1J1

NC2J9

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

UDQSC7

UDQSnB7

RESETT2

NC5M7

C220

0.1u

C298

2.2n

V16V24

C302

2.2n

V15

C224

0.47u

V22

R247240

V2

RN31

51

123456789

10111213141516

V6

C250

0.47u

U18

IS43TR16256A-15HBL

VSSA9

VDDB2

NC3L1

UDMD3

VSSB3

VDDD9

VSSE1

VSSQB1

DQ0E3

LDME7

VSSQB9

VDDQA1

VDDQA8

DQ2F2

LDQSF3

DQ3F8

DQ1F7

VSSQD8VSSQD1

DQ6G2

LDQSnG3

VDDG7

VSSG8

VSSQE2

VREFDQH1

VDDQC1

DQ4H3

DQ7H7

DQ5H8

VDDQC9

VSSJ8

RASJ3

CLKJ7

VSSJ2

ODTK1

VDDK8

CASK3

CLK_nK7

CKEK9

CSL2

WEL3

A10/APL7

ZQL8

VSSM1

BA0M2

BA2M3

NC4L9

VREFCAM8

VSSM9

A3N2

A0N3

A12/BC_nN7

BA1N8

VSSP1

A5P2

A2P3 A1P7

A4P8

VSSP9

A7R2

A9R3

A11R7

A6R8

VSST1

A13T3

A8T8

VSST9

A14T7

VDDQD2

VDDQE9

VDDQF1

VDDQH2

VDDQH9

VDDK2

VDDN1

VDDN9

VDDR1

VDDR9

VSSQE8

VSSQF9

VSSQG1

VSSQG9

NC1J1

NC2J9

DQ8D7

DQ9C3

DQ10C8

DQ11C2

DQ12A7

DQ13A2

DQ14B8

DQ15A3

UDQSC7

UDQSnB7

RESETT2

NC5M7

C219

0.1u

V13

R238 4.7K

C356

0.1u

C216

0.01u

V14

C326

0.01u

C249

2.2n

C323

2.2n

C223

0.01u

V12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VGA_

R7

VGA_

B1VG

A_B0

VGA_

B5VG

A_B4

VGA_

B3VG

A_B2

VGA_

B7VG

A_B6

VGA_

R6

VGA_

R2

VGA_

R3

VGA_

R4

VGA_

R5

VGA_

R0

VGA_

R1

VGA_G0

VGA_G3VGA_G2VGA_G1

VGA_G6VGA_G5VGA_G4

VGA_G7

VGA_G

RSET

VGA_B

VGA_R

VGA_VCC3P3

VGA_VCC3P3

VGA_VCC3P3VGA_VCC3P3

VCC3P3 VGA_VCC3P3

VGA_R[7..0] 5VGA_G[7..0] 5VGA_B[7..0] 5,6

VGA_SYNC_N 5

VGA_

CLK

6

VGA_HS 5VGA_VS 5

VGA_BLANK_N 5

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

ADV7123 VGA F

DE1-SoC BoardB

16 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

ADV7123 VGA F

DE1-SoC BoardB

16 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

ADV7123 VGA F

DE1-SoC BoardB

16 30Thursday, November 20, 2014

R18 47

U5

ADV7123G6

7

SYNC12

G12

G23

B721

B822

B923

CLO

CK

24

GND25GND26IOB27IOB28

B317

B418

B519

B620

B216

B115

B014

VAA

13

G01

G34

BLANK11 G910

G45

G56

G78

G89 VAA

29VAA30IOG31IOG32IOR33IOR34COMP35VREF36

RSE

T37

PSAV

E38

R0

39R

140

R2

41R

342

R4

43R

544

R6

45R

746

R8

47R

948

R17 47

C11 0.1u

C47

10u

R14

75

C176

0.1u

R57 0

R15

75

C164

0.1u

R16

75

C165

0.1u

C12

0.1u

R40 4.7KR25 560

C13

0.1u

10

11

6

1

5 15

J9

VGA

5

9

4

8

3

7

2

6

1

1716

101112131415

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

I2C ADDRESS W/R = 0x40/0x41

TD_DATA1

28MHz

28MHz

TD_DATA2TD_DATA3TD_DATA4TD_DATA5TD_DATA6TD_DATA7

TD_DATA0VGND

V_VCC3P3 VGND

PV_VCC1P8

V_VCC3P3

V_VCC3P3

V_VCC1P8

V_VCC3P3

AV_VCC1P8 PV_VCC1P8

V_VCC1P8VCC1P8V_VCC3P3

AV_VCC1P8V_VCC1P8

VCC3P3

VGND

VGNDVGND VGND

VGND

VGND

VGND

TD_DATA[7..0] 5

TD_RESET_N 5

I2C_SCLK 18,26I2C_SDAT 18,26

TD_VS5TD_HS5

TD_CLK276

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

ADV7180 Video Decoder F

DE1-SoC BoardB

17 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

ADV7180 Video Decoder F

DE1-SoC BoardB

17 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

ADV7180 Video Decoder F

DE1-SoC BoardB

17 30Thursday, November 20, 2014

C23 0.1u

R12 39

R39

1.74K

C37

0.1u

C28

10u

R69 0

L10 BEAD

C38

0.01u

C27

0.1u

C45

10u

C177

0.1u

R13 36

R54 0

U4

ADV7180

HS39

DG

ND

3

XTAL112

XTAL13

DVD

D14

DG

ND

35

P116P017

P48P39P210

LLC11

P57

P66

P75

INTRQ38

DVD

DIO

1

DVD

DIO

4

DG

ND

15

SFL2

PWRDWN18

PVD

D20

AGN

D21

DG

ND

40

AIN123

AIN229

AGN

D24

TEST_022

VREFP25

AVD

D27

AGN

D28

VREFN26

AIN330

RESET31

ALSB32

SDATA33 SCLK34

DVD

D36

VS/FIELD37

ELPF19

EXPO

SED

41

D1BAT54S

123

R55 120

C182

0.1u

C51

10u

C152

0.1u

L6 BEAD

C25 0.1u

C24

0.1u

C39 0.1u

C26 0.1u

Y1

28.63636MHZ

VCC4

OUT3

GND2

EN1

J6

RCA JACKRN1 4712345678 9

10111213141516

R56 120

C183

0.1u

C46

0.1u

L5 BEAD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

I2C ADDRESS = 0x34 (write only)

LINE IN

MIC IN

LINE OUT

AGND

AGND

AGND

AGNDAGND

AGND AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

VCC3P3

A_VCC3P3

A_VCC3P3

A_VCC3P3

A_VCC3P3

VCC3P3VCC3P3

VCC3P3

VCC3P3

I2C_SCLK 17,26I2C_SDAT 17,26

AUD_ADCDAT 5

AUD_XCK 5

AUD_DACDAT 5AUD_BCLK 5

AUD_DACLRCK 5

AUD_ADCLRCK 5

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Audio CODEC F

DE1-SoC BoardB

18 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Audio CODEC F

DE1-SoC BoardB

18 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Audio CODEC F

DE1-SoC BoardB

18 30Thursday, November 20, 2014

C6

1u

C19

10u

C21 1u

C153

0.1u

R23

47K

J2

PHONE JACK B

L1

R2

GN

D3

NC

R4

NC

L5

C166

0.1u

R8

47K

L8 BEAD

C8 10u

R11 4.7K

J3

PHONE JACK G

L1

R2

GN

D3

NC

R4

NC

L5

C10 100u

R37

2K

R22

4.7K

C7

1n

L9 BEAD

J1

PHONE JACK P

L1

R2

GN

D3

NC

R4

NC

L5

C20 1u

C9

0.1u

R38

2K

R20 330

C167

0.1u

R24

47K

C22 100u

R21

4.7K

R9 680

U3

WM8731

BCLK7

HPV

DD

12

XTO2

DCVDD3

MBIAS21

MIC

IN22

RLI

NEI

N23

LLIN

EIN

24M

OD

E25

CSB

26SD

IN27

SCLK

28

ROUT17AVDD18AGND19VMID20

LOUT16

HPGND15

RH

POU

T14

LHPO

UT

13

XTI/MCLK1

DGND4

ADC

LRC

K11

ADC

DAT

10

DBVDD5

CLKOUT6

DAC

DAT

8

DAC

LRC

K9

EXPO

SED

29

R10 4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

F4

G5

G4

F0

D2

A2

E5

C2B2

D4

E3

C4

A3

B4

F1E1

C1

A1

D1

B1

D3

E4

C3B3

B5

D5

F2

C5

A5

E2

E0

G0

A0B0C0D0

HEX14HEX13HEX12

HEX00HEX16

HEX15

HEX01

HEX35

HEX30

HEX34

HEX33HEX32HEX31

HEX36

HEX53

HEX55HEX54

HEX52

HEX41HEX40HEX56

HEX06HEX05HEX04HEX03

HEX21HEX22HEX23HEX24

HEX25HEX26

HEX46

HEX43

HEX45HEX44

HEX10

HEX50

G1

G2

F3F5 G3

HEX20HEX42

HEX11

HEX02

HEX51

A4

LEDR4LEDR5

LEDR7LEDR6

LEDR8LEDR9

LEDR3LEDR2LEDR1LEDR0

VCC3P3

VCC3P3

VCC3P3VCC3P3

VCC3P3VCC3P3

HEX0[6..0] 4,7

HEX1[6..0] 4,7

HEX2[6..0] 4,6

HEX3[6..0] 4,7

HEX4[6..0] 4

HEX5[6..0] 4,6

LEDR[9..0] 3,4

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

7-Segment Display, LED F

DE1-SoC BoardB

19 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

7-Segment Display, LED F

DE1-SoC BoardB

19 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

7-Segment Display, LED F

DE1-SoC BoardB

19 30Thursday, November 20, 2014

RN29 1K1234 5

678

ed

dp

c

g

b

f

a

CA1

CA2

HEX3

7Segment Display

1

23

45

6

1098

7

RN27 1K1234 5

678

LEDR6 LEDR2 1

LEDR4 LEDR2 1

RN26 1K1234 5

678

LEDR3 LEDR2 1

ed

dp

c

g

b

f

a

CA1

CA2

HEX2

7Segment Display

1

23

45

6

1098

7

ed

dp

c

g

b

f

a

CA1

CA2

HEX1

7Segment Display

1

23

45

6

1098

7

RN37 330

1234 5

678

LEDR1 LEDR2 1

RN25 1K1234 5

678

RN23 1K1234 5

678

ed

dp

c

g

b

f

a

CA1

CA2

HEX4

7Segment Display

1

23

45

6

1098

7

LEDR8 LEDR2 1

LEDR9 LEDR2 1

RN21 1K1234 5

678

RN24 1K1234 5

678

ed

dp

c

g

b

f

a

CA1

CA2

HEX5

7Segment Display

1

23

45

6

1098

7

R275 330

LEDR7 LEDR2 1

LEDR5 LEDR2 1

R277 330

ed

dp

c

g

b

f

a

CA1

CA2

HEX0

7Segment Display

1

23

45

6

1098

7

RN22 1K1234 5

678

LEDR0 LEDR2 1

LEDR2 LEDR2 1

R176 1K

RN20 1K1234 5

678

RN28 1K1234 5

678

RN35 330

1234 5

678

R175 1K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SW7SW6SW5SW4

SW3SW2SW1SW0

KEYIN3

GNDGND

VCC3P3GND GND

GND

VCC3P3

GND

GND

GNDGND

VCC3P3

GND

GNDVCC3P3

GNDGND

GND

GND

VCC3P3

GND

GNDVCC3P3

GND

GND

GND

GNDVCC3P3

GNDGND

VCC3P3

GND

GND

GND

GNDVCC3P3

GNDGND

KEYIN1

GND

VCC3P3

KEYIN2

KEYIN0 KEY0

KEY2KEY3

KEY1

KEYIN3

KEYIN1KEYIN0

KEYIN2

SW9SW8

VCC3P3

VCC3P3

VCC3P3

KEY[3..0] 3,6

SW[9..0] 3,7

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BUTTON, Switch F

DE1-SoC BoardB

20 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BUTTON, Switch F

DE1-SoC BoardB

20 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

FPGA BUTTON, Switch F

DE1-SoC BoardB

20 30Thursday, November 20, 2014

RN36 12012345

678

KEY2

TACT SW

4 3

21

RN38 10K12345

678

SW8

SLIDE SW

123

4

5

BUTTON1

6x6 SW

DNI

4 3

21

SW3

SLIDE SW

123

4

5

SW0

SLIDE SW

123

4

5

SW7

SLIDE SW

123

4

5

KEY1

TACT SW

4 3

21

C141

1u

U42

74HC245

A12 A23 A34 A45 A56 A67 A78 A89

OE19

DIR1

B118B217B316B415B514B613B712B811

VCC20

GND10

C139

1u

BUTTON0

6x6 SW

DNI

4 3

21

SW6

SLIDE SW

123

4

5

BUTTON3

6x6 SW DNI

4 3

21

KEY0

TACT SW

4 3

21

SW9

SLIDE SW

123

4

5

SW5

SLIDE SW

123

4

5

SW2

SLIDE SW

123

4

5

KEY3

TACT SW

4 3

21

C413

0.1u

RN39 100K1234 5

678

RN34 12012345

678

R274 120R276 120

BUTTON2

6x6 SW

DNI

4 3

21

C142

1u

SW4

SLIDE SW

123

4

5

C140

1u

SW1

SLIDE SW

123

4

5

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IRM

IR Emitter tuen on voltage = 1.7V

ADC_IN0ADC_IN2ADC_IN4ADC_IN6

ADC_IN1ADC_IN3ADC_IN5ADC_IN7

KBCLK

KBDAT

MSDAT

MSCLK

ADC_IN0

ADC_IN1

ADC_IN2

ADC_IN3

ADC_IN4

ADC_IN5

ADC_IN6

ADC_IN7

DC_BIAS

ADC_VREF

DC_BIAS

ADC_REFCOMP

Analog_In4ADC_IN4

Analog_In1ADC_IN1

Analog_In2ADC_IN2

Analog_In3ADC_IN3

Analog_In5ADC_IN5

Analog_In6ADC_IN6

ADC_IN7 Analog_In7

Analog_In0ADC_IN0

Analog_In0

Analog_In1

Analog_In2

Analog_In3

Analog_In4

Analog_In5

Analog_In6

Analog_In7

VCC5

VCC5

VCC5 VCC5 VCC5VCC5

VCC3P3 VCC3P3VCC3P3VCC3P3

VCC3P3

VCC3P3

VCC3P3

VCC5

VCC5

VCC3P3VCC5_ADCVCC5_ADC

PS2_DAT 7PS2_CLK 7PS2_DAT2 7PS2_CLK2 7

IRDA_RXD4

IRDA_TXD 4

ADC_SCLK3

ADC_DOUT3

ADC_DIN3

ADC_CONVST3

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

ADC, PS2, IR Tx, IR Rx F

DE1-SoC BoardB

21 30Friday, November 21, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

ADC, PS2, IR Tx, IR Rx F

DE1-SoC BoardB

21 30Friday, November 21, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

ADC, PS2, IR Tx, IR Rx F

DE1-SoC BoardB

21 30Friday, November 21, 2014

R36 120

C4301n

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

VREF

REFCOMP

SDI

SCK

SDO

CONV

DVD

D

OVD

D

AVD

D1

AVD

D1

U24

LTC2308CUF

22

23

24

1

2

3

4

5

6

25 9 10 11 20 18

7

8

15

16

17

14

12131921

R51

2K

R4570

C4291n

D29

BAT54S

1

23

R67 120

R454 49.9

C4361nDNI

C143

47u6.3V

R53

2K

R452 49.9

C4351nDNI

C4241n

C4311n

R450 49.9

R456 0DNI

C4321u

C4261n

R19310K

C39510u

R194 47

R448 49.9

D32

BAT54S

1

23

L27 30ohm, 3AR447 0

Q2HE8050G

R52 120

R1694.99K

D2

BAT54S

1 23

C3940.1u

J15

2x5 Box Header

1 23 45 67 89 10

D92

BAT54S

1

23

D3

BAT54S

1 23

C4341nDNI

C1042.2u

C40110u

C4331nDNI

C4281n

D35

BAT54S

1

23

D87

BAT54S

1

23

R74 120

R455 49.9

D44

BAT54S

1 23

C18 0.1u

R192 560

R453 49.9

R191

4.99

R66

2K

D95

BAT54S

1

23

D43

BAT54S

1 23

R451 49.9

R68

2K

C4020.1u

C4271n

R449 49.9

D38

BAT54S

1

23

C4251n

C36

0.1u

IRM

U35

IRM_V538_TR1

VCC2

GND3

OUT1

CHASSIS4 LED1

IR_Emitter_LED

12

D96

BAT54S

1

23

C4060.1u

VCC5_ADC

C4000.1u

35

TOP

8 6

2 1

J12

PS2

356

9 10 1121

8

R190

4.99

C40710u

R1684.99K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USBUP_DM

USB_CPEN

USBUP_DP

HPS_USB_DATA0HPS_USB_DATA1HPS_USB_DATA2HPS_USB_DATA3HPS_USB_DATA4HPS_USB_DATA5HPS_USB_DATA6HPS_USB_DATA7

USB_RBIAS

USB_VBUS

USB_ID

USB_EXTVBUS

HPS_USB_RESET

USB_EXTVBUS

USBPHY_CLK_24

USBHUB_CLK_24

USBUP_DPUSBUP_DM

USBDN1_DMUSBDN1_DP

USBDN2_DMUSBDN2_DP

USBDN1_DPUSBDN1_DM

USBDN2_DPUSBDN2_DM

USB_VDD

USB_VDD

USB_VDDA

USB_VDDA VCC5

VCC3P3

VCC3P3_USB

VCC3P3_USB

VCC3P3_USB

VCC5 USB_VCC5

VCC3P3_USB

VCC3P3_USB

VCC3P3_USB

VCC3P3_USB

USB_VCC5

USB_VCC5

VCC3P3_USB

VCC3P3_USB

VCC3P3_USB

VCC3P3

HPS_USB_RESET5

HPS_USB_STP 5

HPS_USB_CLKOUT 5HPS_USB_NXT 5HPS_USB_DIR 5

HPS_USB_DATA[7..0] 5

USB3300_MR_N 26

USBPHY_CLK_24 6

USBHUB_CLK_24 6 Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

2-port USB Host F

DE1-SoC BoardB

22 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

2-port USB Host F

DE1-SoC BoardB

22 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

2-port USB Host F

DE1-SoC BoardB

22 30Thursday, November 20, 2014

C644.7u

U15

USB3300

GND1

GND2

CPEN3

VBUS4

ID5

VDD

3P3

6

DP7DM8

RESET9

EXTVBUS10

NXT11

DIR12

STP13

CLKOUT14

VDD

1P8

15

VDD

3P3

16

DATA717 DATA618 DATA519 DATA420 DATA321 DATA222 DATA123 DATA024 VD

D3P

325

VDD

1P8

26

XO27

XI28

VDD

A1P8

29

VDD

3P3

30

REG_EN31

RBIAS32

GND_FLAG33

R29 10K

C24.7u

U2

USB2512B-AEZG

USBUP_DM30 USBUP_DP31

VBUS_DET27

USBDN1_DP2

USBDN1_DM1

OCS_N113

USBDN2_DP4

USBDN2_DM3

OCS_N217

PRTPWR216

PRTPWR112

SDA/SMBDATA/NON_REM122 SCL/SMBCLK/CFG_SEL024

HS_IND/CFG_SEL125

SUSP_IND/LOCAL_PWR/NON_REM028 RESET26 RBIAS35 TEST11

XTALIN/CLKIN33

XTALOUT32

VSS_

EP37

VDD

3315

VDD

3323

VDD

3336

VDD

A33

5

VDD

A33

10

VDD

A33

29

NC16

NC27

NC38

NC49

NC518

NC619

NC720

NC821

CRFILT14

PLLFILT34

R90820

C194

0.1u

R43 0

R10112K

C193

0.1u

C149

0.1u

C34

1u

Q6HE8050G

C172

0.1u

R64

100K

R46 100K

C63

0.1u

VBUS

D-

D+

GND

J8

USB A-TYPE

1234

56

C151

0.1u

C156

0.1u

C174.7u

R284 560

U9

TPS2553DRVR

IN6

GND5

EN4

FAULT_n3

ILIM2

OUT1

EP_GND7

R49 100K

R7210KDNI

C148

1u

L11 60ohm 3A

C155

0.1u

C42

2.2u

L2 BEAD

R73 0

C40

4.7u

C170

0.1u

C150

0.1u

R31 12KR47 100K

C147

0.1u

R48 0

C65

0.1u

R283

4.99K

C62

4.7u

C178

0.1u

VBUS

D-

D+

GND

J7

USB A-TYPE

1234

56

C146

0.1u

C594.7u

R45 100K

C49

0.1u

L1 BEAD

R6320K

R30 10K

C171

0.1u

R30

R62 22

R203 100KDNI

R44 100K

C41

2.2u

R40

TP1DNI

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PHY Address is 00001

HPS_ENET_RESET_N

LED2_DUAL_1

LED2_DUAL_2

HPS_ENET_INT_NHPS_ENET_MDCHPS_ENET_MDIO

CLK125_NDO_LED_MODE

HPS_ENET_GTX_CLK

HPS_ENET_TX_EN

HPS_ENET_TX_DATA0HPS_ENET_TX_DATA1HPS_ENET_TX_DATA2HPS_ENET_TX_DATA3

HPS_ENET_RX_CLK

HPS_ENET_RX_DV

HPS_ENET_RX_DATA0HPS_ENET_RX_DATA1HPS_ENET_RX_DATA2HPS_ENET_RX_DATA3

CLK125_NDO_LED_MODEHPS_ENET_INT_NHPS_ENET_RESET_N

HPS_ENET_MDC

HPS_ENET_MDIO

LED2_DUAL_1

LED2_DUAL_2

HPS_ENET_RX_CLK

MDI_HPS_P0MDI_HPS_N0

MDI_HPS_P1MDI_HPS_N1

MDI_HPS_P2MDI_HPS_N2

MDI_HPS_P3MDI_HPS_N3

LED2_DUAL_1

LED2_DUAL_2

MDI_HPS_P0

MDI_HPS_N0

MDI_HPS_P1

MDI_HPS_N1

MDI_HPS_P2

MDI_HPS_N2

MDI_HPS_P3

MDI_HPS_N3

HPS_ENET_RX_DV

HPS_ENET_GTX_CLK

HPS_ENET_RX_DATA0

HPS_ENET_RX_DATA1

HPS_ENET_RX_DATA2

HPS_ENET_RX_DATA3

ENET_CLK_25

ENET_PLL

VCC1P2VCC1P2 ENET_PLL

ENET_VCCA

ENET_VCCA

VCC1P2 ENET_DVDDL

VCC3P3 ENET_AVDD

ENET_DVDDL

VCC3P3

VCC3P3

VCC3P3

ENET_AVDD

VCC3P3

VCC3P3 ENET_DVDDH

ENET_DVDDH

ENET_DVDDH

HPS_ENET_GTX_CLK 5

HPS_ENET_RX_CLK 5

HPS_ENET_TX_EN 5HPS_ENET_MDC 5HPS_ENET_RESET_N 5,26

HPS_ENET_MDIO 5

HPS_ENET_TX_DATA[3..0] 5

HPS_ENET_RX_DATA[3..0] 5

HPS_ENET_RX_DV 5HPS_ENET_INT_N 5

ENET_CLK_25 6

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

1 Gigabit Ethernet F

DE1-SoC BoardB

23 30Thursday, March 09, 2017

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

1 Gigabit Ethernet F

DE1-SoC BoardB

23 30Thursday, March 09, 2017

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

1 Gigabit Ethernet F

DE1-SoC BoardB

23 30Thursday, March 09, 2017

C158 10n

DNI

C1620.22u

C159 10n

DNI

C16310u

C19110u

C1801u

R86 4.7K

U8

KSZ9021RN

AVD

DH

1

TXRXP_A2

TXRXM_A3

AVD

DL

4

TXRXP_B5

TXRXM_B6

TXRXP_C7

TXRXM_C8

AVD

DL

9

TXRXP_D10

TXRXM_D11

AVD

DH

12

VSS_

PS13

DVD

DL

14

LED2/PHYAD115

DVD

DH

16

LED1/PHYAD017

DVD

DL

18

TXD019

TXD120

TXD221

TXD322

DVD

DL

23

GTX_CLK24

TX_EN25

DVD

DL

26

RXD3/MODE327 RXD2/MODE228

VSS

29

DVD

DL

30

RXD1/MODE131 RXD0/MODE032

RX_DV/CLK125_EN33

DVD

DH

34

RX_CLK/PHYAD235

MDC36

MDIO37

INT_N38

DVD

DL

39

DVD

DH

40

CLK125_NDO/LED_MODE41

RESET_N42

LDO

_O43

AVD

DL_

PLL

44

XO45

XI46

AVD

DH

47

ISET48

PAD

DLE

49 R211 49.9DNI

R26 4.7K DNI

R227 4.7K DNI

R208 49.9DNI

R27 4.7K

R207 49.9DNI

R200 4.7K DNI

C1 0.01u

R223 4.7K DNI

L22 BEAD

R217 4.7KDNI

R88 4.7K

J10

8207S-810X4372

GND11

GND210

MD(1)+4

MD(1)-5

MD(3)+8

MD(3)-9

LEDG+11

LEDG-12

LEDY+13

LEDY-14

SHIELD_216

MD(0)+2

MD(0)-3

MD(2)+6

MD(2)-7

SHIELD_115

R82 4.7K

C581u

L20 60ohm 3A

R204 49.9DNI

R201 1KDNI

R42 4.7K

L4 BEAD

L21 60ohm 3A

R70 4.7K

C300.22u

C2910u

C160 10n

DNI

C161 10n

DNI

R212 4.7KDNI

C3110u C174

0.22u

C320.22u

C1751u

C1901u

R89 4.99K

R202 4.7KDNI

R216 4.7KDNI

R209 49.9DNI

R59 4.7K

R206 49.9DNI

R196 220

R222 4.7K DNI

R83 4.7K

R195 220

R28 1K

R19 10

C1890.22u

R84 4.7K

C18810u

R41 4.7K

R205 49.9DNI

R213 4.7KDNI

L7 60ohm 3A

R71 1K

R58 4.7K

C481u

R210 49.9DNI

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

bus-powered & internal OSC FT232_DP

FT232_DM

USB_UART_VBUS

HPS_RESET_UART_N

HPS_SD_DATA0HPS_SD_DATA1HPS_SD_DATA2HPS_SD_DATA3

HPS_SD_CMD

HPS_SD_DATA1

HPS_SD_DATA2HPS_SD_DATA3

HPS_SD_DATA0

HPS_SD_CMD

HPS_SD_CLK

SD_CD

SD_CD

FT232_DPFT232_DM

VCC3P3_UART

USB_UART_VBUS

VCC3P3_UART

VCC3P3_UART

USB_UART_VBUS

USB_UART_VBUS

VCC3P3_SD

VCC3P3_SD

VCC3P3_SD

VCC3P3

USB_UART_VBUS

VCC3P3_UART

HPS_UART_RX 5HPS_UART_TX 5

HPS_CONV_USB_N 5

HPS_RESET_UART_N 26

HPS_SD_CMD 5HPS_SD_CLK 5

HPS_SD_DATA3 5

HPS_SD_DATA2 5HPS_SD_DATA1 5HPS_SD_DATA0 5

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

UART to USB, SD CARD F

DE1-SoC BoardB

24 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

UART to USB, SD CARD F

DE1-SoC BoardB

24 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

UART to USB, SD CARD F

DE1-SoC BoardB

24 30Thursday, November 20, 2014

C4

0.01u

R21510KDNI

R65 0

U38

ESD5V3U2UDNI

K11

K22

A3

TPD2E001DRLR

U1

VCC1

NC2

IO13

GND4

IO25

U36

ESD5V3U2UDNI

K11

K22

A3

L19 30ohm, 3A

C43

0.1u

R5 1M

J4

Mini-USB-B

VBUS1 D-2 D+3 ID4 GND5

SHIE

LD1

6

SHIE

LD2

7

D102

SD107WS-TP

21

R34 0

123

11

45678

109

12

J11

Mic

ro S

D C

ard

Sock

etDAT3CMDVCCCLKVSSDAT0DAT1

DAT2

CD

VSS

VSS

CD2

TXD LEDB

R198 10K

R214 1KDNI

C144

4.7u

R308499

DNI

RN30

10K

1234 5

678

R32 4.7K

C168

0.1u

R218 330

C169

0.1u

C3

0.1u

R293 0DNI

R19910KDNI

R35 10K

Q4MMBT3904DNI

C1450.1u10VDNI

R50 0 DNI

R444 10K

C444.7u

C5 0.1u

C35 0.1u

R219 330

G

S D

Q3PMOS

20V4ADNI

2

1

3

R197100KDNI

RXD LEDB

C154

0.1u

R33 10K

L3 BEAD

U7

FT232R

VCC19VCCIO1

GN

D4

RESET18

3V3OUT16

USBDP14

USBDM15

TXD30

RXD2

CTS#8 RTS#

32

DSR#6 DTR#

31

DCD#7

RI#3

CBUS022

NC15

AGN

D24

NC212

NC313

NC525

NC629

NC423

OSCI27

OSCO28

GN

D17

GN

D20

TEST26

CBUS121

CBUS311 CBUS210

CBUS49

EP_G

ND

33U37

ESD5V3U2UDNI

K11

K22

A3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Digital Accelerometer

Tie CS_n to high to I2C mode only

Default : I2C Address 0xA6/0xA7

LTC 2x7 Connector

HPS_I2C1_SDAT

HPS_GSENSOR_INT

HPS_I2C1_SCLK

SCK_SCL_R

MISO

CSn

MOSI_SDA

HPS_I2C2_SDAT_R

HPS_I2C2_SCLK_R

HPS_LTC_GPIO_R

SCK_SCLSCK_SCL_R

HPS_I2C2_SDAT_RHPS_I2C2_SCLK_R

HPS_LTC_GPIO_R

CSnMISOMOSI_SDA

HPS_LTC_GPIO

HPS_I2C2_SDATHPS_I2C2_SCLK

CSn

HPS_SPIM_MISOMISO

HPS_SPIM_SS

HPS_LTC_GPIO

HPS_SPIM_CLK

HPS_I2C2_SCLK

MOSI_SDA

SCK_SCL

HPS_SPIM_MOSI

HPS_I2C2_SDAT

CODEC_SEL

VCC_VS

VCC3P3

VCC3P3

VCC_Gsensor

VCC_Gsensor

VCC_Gsensor

VCC3P3

VCC9 VCC3P3

VCC3P3

VCC3P3

VCC3P3

VCC3P3

VCC3P3

VCC3P3

HPS_I2C1_SDAT 5,26

HPS_GSENSOR_INT 5

HPS_I2C1_SCLK 5,26

HPS_I2C2_SCLK 5

HPS_SPIM_MOSI 5HPS_SPIM_CLK 5HPS_SPIM_SS 5

HPS_I2C2_SDAT 5

HPS_LTC_GPIO 5

HPS_SPIM_MISO 5

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Accelerometer, LTC Connector F

DE1-SoC BoardB

25 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Accelerometer, LTC Connector F

DE1-SoC BoardB

25 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Accelerometer, LTC Connector F

DE1-SoC BoardB

25 30Thursday, November 20, 2014

R1652.2KDNI

R1722.2K

C108

0.1u

D41

BAT54S

1

23

C107

1u

L15 BEAD

D98

BAT54S

1

23

U28

ADXL345

VDD1

GND2

RESERVED3

GND4

GND5

VS6

CS_n7

INT18INT29NC10RESERVED_111SDO_ALT_ADDRESS12SDA_SDI_SDIO13SCL_SCLK14

C111

1u

R259 0

D39

BAT54S

1

23

R261 0

C408

0.1u

R162 0

R166 0DNI

R262 0

R1732.2K

C403

0.1u

R260 0DNI

R16410KDNI

C109

0.1u

R253 0

C411

0.1u

D42

BAT54S

1

23

D100

BAT54S

1

23

COM1 NC1

NO1

NO2

NC2COM2

NO3

NC3COM3

NO4

NC4COM4

IN

ENGND

V+

H:COM=NO:COM=NCL

U41

TS3A5018

8

16

11

14

5

2

3

6

10

13

4

7

9

12

115

J17

2x7 Header

1 23 45 67 89 10

11 1213 14

D40

BAT54S

1

23

R171 0

R263 0

R1612.2K

D97

BAT54S

1

23

C110

4.7u

R174 2.2KDNI

L16 BEAD

R1632.2K

R25210KDNI

R258 0

R167 0

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LOW --> NC to/from COM = ON and NO to/from COM = OFFHIGH --> NC to/from COM = OFF and NO to/from COM = ON

I2C Multiplexer

HPS User Button

HPS User LED

HPS Cold Reset

HPS Warm Reset

VCC3P3VCC3P3

VCC3P3VCC3P3

VCC3P3

VCC3P3 VCC3P3

USB3300_MR_N 22

HPS_ENET_RESET_N5,23

HPS_RESET_UART_N24

HPS_LED 5

HPS_KEY5

I2C_SDAT17,18

I2C_SCLK17,18

FPGA_I2C_SCLK5

FPGA_I2C_SDAT5

HPS_I2C1_SCLK 5,25

HPS_I2C1_SDAT 5,25

HPS_I2C_CONTROL 5

HPS_WARM_RST_N5,10,11

HPS_RESET_N5,10

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

I2C Multiplexer, HPS BUTTON, HPS LED F

DE1-SoC BoardB

26 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

I2C Multiplexer, HPS BUTTON, HPS LED F

DE1-SoC BoardB

26 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

I2C Multiplexer, HPS BUTTON, HPS LED F

DE1-SoC BoardB

26 30Thursday, November 20, 2014

C409 0.1u

R2282.2K

KEY7

HPS_WARM_RST

4 3

21

U10

TS5A23157

IN11

NO12

GND3

NO24

IN25

COM26

NC27

V+8

NC19

COM110

U33

ADM6711SAKSZ

GND1

RST_n2

MR_n3

VCC4

KEY8

HPS_Button

4 3

21

LEDG7 LEDG2 1

C410 0.1u

R267 100K

R273 0

C412

1u

R268

4.7K

R272 0

C1810.1u

R266 0

R279

100K

DNIU34

ADM6711SAKSZ

GND1

RST_n2

MR_n3

VCC4

R278100K

KEY5

HPS_RST

4 3

21

R265 0

DNI

R264 100K

R280

100K

DNI

R271 330

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

POWER

Ramp Time = 190 usec1.1V / 8ASwitching Frequency : 617KHz

Place 0.1uF cap close to SVIN pin

Panasonic2R5TPE330MAZB

VCC1P1_INTVCC

VCC1P1_INTVCC

VCC1P1_PGOOD

RP_GATE

RP_GATE

PS_GATE

PS_GATE

VCC12VCC12

VCC12

GND

VCCINT_FPGA

VCC1P1_HPS

VCC1P1_PGOOD28,29

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 1.1V F

DE1-SoC BoardB

27 30Wednesday, May 27, 2015

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 1.1V F

DE1-SoC BoardB

27 30Wednesday, May 27, 2015

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 1.1V F

DE1-SoC BoardB

27 30Wednesday, May 27, 2015

FID3

MTG3GND

R156

162K

FID6 FID9

Q10AO3415

Q8AO3415

MTG4GND

R248 510K

C423

0.1u

R13930K

FID12 FID2

VCC1P1

R158

16.5K

GND4

GND1

FID8

C85

22u25V

R144 30K

C84 0.22u

FID1

LTC3608

U23

PVIN_11

PVIN_22

PVIN_33

PVIN_44

PVIN_55

PVIN_66

PVIN_77

PVIN_848

PVIN_949

PVIN_1050

PVIN_1151

PVIN_1252

PVIN_EPAD53

RUN/SS12

PGOOD16

NC_19

NC_221

NC_324

NC_425

NC_528

SW_18

SW_233

SW_341

SW_442

SW_543

SW_644

SW_745

SW_846

SW_947

SW_EPAD55

BOOST11

FCB19

VFB23

INTVCC_131

INTVCC_232

VON13

ITH

18

ION

22

EXTV

CC

29

SVIN

30

SGN

D_1

10

SGN

D_2

14

SGN

D_3

15

SGN

D_4

20

SGN

D_5

26

SGN

D_6

27

SGN

D_E

PAD

54

VRN

G17

PGN

D_1

34

PGN

D_2

35

PGN

D_3

36

PGN

D_4

37

PGN

D_5

38

PGN

D_6

39

PGN

D_7

40

R29230K

C91 180p

MTG6GND

C391

0.1uDNI

GND3

R157

13.7K

PCB1

10-01306101-F0

MTG5GND

FID7 FID10FID4

Q9AO3415

C390

0.1uDNI

Q7AO3415

FID11

J14 DC_12V123

D14

LEDB

21

GND2

R29130K

R152100K

R245

4.7K

MTG2GND

C374

0.1u

VCC12

C70

22u25V

C81

47u6.3V

L14 1uH744311100

SW11

POWER SW

51

6

24

3

C69

22u25V

MTG1GND

C80

22u25V

R1512.32k

C1034.7u

D24MBR0540T1G

21

C86330u2.5V

C90 3.3n

FID5

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3.3V / 5ASwitching Frequency : 988KHzRamp Time = 1 msec

Ramp Time = 1 msec5V / 5ASwitching Frequency : 988KHz

Panasonic6TPE330MAPVCC1P1_PGOOD

VCC3P3_PGOOD

VCC1P1_PGOOD

VCC3P3VCC3P3_INTVCC

VCC3P3_INTVCCVCC12 VCC3P3_INTVCC

VCC3P3_INTVCC

VCC5VCC5_INTVCC

VCC5_INTVCCVCC12 VCC5_INTVCC

VCC5_INTVCC

VCC1P1_PGOOD 27,29

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 5V, 3.3V F

DE1-SoC BoardB

28 30Wednesday, May 27, 2015

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 5V, 3.3V F

DE1-SoC BoardB

28 30Wednesday, May 27, 2015

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 5V, 3.3V F

DE1-SoC BoardB

28 30Wednesday, May 27, 2015

R30110K

D19 CMDSH-3

C9839p

R150162K

R304162K

C419 3.3n

R15410K

C418 0.1u

C4215p

C7822u

VCC3P3

C41522u

C414 2.2u

C88330u6.3V

C41622u

R14810

R30314K

R302 0DNI

U22

LTC3605EUF#TRPBF

PHMODE2

MODE3

TRACK/SS5

ITH6

CLKIN24

SGN

D22

PGN

D1

10

EP_P

GN

D2

25

PVIN

117

PVIN

218

BOOST20

PGOOD8

SW111

SW212

SW313

SW414

SW515

SW616

FB4

RT1

RUN7

VON9SVIN

19

INTV

CC

21

CLKOUT23

U29

LTC3605EUF#TRPBF

PHMODE2

MODE3

TRACK/SS5

ITH6

CLKIN24

SGN

D22

PGN

D1

10

EP_P

GN

D2

25

PVIN

117

PVIN

218

BOOST20

PGOOD8

SW111

SW212

SW313

SW414

SW515

SW616

FB4

RT1

RUN7

VON9SVIN

19

INTV

CC

21

CLKOUT23

C87 2.2u

C127

100u10V

L12 1uH744311100

C79 0.1u

C101220p

C7422u

C42039p

C422220p

C1005p

C128

47u16V

D101 CMDSH-3

R249100K

R300100K

R1532.21K

R250 0DNI

C89

47u6.3V

L28 1uH744311100

C417 0.1u

C99 3.3n

R3051.37K

R15514K

R29910

VCC5

C83 0.1u

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

9V / 500mA

Ramp TimeTsoft-start = 2 msec

Ramp TimeTsoft-start = 2 msec2.5V /3A 1.5V / 3A

Switching Frequency : 988KHz

Panasonic2R5TPE330MAZB

Panasonic6TPE100MPB

VCC1P1_PGOOD VCC1P1_PGOOD

VCC12 VCC9

VCC1P5_DDR3VCC2P5

INTVCC_3633

VCC12 VCC12

INTVCC_3633 INTVCC_3633

VCC12

INTVCC_3633 INTVCC_3633

INTVCC_3633

VCC1P1_PGOOD 27,28

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 9V, 2.5V, 1.5V F

DE1-SoC BoardB

29 30Wednesday, May 27, 2015

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 9V, 2.5V, 1.5V F

DE1-SoC BoardB

29 30Wednesday, May 27, 2015

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 9V, 2.5V, 1.5V F

DE1-SoC BoardB

29 30Wednesday, May 27, 2015

R184324K

R18919.1K

R18825.5K

VCC2P5

VCC9

C13510p

C13210p

C1291u25V

C1251n

C121

0.1u

R269 10KDNI

C112

47u6.3V

C136

4.7n

C133

4.7n

R18613K C137

10p

R270 10KDNI

R18528.7K

R180 0

C122

1u

C113

47u6.3V

R179 680K

C13410p

U31

LT3085

IN5

IN6

Vcontrol4

SET3

OUT1

OUT2

EP_OUT7

R18380.6K

C117

47u16V

R18213K

C130

22u

C123

0.1u

VCC1P5_DDR3

C131220p

C118

47u16V

C138220p

C116

100u6.3V

C119330u2.5V

R178

220K

U32

LTC3633EUFD#TRPBF

VON125

BOOST120

INTV

cc19

BOOST217

GN

D7

VON212

FB29

TRAC

K/SS

210

ITH211

PGO

OD

28

SW213SW214

PVIN

215

PVIN

216

RUN26

RT

5

MO

DE/

SYN

C4

RUN13

PVIN

121

PVIN

122

SW123

SW124

PGO

OD

11

TRAC

K/SS

127

FB128

PGN

D29

ITH126

PHMODE2

V2P518

R187680

L17 1.5uH744311150

L18 1.5uH744311150

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR3 VTT, VREF

1.2V / 1.1ARamp Time = 0.8msec

1.8V / 1.1ARamp Time = 1.2 msec

VCC1P5_DDR3

DDR3_VTT_HPS DDR3_VREF_HPS

VCC2P5

VCC1P2VCC2P5

VCC3P3

VCC1P8VCC2P5

VCC3P3

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 1.2V, 1.8V, DDR3 VREF, DDR3 VTT F

DE1-SoC BoardB

30 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 1.2V, 1.8V, DDR3 VREF, DDR3 VTT F

DE1-SoC BoardB

30 30Thursday, November 20, 2014

Title

Size Document Number Rev

Date: Sheet of

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.

Power - 1.2V, 1.8V, DDR3 VREF, DDR3 VTT F

DE1-SoC BoardB

30 30Thursday, November 20, 2014

C7122u

DDR3_VREF_HPS

C92

10u

C761u

R81120K

C541u

R149 100K

C771u

C572.2u

C97

22u

VCC1P8

DDR3_VTT_HPS

R159

10K

R306

2K

R160 10K

R307

2K

C102

22u

C754.7n

LT3080

U19

OUT11

OUT22

OUT33

SET4

IN28 IN17

NC6

V_CONTROL5

OUT49

C524.7n

C934.7u

LT3080

U11

OUT11

OUT22

OUT33

SET4

IN28 IN17

NC6

V_CONTROL5

OUT49

C95

0.1u

R140180K

C5622u

C551u

VCC1P2

C722.2u

C94

1n

L13 BEAD

TPS51200

REG1

REFIN1

VLDOIN2

VO3

VOSNS5

VIN10

PGOOD9

GN

D8

EN7

REFOUT6

GN

D_P

AD11

PGN

D4

C96

22u