Total Solution for Designing

Mobile Storage Systems

Yuping Chung

Product Marketing Manager

Arasan Chip SystemsSan Jose, CA 95131

2

Mobile Storage Interfaces

Challenges to Mobile Storage System Designs

Total IP Solution Approach

Agenda

Typical Mobile Storage Devices

Mobile Devices • Smartphone, Tablet, eReader, Digital Camcorder, Camera, etc

Mobile Storages• Embedded Storage

– NAND flash– e MMC Managed NAND storage

• External Storage– Micro SD cards– USB thumb drives, USB HDD– Other removable memory cards

Santa Clara, CAAugust 2011

Typical Mobile Devices Support Major Mobile Storage Interfaces

2000 2004 2005 2006 2007 2008 2009 2010 2011 20121994

SD 1.1High

speedSD 1.0

SD 2.0High

capacity

SD 3.0SDXC / UHS-I

SDIO1.0

SDIO 3.0UHS I

SD 4.0UHS II

200Mhz

SDIO 2.050Mhz

SD

eMMC 4.5HS200

200MB/s

eMMC 4.3Boot-up

MMC 4.1High

Speed

eMMC 4.41DDR

MMC 4.2High

Capacity

UFS 1.0e MMC / UFS

Santa Clara, CAAugust 2011

USB 1.015 Mbps

USB 2.0480 Mbps

USB 3.05 GbpsUSB

ONFi 1.050 MB/s

ONFi 2.0150 MB/s

DDR

ONFi 3.0400MB/s

DDRONFi NAND

Challenges of Designing Mobile Storage Systems

1. Complexity of Integrationa) Physical Layer Analog Interfaceb) Controller Digital Designc) Controller Firmware and OS Software Driversd) OS File Systems & Stacks

Santa Clara, CAAugust 2011

System OS & Software

ONFiNAND Flash DEVICE

SoC’s

MCU Controller

MCU Controller

MCU Controller

MCU Controller

MCU Controller

MCU Controller

MCU Controller

MMC4.3

e-MMC 4.5

USB2.0/3.0 OTG 3.0

SDIO 3.0

SD 4.0

UFS 1.0

SD 3.0Core Processors

(e.g. ARM-15A)

Host IP(in SOC)

MMC4.3

e-MMC 4.5

USB2.0/3.0OTG 3.0

SDIO 3.0

SD 4.0

UFS 1.0

SoC

bus

-AXI

or A

HB

ONFi2.0/3.0HOST

SoC

SD 3.0

ONFiNAND Flash

Device IP(in Memory or I/O Cards)

UH

S II

M-P

HY

USB

PH

Y

ON

FI P

HY

ON

FI P

HY

ON

FI P

HY

ON

FI P

HY

ON

FI P

HY

ON

FI P

HY

UH

S II

M-P

HY

ON

FiPH

YU

SB P

HY

SoCBus

Protocol

SD/SDIO/eMMC

UFS

USB/OTG

ONFi

OS

File

s Sy

stem

and

Sta

cks

Appl

icat

ions

SW D

river

sSD

/SD

IO/e

MM

CU

FSU

SB/O

TGO

NFi

2. Compliant to Multiple Standards- Backward Compatibility

3. Compatibility- Interoperable to potentially hundreds of devices in the open market

6

SD 4.0 / e MMC 4.5Design Considerations

SD 4.0 backward compatible to SD 3.0/2.0/1.0 Faster UHS-II PHY 1.56 Gbps/lane at 52MHz

Additional pins for differential signaling• D0 +/- and D1 +/-

Challenges:• Backward Compatible to

– SD 3.0, SD 2.0, SD 1.0– e MMC 4.4, 4.3, 4.2, 4.1

• New SD UHS-II PHY & Additional SD Differential Signals

• Interoperability

System OS & Software

DEVICE SoC’s

MCU Controller

MCU Controller

MCU Controller

SDIO 3.0

SD 4.0

SD 3.0Core Processors

(e.g. ARM-15A)

Host IP(in SOC)

SDIO 3.0

SD 4.0

SoC

bus

-AXI

or A

HB

HOSTSoC

SD 3.0ONFi

NAND Flash

Device IP(in Memory or I/O Cards)

UH

S II

ON

FI P

HY

ON

FI P

HY

UH

S II

SoCBus

Protocol

SD/SDIO/eMMC

OS

File

s Sy

stem

and

Sta

cks

Appl

icat

ions

SW D

river

sSD

/SD

IO/e

MM

CMCU

Controller

MCU Controller

MMC4.3

e-MMC 4.5

MMC4.3

e-MMC 4.5

ON

FI P

HY

ON

FI P

HY

e MMC 4.5

Published in June 2011 for embedded only

Adds 200Mhz mode for max 200MB/s @ 8-bit data bus

4 KB access Removed secure erase and secure trim Adds Discard & Sanitize command e2•MMC - optional cache command and

two optional internal voltage nodes

Santa Clara, CAAugust 2011

7

Universal Flash Storage is originally part of Mobile Industry Processor Interface (MIPI) Alliance

Performance - 5.8 Gbps max per lane• Gear 1 - 1.25 Gbps• Gear 2 - ~3 Gbps optional

Physical Layer adopts MIPI’s M-PHY

Link Layer adopts MIPI’s UniPro

Protocol layer adopts SCSI, but with own command set

UFS 1.0Design Considerations

Challenges:• New standards adopting

MIPI M-PHY and MIPI UniPro• High speed M-PHY 5.8Gbps• New Compliance and evolving

Interoperability ecosystem

MIPI UniPro

PHY Adapter Layer

Data Link Layer

Network Layer

Transport Layer

Transport Protocol LayerSCSI command set

System Bus Interface

Host Controller Interface

Hos

tR

egis

ter

Dev

ice

Man

agem

ent

Entit

y

MIPI M-PHY

UFS Host Architecture

UFS Devices Santa Clara, CAAugust 2011

8

USB 3.0Design Considerations

DEVICE SoC’s

System OS & Software

MCU Controller

USB2.0/3.0 OTG 3.0

Core Processors

(e.g. ARM-15A)

Host IP(in SOC)

USB2.0/3.0OTG 3.0

SoC

bus

-AXI

or A

HB

HOSTSoC

ONFiNAND Flash

Device IP(in Memory or I/O Cards)

USB

PH

Y

ON

FI P

HY

USB

PH

Y

SoCBus

Protocol

USB/OTG

OS

File

s Sy

stem

and

Sta

cks

Appl

icat

ions

SW D

river

s

USB

/OTG

USB SuperSpeed @ 6Gbps Dual bus architecture

• Concurrently operating SuperSpeed and Full Speed bus

Dual simplex signaling• 2 differential pairs

Four link states for power management• U0 - Operation, U1 - idle/fast exit, U2 - idle/slow

exit, U3 - suspend

Multiple command on a pipe and out of order completion

Santa Clara, CAAugust 2011

Challenges:• Integrating high speed 6Gbps PHY• Update Firmware and Driver for

power management• Backward compatibility• Compliance and Interoperability

9

ONFi 3.0Design Consideration

ONFi 3.0 NAND Specification• Published in March 2011

• Backwards compatible with ONFi 2.0

• Up to 400 MB/s Differential signaling on clock and data lines DDR-2 Transfers

• True and Complement Data Strobes• SDR, NV-DDR and NV-DDR2

Single and Dual data bus discovery Page sizes up to 8K ECC up to 64 bits

• Dynamically configurable ECC width

System OS & Software

ONFiNAND Flash

Core Processors

(e.g. ARM-15A)

Host IP(in SOC)

SoC

bus

-AXI

or A

HB

ONFi2.0/3.0

HOSTSoC

ON

FiPH

Y

SoCBus

Protocol

ONFiOS

File

s Sy

stem

and

Sta

cks

Appl

icat

ions

SW D

river

sO

NFi

Santa Clara, CAAugust 2011

Challenges:• Backward compatibility• Compliance and Interoperability

Total IP Solution SatisfyingTotal Compliance and Compatibility

Superior Support

Leader inIndustry

Standards

SD, SDIO,eMMC, MMC

Architecture Development & Customization

DigitalRTL IP

VerificationIP

Analog PHY IP

SW Stacks & Drivers

ElectricalSystem Level

Models

HWSystem

IntegrationPlatform &Analyzers

USB

AHB, AXI,APB, OCP

UFS

Money

RiskTime

Santa Clara, CAAugust 2011

Total ROI !!

11

Thank You !

Yuping Chung

Product Marketing Manager yuping.chung@arasan.com

Arasan Chip Systems San Jose, CA 95131