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8/8/2019 Thesis 20min
http://slidepdf.com/reader/full/thesis-20min 1/12
Characterization system for Network onChip (NoC) architectures with QoS.
Rayco Hernández Moreno
Master Thesis
ESCUELA TÉCNICA SUPERIOR DE INGENIEROSDE TELECOMUNICACIÓN
8/8/2019 Thesis 20min
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Introduction• Goal: Design and write a Simulator for NoC.
• What's NoC? Network on chip.
2
NoC 5 main characteristic:
* Topology:
* Switching:* Routing:
* Flow Control:
* Buffering:
* Arbitration:
Selecting the appropriate parametersCharacterization
Environment
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3
Steps
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4
Charateristic Description
Topology Implement 2D-Mesh. Supports Torus, Folded-Torus.
Routing Implement X-Y. Support algorithm: deterministic, oblivious y adaptative.
Switching Wormhole.
Flow Control Credits.
Memory allocation Ports and Virtual channels.
QoS With QoS. GT (Guaranteed Traffic).
Without QoS. BE ( Best-Effort ).
Allocation Independent allocators. Weighted round-robin arbiters.
Traffics Modular traffic. Supports many possibilities.
Outputs Behavioral Outputs. Latency, Throughput.
SpecificationDevelop a basic characterization system for NoC.Modular system that allows enlarging the range of characterized NoC.
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5
Simulation
Input parameters
int sim_id;
int BE_VCs;
int GT_VCs;
int dim;
int MAX_VC_flit;
float packet_insertion_rate;
float qos_insertion_rate;
bool numeric_data;
cycle final_cycle;
int flits_per_packet;
int fsel;
int farb;
int fsel_route;
int fselout;
int ftraffic;
Outputslong int num_flits;
long int num_flits_gt;
long int num_flits_be;
double average_latency;
double average_latency_gt;
double average_latency_be;
long int num_pack;
long int num_pack_gt;
long int num_pack_be;
double pack_average_latency;
double pack_average_latency_gt;
double pack_average_latency_be;
long int global_accepted_packets;
long int global_total_packets;
long int global_accepted_packets_be;
long int global_accepted_packets_gt;
float accepted_PIR;
Implementation
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run_sim.h6
C++
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Modularity
7
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8
Events
Batch Allocation
Final Map of events
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Verification
9
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10
QoS IR Dim VC size Packet size BE/GT Weight BE/GT VCs Cycles/WarmUp
50% 3 4 15 1/8 2/2 1M/500k
0
50
100
150
200250
300
0 0,1 0,2 0,3 0,4
L a t e n c y
Accepted Traffic
average_latency average_latency_gt
average_latency_be
Latency
Saturation: More GT
Example
11
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11
0
0,2
0,4
0,6
0,8
1
0 , 0 1
0 , 2
0 , 2 2
0 , 2 4
0 , 2
6
0 , 2
8
0 , 3
0 , 3 3
0 , 3 8
0 , 4 5
0 , 5 5
0 , 7
0 , 9
A
c
c
e
p
ta
n
c
e
R
a
t
i
o
Injection rate
BE GT
0
0,05
0,1
0,15
0,2
0,25
0,3
0,35
0,4
0,45
0 0,2 0,4 0,6 0,8 1
A c c e p t e d T r a f f i c
Injection Rate
Ratio Throughput
Example
12
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Conclusion12
Not a final system. Base System. Usability lacks. But…
Total Physical Source Lines of Code (SLOC) 8,835
Development Effort Estimate, Person-Years (Person-Months)
Embedded COCOMO model
4.10 (49.18)
Característica Booksim PopNet My Work
Interconnections General Interconnection NoC NoC
Goal Behavioral Behavioral / Power Behavioral
Design Space Big NoC(Small) NoC(few implemented)
Modularity Close. Close. Modular System
Core Cycles Events EventsFlexibility. Low Low. Need redesign. Good
Traffic Gen Common Common Supported per Node
QoS support NO. NO. YES.
Allocation Batch Allocation Batch Allocation Independent Allocation
Numbers