CORRESPONDENCE 1189

perimental capacitance-voltage curves of Fig. 2, we can find the charge-storage and the relative capacitor areas for the implanted doses considered. Table I shows these quantities along with the breakdown voltage observed for each implanted boron dose. As can be seen, a significant reduction in area may be achieved with the double-implanted enhanced capacitor, although the maxi- mum size reduction which can be realized may be determined by breakdown considerations. A reduction in capacitor area by a factor of two appears feasible.

REFERENCES [l] K.-U. Stein and H. Friedrich, “A 1-Mi12 single-transistor memory cell

in n silicon-gate technology,” ZEEE J. Solid-State Circuits, vol. SC-8, p. 319, 1973.

[2] H. J. Boll and W. T. Lynch, “Design of a high-performance 1024-b switched capacitor p-channel IGFET memory chip,” ZEEE J.

[3] A. E. Michel, F. F. Fang, and E. S. Pan, “Annealing properties of Sol id-S ta te Circui t s , vol. SC-8, p. 310, 1973.

ion-implanted p-n junctions in silicon,” J . Appl. Phys., vol. 45, p. 2991,1974.

The Probabili ty Distribution of Gains in Avalanche Photodiodes

P. BALABAN, P. E. FLEISCHER, AND H. ZUCKER

Abstract-The probability density function for the gain of a n avalanche photodiode is derived. The derivation is based on a Lagrange expansion of the implicit form of the moment generating function. The results confirm previously published conjectures.

I. INTRODUCTION The avalanche photodiode is a device in which optically gen-

erated primary hole-electron pairs produce additional hole- electron pairs through collision ionization. The collision gener- ated pairs can in turn create additional carriers through the same mechanism. This statistical process is called avalanche multi- plication. The probability density function associated with this process describes the number of secondary pairs thus pro- duced.

An implicit form of the moment generating function for this probability density function starting with one initial (primary) pair was obtained by Personick [l]. Based on this result, Mazo and Salz [2] obtained the explicit expression for this moment generating function and the corresponding probability density function PI,^ (one primary pair producing m secondary pairs). Using a similar approach we obtain P,,, which is the conditional probability of m secondary pairs being created, given n primary pairs (m includes the n primary pairs). The resulting P,,, is the same as that conjectured from special case calculations by Mc- Intyre [3].

11. ANALYSIS

Consider the probabilities P,,, that n initial carriers will result in a total of m pairs. Assuming the present avalanche multipli- cation process to be independent of the past pair generations,l this probability may be obtained through the following recursion relation:

p n , m = Pn-l,kPl,m-k. m-1

(1) k:=n-l

Manuscript received April 14, 1976. The authors are with Bell Laboratories, Holmdel, NJ 07733.

ciated with a given primary do not affect the multiplication process for That is, carriers do not interact, and in particular, secondaries asso-

other secondaries.

This will be recognized as the convolution of two probability density functions

Pn(m) = P,-l(m)*Pl(m) (2)

and therefore we have P,(m) as the n-fold convolution of Pl(m):

P,(m) = Pl(m)*Pl(m)* *Pl(m). (3)

Thus, if Mk(eS) is the moment generating function of Pk(m), 1.e.,

M k ( e s ) = 2 (es)mph,m (4) m = l

then it follows from (3) that

Mn(eS) = [M1(es)ln. ( 5 )

With z = es, an implicit expression for Ml(z) has been derived by Personick [l]:

M l ( 2 ) = z[ ( l - U ) M l ( Z ) + all’(1-k) (6)

where k is the ratio of the hole to electron ionization coefficients, and a is related to k and the mean avalanche gain G by

Recently, Mazo and Salz [2] used the Lagrange expansion to obtain an explicit expression for Ml(z) and We also apply that expansion, but in a more general form, to obtain M,(z) and hence the probabilities P,,,.

The applicable Lagrange theorem [4] states that for

r = b + z 4 ( ! 3 (8 )

(12) The derivatives in (12) are readily evaluated by using the bino- mial expansion

where the binomial coefficients are given by

r -

r --

m (1 - h + ‘1

h - 1’ m (14)

(1 - h 1 + 1) I!

Thus (12) becomes

Using the relation

1190 IEEE TRANSACTIONS ON ELECTRON DEVICES, OCTOBER 1976

(7); (14), and the definition of the moment generating func1,ion (4), the probabilities are

(n + kr)r! r (-) n + k r 1 - k

for r = m - n L 0 and zero otherwise.

McIntyre [3]. These probabilities are identical to the ones obtainec. by

REFERENCES

[l] S . D. Personick, “Statistics of a general class of avalanche detet:tors with applications to optical communication,” Bell Syst. Tech. J . vol.

[2] J. E. Mazo and J. Salz, “On optical communication via direct dctec- 50, Dec. 71, pp. 3075-3095.

tion of light impulses,” Bell Syst. Tech. J. , vol. 55, Mar. 1976, pp. 347-369.

[3] R. J. McIntyre, “The distribution of gains in uniformly multiplying

vol ED-19, June 1972, pp. 703-713. avalanche photodiodes: Theory,” IEEE Trans. Electron Decices,

[4] E. T. Whittaker and G. N. Watson, A Course of Modern Analysis, 4th ed. Cambridge University Press, 1958, pp. 132-133.

(POLY-S i ) SOURCE

(POLY-Si1 DRAIN

EPITAXIAL LAYER

PN JUNCTION ,,k, N - +SUBSTRATE

0x1 DE

POLY-SINGLE BOUNDARY

Fig. 1. Cross section of the p-channel BO-MOS transistor.

The Buried Oxide MOSFET-A New Type of High-Spc;!ed Switching Device

Fig. 2. Cross section of single-poly silicon structure with buried oxides. The thickness of the oxide is 0.82 pm.

OSAMU SHINCHI AND JUNJI SAKURAI

Abstract-A MOSFET of novel structure is proposed, which has a potential advantage on its switching speed. The new structure is similar to that of SOS-MOS which essentially eliminates the junction capacitance of the MOSFET. This structure is fabricsled by simultaneous deposition of single and polycrystalline silicon over silicon with selective oxidations already in place. The fabrication process and dc characteristics of the new devices are described. ‘Che speed-power characteristics are also evaluated by computer 5 im- ulations.

I. INTRODUCTION The switching speed of the MOSFET is usually limited by the

junction capacitance of its drain diffusion. The SOS-MOS technology essentially eliminates the junction capacitance. In fact, switching speeds as fast as subnanoseconds have been re- ported with an experimental SOS-MOS [l]. The major drirw- backs of SOS-MOS are, however, its expensive substrate ;md large junction leakage due to high defect density in the epita::ial silicon.

In this correspondence, we propose a MOSFET of ncvel structure having a thick oxide layer underneath the source ;md drain diffusions which drastically reduces the capacitance be- tween the diffusion and substrate. This reduction of capacitance is essential to high-speed operation of the MOSFET. While 1 his work was being carried out, we were informed that other people were already working along the same lines [2], [3], but to the t est of our knowledge, no functional units have been produced.

11. DISCUSSION A schematic cross section of a buried oxide MOS transistor

(BO-MOS) is shown in Fig. 1. The bottoms of the source and drain diffusions are dielectrically isolated from the substrate by thick oxide layers. The capacitance of the thick oxide is much smaller than that of the p-n junction in the same area. The thin diffused layer on the oxide is composed of polycrystalline silicon. The p-n junctions are formed in the singlecrystalline region just outside the polycrystalline silicon to produce high-quality junctions. An aluminum gate electrode is formed over the thin gate oxide at the top of the channel region, of singlecrystalline silicon, in a standard fashion. In this structure, the p-n junctions are formed only along the side-walls of the diffusions and have extremely small areas as in SOS-MOS.

The process follows the conventional MOS integrated circuit fabrication steps in production, except for the provision for in- corporating the buried oxide by simultaneous deposition of single and polycrystalline silicon. The process begins with 3-0 - cm n-type (100) silicon. A 8000-A thermal oxide is first grown. The oxide is then removed except the areas where the source and drain are to be formed. 2 pm of 3-0 - cm n-type silicon is deposited over the entire surface of the selectively oxidized slices from SiHzClz a t 1050OC in hydrogen. The singlecrystalline silicon is thereby grown everywhere except over the oxide where poly- crystalline silicon is grown. Shallow diffusion is then followed according to the thickness of the polycrystalline silicon. The rest of the processing steps-gate oxidation and metahation-are carried out in a standard fashion to complete the p-channel BO-MOS device. Fig. 2 shows the tapered cross section of the single-poly structure with buried oxides. The thickness of the oxide is 0.82 um. A sham and almost DerDendicular boundarv between the single and pdly-silicon regidn h’as been obtained. The

Manuscript received December 11, 1975; revised May 11, 1976. contour of the top surface is smooth enough to proceed to the

with Texas Instruments, Houston, T X 77001. 0. Shinchi was with Texas Instruments, Dallas, TX 75222. He is llow subsequent processing steps. A typical dc characteristic of the

J. Sakurai was with Texas Instruments, Dallas, TX 75222. He is LOW p-channel BO-MOS transistor is shown in Fig. 3. The channel with Fujitsu Ltd., Kawasaki, Japan 211. length and width are 10 and 650 pm, respectively. The threshold