The Coming-of-Age of Formal Technology · Technical Talk -Formal 12/3/2019 HF, SemIsral Expo, Nov 2019 1 Harry Foster The Coming-of-Age of Formal Technology Chief Scientist, ICVS

Technical Talk - Formal 12/3/2019

HF, SemIsral Expo, Nov 2019 1

Harry Foster

The Coming-of-Age of Formal Technology

Chief Scientist, ICVSMentor, a Siemens Business

November 2019

Restricted © 2019 Mentor, A Siemens Business

How we doing?Number of Required Spins Before Production

0%

10%

20%

30%

40%

50%

1 (FIRST SILICONSUCCESS)

2 3 4 5 6 7 SPINS or MORE

Desi

gn P

roje

cts

Number of Required ASIC Spins Before Production

2012

2014

2016

2018

HF, SEMIsrael, November 20192

Source: Wilson Research Group and Mentor, A Siemens Business, 2018 Functional Verification Study




ASIC: Type of Flaws Contributing to Respin

0%

10%

20%

30%

40%

50%

60%

LOGIC ORFUNCTIONAL

CLOCKING TUNING ANALOGCIRCUIT

CROSSTALK POWERCONSUMPTION

MIXED-SIGNALINTERFACE

YIELD ORRELIABILITY

TIMING – PATH TOO SLOW

FIRMWARE TIMING – PATH TOO FAST

IR DROPS OTHER

Desi

gn P

roje

cts

Type of ASIC Flaws Contributing to Respin

2012

2014

2016

2018



* Multiple answers possible


ASIC: Root Cause of Functional Flaws

0%

10%

20%

30%

40%

50%

60%

70%

80%

DESIGN ERROR CHANGES IN SPECIFICATION INCORRECT or INCOMPLETE

SPECIFICATION

FLAW IN INTERNAL REUSED

BLOCK, CELL, MEGACELL or IP

FLAW IN EXTERNAL IP BLOCK or

TESTBENCH

Desi

gn P

roje

cts

Root Cause of ASIC Functional Flaws

2012

2014

2016

2018







FPGA: Non-trivial Bug Escapes into Production

0%

5%

10%

15%

20%

25%

30%

35%

0 1 2 3 4 5 6 or More

Desi

gn P

roje

cts

Non-trivial FPGA Bug Escapes into Production

2016

2018



84% of FPGA design projects have non-trivial bugs escape into production


FPGA: Type of Flaws Contributing to a Production Issue

0%

10%

20%

30%

40%

50%

60%

LOGIC OR

FUNCTIONAL

CLOCKING CROSSTALK POWER

CONSUMPTION

MIXED-SIGNAL

INTERFACE

TIMING – PATH TOO SLOW

FIRMWARE TIMING – PATH TOO FAST

OTHER

Desi

gn P

roje

cts

Type of FPGA Flaws Contributing to a Production Issue

2012

2014

2016

2018


Source: Wilson Research Group and Mentor, A Siemens Business, 2018 Functional Verification Study * Multiple answers possible




FPGA: Root Cause of Functional Flaws

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

DESIGN ERROR CHANGES IN SPECIFICATION INCORRECT or INCOMPLETE

SPECIFICATION

FLAW IN INTERNAL REUSED

BLOCK, CELL, MEGACELL or IP

FLAW IN EXTERNAL IP BLOCK or

TESTBENCH

Desi

gn P

roje

cts

Root Cause of FPGA Functional Flaws

2012

2014

2016

2018





What’s Driving Verification Complexity?The Emergence of New Layers of Verification


H Foster, Honeywell, Sept 20168

Re

qu

ire

me

nts

Functionality

Clocking

Power

Security & Safety

Performance

Software




What’s Driving Verification Complexity?ASIC Projects Working on Safety Critical Design

46%

54%

59%

41%

0%

10%

20%

30%

40%

50%

60%

70%

Safety Critical Design Not Safety Critical

ASIC

Desi

gn P

roje

cts

2016

2018




What’s Driving Verification Complexity?ASIC Design Projects Implementing Security Features

58%

42%

60%

40%

0%

10%

20%

30%

40%

50%

60%

70%

Security Features No Security Features

ASIC

Desi

gn P

roje

cts

2016

2018






What Makes Verification Difficult?

Single, sequential data streams

— Floating point unit

— Graphics shading unit

— DSP convolution unit

— MPEG decode

— . . .

Multiple, concurrent data streams

— Cross bar

— Bus traffic controller

— DMA controller

— Standard I/F (e.g., PCIe)

— . . .

Channel

Compressed

Audio

Data Link LayerTX

RX

PHY

Sequential data streams1x number of bugs

Concurrent data streams5x number of bugs

Encoder Decoder

-Ted Scardamalia, internal IBM study

H Foster, EE 382M, Verification of Digital Systems, Spring 201811

11 HF, SEMIsrael, November 2019


ASIC: Formal Technology Adoption

0%

5%

10%

15%

20%

25%

30%

35%

40%

Formal property checking Automatic formal verification

Desi

gn P

roje

cts

ASIC: Adoption of Static Techniques

2012

2018






Higher Adoption of Formal for Larger Designs

27%

14%

23% 22%

40%

26%

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

Formal Property Checking Formal Apps

Desi

gn P

roje

cts

< 1M

1M-40M

>40M




FPGA: Formal Technology Adoption

0%

5%

10%

15%

20%

25%

Formal property checking Automatic formal verification

Desi

gn P

roje

cts

FPGA: Adoption of Static Techniques

2012

2014

2016

2018






The Evolution of Formal-Based TechnologyNot just for experts anymore!


EveryoneFormal Experts

LowEffort

FormalPropertyChecking

1990s

FullyAutomatic

Formal

Today

AutomatedApplications

2000s


Questa Formal Solutions & AppsAutomated, Exhaustive Verification For Complex Challenges





Questa Formal-Based Solutions & AppsAutomated, Exhaustive Verification For Each Project Phase



Examples of How Apps Map to Market Segment Needs


Mil-Aero FPGAQuesta Simulation Safety & Security




Formal Apps Targeting New Security Features

Syste

m I

nte

rco

nn

ect 0

Syste

m I

nte

rco

nn

ect 1

DMA

DMA

RAM

RAM RAM

AXI

Bridge

Ethernet

Controller

SDRAM

Controller

SD

RA

M

μC

Encryption

Engine

AX

I B

us

PH

Y

KeyStorage

19 HF, SEMIsrael, November 2019

Is the desired path the only path?


Verification Academy Courseswww.verificationacademy.com

Getting Started with Formal-Based Technology

Formal-Based Technology:

Automatic Formal Solutions

Formal Assertion-Based Verification

Power Aware CDC

SLEC flows – ECO, Clock Gating, Fault

Coming soon: Additional advanced

formal & CDC courses





Questa Formal Apps & Differentiation


Mentor’s Differentiation

Performance (up to 10x faster!)

Easy to adopt apps

Enterprise Verification Platform Integration

Restricted © 2019 Mentor, A Siemens Businesswww.mentor.com

Documents

The Coming-of-Age of Formal Technology · Technical Talk -Formal 12/3/2019 HF, SemIsral Expo, Nov 2019 1 Harry Foster The Coming-of-Age of Formal Technology Chief Scientist, ICVS