The 500 Series Z-Wave Single Chip ADC...APL12678-2 The 500 Series Z-Wave Single Chip ADC 2018-03-06 silabs.com | Building a more connected world. Page 1 of 12 1 ABBREVIATIONS Abbreviation

Application Note

The 500 Series Z-Wave Single Chip ADC

Document No.: APL12678

Version: 2

Description: This application note describes how to use the ADC in the 500 Series Z-Wave Single Chip

Written By: OPP;MVO;BBR

Date: 2018-03-06

Reviewed By: MOS;MVITHANAGE;PNI

Restrictions: None

Approved by:

Date CET Initials Name Justification

2018-03-06 11:33:29 NTJ Niels Thybo Johansen

This document is the property of Silicon Labs. The data contained herein, in whole or in part, may not be duplicated, used or disclosed outside the recipient for any purpose. This restriction does not limit the recipient's right to use information contained in the data if it is obtained from another source without restriction.

APL12678-2 The 500 Series Z-Wave Single Chip ADC 2018-03-06

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REVISION RECORD

Doc. Rev

Date By Pages affected

Brief description of changes

2 20130923 OPP All References fixed, quantities added.

1 20130918 OPP ALL Initial version

3 20180306 BBR All Added Silicon Labs template

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Table of Contents

1 ABBREVIATIONS ................................................................................................................................. 1

2 INTRODUCTION ................................................................................................................................... 1

2.1 Purpose .............................................................................................................................................. 1 2.2 Audience and prerequisites ................................................................................................................ 1 2.3 Application overview ........................................................................................................................... 1

3 HW DESCRIPTION OF THE 500 SERIES Z-WAVE SINGLE CHIP ADC ........................................... 2

4 ADC CONFIGURATIONS ..................................................................................................................... 4

4.1 Setting the resolution .......................................................................................................................... 4 4.1.1 How to calculate the ADC result .............................................................................................. 4

4.2 Voltage references ............................................................................................................................. 5 4.3 Input sources ...................................................................................................................................... 7 4.4 Input current ....................................................................................................................................... 7 4.5 Interrupt modes .................................................................................................................................. 7 4.6 Battery supply monitoring ................................................................................................................... 8

5 HW CONSIDERATIONS ....................................................................................................................... 9

5.1 Input filters .......................................................................................................................................... 9 5.2 Decoupling .......................................................................................................................................... 9 5.3 Routing considerations .....................................................................................................................10

5.3.1 Avoid switching neighbor signals ...........................................................................................10 5.3.2 Avoid inductive pickup ............................................................................................................11

6 REFERENCES ....................................................................................................................................12

Table of Figures

Figure 1, Hybrid charge-redistribution ADC conversion cycle ..................................................................... 2 Figure 2, ADC equivalent circuit during sampling phase ............................................................................. 3 Figure 3, 12 bit conversion cycle and 8 bit conversion cycle ...................................................................... 3 Figure 4, Reference span and input signal dynamic range ......................................................................... 5 Figure 5, Voltage reference sources ........................................................................................................... 6 Figure 7, Interrupt generated when above threshold .................................................................................. 8 Figure 8, Interrupt generated when below threshold ................................................................................... 8 Figure 9, Various input filter possibilities ..................................................................................................... 9 Figure 10, Decoupling capacitor placement and connection to power planes .......................................... 10 Figure 11, How to minimize noise coupling ............................................................................................... 10 Figure 12, ADC trace routing to avoid inductive noise pickup ................................................................... 11 Figure 13, Placement of potentially noisy circuits on multiple application PCB's ...................................... 11

Table of Tables

No table of figures entries found.



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1 ABBREVIATIONS

Abbreviation Explanation

ADC Analog to Digital Converter

API Application Programming Interface

AVDD CO Voltage supply for analog core = battery supply

GND Ground

HW HardWare

ISR Interrupt Service Routine

LSB Least Significant Bit

MSB Most Significant Bit

N.A. Not Applicable

PCB Printed Circuit Board

SFR Special Function Register of a 8051 type micro controller

SMPS Switched Mode Power Supply

SW SoftWare

2 INTRODUCTION

2.1 Purpose

The purpose of this application note is to describe the ADC in the 500 Series Z-Wave Single Chip, how it works and how to use it in an application.

2.2 Audience and prerequisites

The application note is written for developers working with the 500 Series Z-Wave Single Chip. A basic knowledge of the Z-Wave SW API is required.

2.3 Application overview

This document contains the following sections:

HW description of the 500 Series Z-Wave Single Chip ADC: Description of the ADCconfiguration and how it is implemented.

ADC configurations: Describes the different modes and selections that the ADC offers.

HW considerations: Describes which considerations one should take into account priorto designing the HW.




3 HW DESCRIPTION OF THE 500 SERIES Z-WAVE SINGLE CHIP ADC

The Analog to Digital converter build into the 500 Series Z-Wave Single Chip is of the type “hybrid charge-redistribution ADC”.

In short, a charge-redistribution ADC works by charging a binary scaled capacitor array with the voltage to be converted. This phase is called the sampling phase (or sampling period). After having sampled the input voltage, a search is performed starting with the largest capacitor. Each element of the capacitor array is switched to either the high or low reference voltage rail and the total voltage across the capacitor array is compared with a fixed voltage. The outcome of the comparator decides which side to leave the tested capacitor at, before the next capacitor is tested. When all capacitors have been switched, their final position gives the converted LSB result, which is read by a digital controller and presented to the application by calling the appropriated API function.

The ADC being a hybrid charge-redistribution ADC refers to an extra search performed prior to the capacitor search in order to set the internal upper and lower reference voltages. This enhances the resolution of the ADC. The hybrid search takes place right after the sampling period. The charge across the binary scaled capacitors is compared with a voltage generated by a resistor array. A resistor search is performed, and this search sets the upper and lower reference level used during the following capacitor search. Furthermore, the outcome of the resistor search is the MSB bits of the final conversion result. Please note, that the internal upper and lower reference voltages used during the conversion process are derived from the external upper and lower voltage references, and it is the user of the ADC who sets the external voltage references.

The final conversion result is thus a combination of the resistor search performed in order to set the reference levels and the following capacitor search.

The diagram below shows the phases of a conversion cycle:

Start of conversion

Sampling Resistor search Capacitor Search

End of conversion

One conversion cycle

Time

Figure 1, Hybrid charge-redistribution ADC conversion cycle

During the sampling phase of a conversion cycle, the input of the ADC is equivalent to a RC LP-filter:




Rin, 7kOhm

Carray

29pF

Vin VADC

500 Series Z-Wave Single Chip

Figure 2, ADC equivalent circuit during sampling phase

The capacitor array is charged through the input resistance of the ADC plus the voltage source impedance. Because current is drawn in the ADC input during the ADC operation, the voltage source resistance should ideally be 0 Ohm to ensure Vin = VADC. In reality, most voltage sources has a finite output resistance, which means, that Vin > VADC, but the lower the output resistance, the more VADC will be equal to Vin (please refer to the sections 4.3 and 4.4 for details). If the voltage source resistance is < 200 Ohm, the conversion error due to the input current at a supply of 3.3V will be 2 LSB..

A conversion consists as described of 3 phases. A sampling period, a resistor search and a capacitor search. The resistor search is performed among 16 different voltage-steps and the capacitor search is performed on 8 binary scaled capacitors. This means, that the resistor search adds the upper 4 MSB bits of the total result, whereas the capacitor search yield the 8 bit LSB bits, giving a total resolution of 12 bit.

However, if the demands to the conversion resolution are lower than 12 bit, it is possible to skip the resistor search and only perform the capacitor search. This gives an 8 bit result and the conversion time is app. halved:

Start of conversion

Sampling Resistor search Capacitor Search

End of conversion

One 12 bit conversion cycle

Time

Start of conversion

Sampling Capacitor Search

End of conversion

One 8 bit conversion cycle

Time

Figure 3, 12 bit conversion cycle and 8 bit conversion cycle, sampling period = 16uS

The ADC is enabled and started via the SW API. Once the ADC has been started, sampling and conversion is done automatically. When a conversion has completed, the result is transferred to the 8051 SFR and a flag is set. This flag can be set to trigger an interrupt, or the application SW can poll the flag in order to be notified about the generated ADC result.

To reduce overall current consumption the ADC can be powered completely down when not used.




4 ADC CONFIGURATIONS

The following features can be configured through the SW API (please refer to [2] for further details):

Resolution

Voltage references

Input sources

Interrupt generation modes

Battery supply monitoring

The length of the sampling period can be set, but due to the input current problematic described in section 3 and 4.4, there is no value in using longer sampling periods, and it is thus advised to use the shortest possible sampling period.

The following section describes each of the configurable parameters.

4.1 Setting the resolution

The ADC resolution can either be selected to 8 bit or 12 bit. This is set using the ADC SW API functions [2].

8 bit resolution gives the shortest possible conversion time. The conversion time of a 8 bit conversion is app. half the time of a 12 bit conversion.

For both 8 bit and 12 bit conversion, two types of conversion can be performed, either single conversion or continuous conversions.

If using single conversion mode, only one conversion is performed when the ADC is started. The actual conversion starts right after having started the ADC using the SW API. When the conversion has completed the ADC is stopped, but not powered down. ADC power down has to be done using the SW API. Single mode can be used if a voltage has to be converted occasionally.

Continuous conversions means that the ADC starts another conversion automatically when a conversion has ended. This gives the fastest possible sampling sequence obtainable, since the ADC is controlled directly by the digital hardware controller. This mode can be used if a signal has to be monitored continuously. The conversion results can be read either by polling the ADC or by using interrupts. If the result is not read within one sampling period, it will be overwritten by the result of the following conversion. The continuous conversion mode can be an advantage to use if ADC interrupts and ADC thresholds are used, please refer to section 4.5.

Since the ADC is constantly turned on during the continuous conversions mode, this mode is not recommended for use in battery powered applications.

4.1.1 How to calculate the ADC result

If the input voltage is known, it is possible to calculate the ADC conversion result using the following equations depending on the resolution selected:




ADCresult_8bit

Vin

Vupper_reference Vlower_reference

28

Equation 1, 8 bit conversion equation

ADCresult_12bit

Vin


212

Equation 2, 12 bit conversion equation

Vupper_reference and Vlower_reference refer to the voltage references that the user of the ADC can apply externally to the ADC. Please refer to section 4.2.

4.2 Voltage references

As seen in section 4.1.1, the input voltage is converted relative to the references applied to the ADC. This means, that it is important to select the correct voltage references when designing a system with an ADC. The input signal may never be larger than the upper reference voltage or lower than the lower reference voltage, since this will saturate the ADC. But, selecting a too large reference span is of no good either. The reason for this is illustrated below:

Dynamic range of input signal

Upper reference voltage

Lower reference voltage

Reference span

Upper reference voltage

Lower reference voltage

Reference span Dynamic range of input signal

Figure 4, Reference span and input signal dynamic range

If the reference span is large compared to the input dynamic range, the full dynamic range of the ADC is not utilized, and the precision of the converted input signal is lower than it could be. If, however, the reference span is equal to or slightly larger than the dynamic range of the input signal, the full dynamic range of the ADC is utilized, and the precision of the conversion is much larger.

Consider the following example:

Vupper_reference = 3.0V, Vlower_reference = 0.0V, Vinput_range = [0.0V; 1.1V], Vin = 1.055V

Using a 12 bit resolution, the ADC conversion result can be calculated to:

Vin


212

1440




If the input voltage changes to 1.056V, this leads to an ADC conversion result of:

Vin


212

1442

A change of 1mV gives a change in conversion result of 2 LSB.

Now change the upper reference to e.g. Vupper_reference = 1.2V and repeat the same calculations as above:

Vupper_reference = 1.2V, Vlower_reference = 0.0V, Vinput_range = [0.0V; 1.1V], Vin = 1.055V

Vin


212

3601

A 1mV input voltage change gives the following ADC conversion result:

Vin


212

3604

With the lower reference span, a change of 1mV gives a change in conversion result of 3 LSB.

The example shows, that by having selected the reference levels properly according to the input signal range, it is possible to track smaller changes in the input signal. But, the absolute accuracy of the ADC does not scale with the size of the LSB. If the offset error of the ADC is 1 LSB using a 3V span as reference, it will be 2 if the reference span is set to 1.5V since the mechanisms causing the offset error is independent of the size of the reference span.

It is possible to select among 3 different voltage sources for the upper reference and 2 different voltage sources for the lower reference:

P3.6P3.7

P3.4P3.5

Internal Ref.

VDDInternal Ref.

GND Interrupt

Out Comparator

SFR

ADC

Vin

Vupper_ reference

Vlower_reference

500 Series Z-Wave Single Chip

Figure 5, Voltage reference sources

The upper reference can be applied either as:




A voltage applied on the IO pin P3.7

An internal reference voltage which is equal to typically 1.23V

VDD, which is the supply voltage applied to AVDD_CO.

The lower reference can be applied either as:

A voltage applied on the IO pin P3.6

GND, which is the GND of the 500 Series Z-Wave Single Chip.

4.3 Input sources

The ADC has 4 multiplexed inputs, please refer to Figure 5. This means that one input can be sampled at the time.

Each of the IO pins can be used as general digital IO’s if they are not used as ADC inputs.

As the ADC is supplied directly from the power supply pins of the 500 Series Z-Wave Single Chip with no voltage regulators in between, input rail-to-rail performance is possible if the supplies are selected as references. If the supply of the 500 Series Z-Wave Single Chip is 3.0V, the input voltage to the ADC can vary from 0V – 3.0V. If the supply is 2.4V, the input voltage to the ADC can vary from 0V - 2.4V etc.

4.4 Input current

All inputs (VIN, VREF+, VREF-) must be driven by low impedance voltage sources, preferably not exceeding 200Ω, to suppress offsets caused by GPIO input leakage of up to 10µA. Usage of the internal buffer does not decrease the input current.

4.5 Interrupt modes

The digital controller that controls the ADC notifies the application of an “end of conversion” in two ways. The first is that a “Done” flag is set when the conversion result is ready to be read from the SFR registers. This flag can be polled by the application. The “Done” flag is set regardless of the conversion result and can be read using the appropriate API calls.

The second method is to allow the ADC controller to generate an interrupt upon end of conversion. The interrupt will break the application program execution and jump to the ADC ISR.

The time it takes the application before the ADC interrupt is serviced depends on

1. The priority setting of the ADC interrupt (configurable through the SW API)2. Higher priority interrupts released while executing the ADC interrupt.

In the Z-Wave protocol, two types of interrupts have the highest possible interrupt priority by default. Any of these interrupts can “interrupt” the service of an ADC interrupt, and thus prolong the handling of the ADC interrupt.

If the application code is not handling any interrupts, an ADC interrupt will receive the fastest possible handling time according to the normal 8051 interrupt handling scheme.




If the application code is handling an interrupt with higher priority than the ADC, then the ADC ISR will be executed once the code from the higher priority interrupt has finished execution.

Interrupts can be setup to be generated whenever the converted result is larger than or equal to a threshold or lower than or equal to a threshold:

Voltage

Time

Threshold

ADC

interrupt

ADC conversion

results

Figure 6, Interrupt generated when above threshold

Voltage

Time

Threshold

ADC

interrupt

ADC conversion

results

Figure 7, Interrupt generated when below threshold

The advantage of using thresholds is that it eliminates the need of complicated software comparisons. Setup the threshold, start the ADC, and if the conversion result violates the threshold, the ISR will act on the situation. If the conversion result is within the limits, no action is taken.

If the interrupt threshold mode is used in connection with 8 bit continuous conversion mode, the shorter sampling time of the 8 bit sampling insures the fastest possible response time.

4.6 Battery supply monitoring

The ADC can be configured in a way that enables it to perform a measurement of the power supply of the 500 Series Z-Wave Single Chip without the use of external components. Battery monitoring should be used in battery powered applications in order to prevent unexpected behavior of the application due to low battery voltage.

How to use the ADC of the 500 Series Z-Wave Single Chip as a battery monitor is described in detail in [1].




5 HW CONSIDERATIONS

Some considerations have to be made regarding the HW surrounding an ADC in order to obtain the expected precision of the ADC. It is of no use to work with a 12-bit converter with a LSB of e.g 300uV if noise on the input line or power supplies is in the mV range.

All the possible means to avoid excessive noise cannot be described here, since they vary from hardware platform to hardware platform, but this section describes some general precautions to take.

5.1 Input filters

High frequency noise may, regardless of how high the noise frequencies are compared to the sampling period, always interfere with ADC-measurements. Implementing a LP filter in front of the input of the ADC can suppress such interference.

Since the converter during the sampling period looks like a RC LP-filter, adding a series resistor in the input of the converter is equivalent to lowering the 3 dB cut-off frequency of input filter. But, the series resistor may not be too large, since it may influence the precision of the converter (please refer to section 4.4)

A normal passive RC filter is also a solution to consider, or an active filter, depending on the situation.

Using an active filter may be feasible if the dynamic range of the signal is low, since it would be possible to both amplify and filter the input signal using the same circuit.

For all filters, one has to think about the bandwidth of the signal to convert, the bandwidth of the converter and the bandwidth of the filter. The filter should prevent alias products of the signal in corrupting the measurements, filter out noise but not limit the signal nor decrease the precision of the converter. These factors are tradeoffs that need to be solved prior to a hardware design using an ADC.

Rfilter

Rin

Carray

Filter resistor in signal path

Rfilter Rin

CarrayCfilter

RC Filter in signal path

Rin

Carray

Active filter in signal path

500 Series Z-Wave Single Chip 500 Series Z-Wave Single Chip 500 Series Z-Wave Single Chip

Figure 8, Various input filter possibilities, Rin = 7kOhm, Carray = 29pF

When using active filters, matters like inverting / non-inverting amplification, offset errors, power consumption etc. have to be considered when selecting the filter configuration.

5.2 Decoupling

The RF-circuits of the 500 Series Z-Wave Single Chip have a large power-supply noise rejection ratio, since the voltage supplied to the 500 Series Z-Wave Single Chip is regulated internally on the chip for these circuits. This is not the case for the ADC. The ADC is connected directly to the AVDD_CO pin. All noise, ripple and spikes applied to AVDD_CO will thus influence the performance of the ADC directly. Ensuring adequate decoupling close to the AVDD_CO pin when using the 12-bit ADC for high precision is mandatory.




Since the input pins of the ADC shares functionality with the digital IO pins, heavy switching of the IO pins may introduce noise in form of spikes which can lead to noise on the pins used for AD conversions. Ample decoupling on the DVDD_IO and the DVDD pins is therefore recommended for achieving the best possible performance.

As always valid when placing the decoupling capacitors, they should be placed as close as possible to the pin they are decoupling. Preferably on the same side of the PCB and with no via (alternately many via’s) in any of the power connections:

C

GND plane

Po

we

r p

lan

e

C

Via to GND

Via to power

C

Vias to GND

Vias to power

Good solution Bad solution OK solution

500 Series Z-Wave

Single Chip

500 Series Z-Wave

Single Chip

500 Series Z-Wave

Single Chip

Figure 9, Decoupling capacitor placement and connection to power planes

5.3 Routing considerations

Noise is not just a problem on the power supply connections; it can also be introduced to the signal path through inductive pickup and capacitive coupling.

The routing of the signal path from the signal source to the ADC should ideally be short and have no neighbor signals at all. This would both minimize the risk of inductive noise pickup and capacitive coupling.

When connecting the ADC to its signal source, one should take the following precautions:

5.3.1 Avoid switching neighbor signals

The sensitive trace (the PCB trace connecting the ADC with its signal source) should not be routed along a data bus or other signals with rapid and sharp level changes, since this may introduce noise on the sensitive trace due to capacitive coupling. The distance between the sensitive trace and fast switching signals should always be as large as possible:

ADC

IO1

IO2

ADC

IO1

IO2

Good routing practice Non optimal routing practice

500 Series Z-Wave

Single Chip

500 Series Z-Wave

Single Chip

GND plane

Figure 10, How to minimize noise coupling




5.3.2 Avoid inductive pickup

Switch mode power supplies, mains noise suppression coils or other sources of magnetic fields induces noise currents in neighboring wires, traces and circuits. Magnetic fields are impossible to suppress, but the effects of noise pickup can be minimized by placing the noisy circuits relatively as far away from the sensitive trace as possible:

500

Series

Z-Wave

Chip

SMPS

500

Series

Z-Wave

Chip

SMPS

Preferable placement

of SMPS circuit

ADC ADC

Non optimal placement

of SMPS circuit

Figure 11, ADC trace routing to avoid inductive noise pickup

Many applications are divided in two application PCBs assembled over or next to each other. In these cases, circuits radiating magnetic fields should be placed carefully with respect to the 500 Series Z-Wave Single Chip and its connections. Interfering circuits should be placed as far away from both the ADC connections and the RF circuits as possible:

Preferable placement

of noisy circuit

500

Series

Z-Wave

Chip

SMPS

Magnetic field lines

Application

PCB 1

Application

PCB 2

ADC

SMPS

Magnetic field lines

Application

PCB 1

Application

PCB 2

ADC

Non optimal placement

of noisy circuit

500

Series

Z-Wave

Chip

Figure 12, Placement of potentially noisy circuits on multiple application PCB's




6 REFERENCES

[1] Silicon Labs, APL12665, Application Note, Battery powered applications using the 500 Series Z-Wave Single Chip

[2] Silicon Labs, INS12308, Instruction, Z-Wave 500 Series Appl. Prg. Guide v6.50.01 (Beta1)


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DisclaimerSilicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

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The 500 Series Z-Wave Single Chip ADC...APL12678-2 The 500 Series Z-Wave Single Chip ADC 2018-03-06 silabs.com | Building a more connected world. Page 1 of 12 1 ABBREVIATIONS Abbreviation