The 10-ps TDC implemented in an FPGA

Jinhong Wang, Shubin Liu, and Qi AnFELab@USTC

Outline

Implementation of FPGA TDC @ USTCTiming Performance of FPGA TDCTDC Modules @ USTC

The Principle of the FPGA TDC

Coarse Counter (Coarse Time)+Time Interpolation within one clock period (Fine Time)

CLK

Hi tIn

CNT N N+1

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Encoder Unit

FIFO

CLK

Hit

Step[0]

Step[1]

Step[2]

Step[n-1]

Enable

CLK

Latch

Double Coarse Time Counters

Coarse Time

Selector

CLK

Fine Time

Control

Channel ID

Temperature

Read

RdClk

Out Data

Empty

Full

Del

ayD

elay

Del

ayD

elay

Del

ay

Implementation of the Time Interpolation

Time Interpolation with the delay of Carry lines

AdderAdderAdderCi=0

Sum[0]Sum[1]Sum[n-1]

Hit1

Co[0]Co[1]Co[n-2]Co[n-1]

11 00

SwitchMatrix

SLICE(0)XmYn

SLICE(2)XmYn+1

SLICE(1)Xm+1Yn

SLICE(3)Xm+1Yn+1

Interconnect to Neighbors

SLICEM SLICEL

CLB

CIN CIN

COUT COUT

SLICEX65Y100

SLICEX65Y101

SLICEX65Y102

SLICEX65Y103

c) Carry chain of a multibit adder

a) Carry-in in a Slice

b) Rout in a SLICE

FPGA TDC @FELab, USTC ~100 ps Bin Size, 50 ps RMS ; In the year 2005 TNS Vol.53, Issue 1 Part 2 Time interpolation with the dedicated Carry lines

~50 ps Bin Size, < 20 ps RMS ; In the year 2009 TNS Vol.57, Issue 2 Part 1 With Several Compensation Strategies: self-test,

Temperature compensation Up to the present ~ 10 ps Bin Size (Effective) , <10 ps RMS a Modified Wave Union TDC

The 10-ps FPGA TDC

Delay

1

0Hit

1 2 3 k k+1 n-1 n

INV

Hit_In

Delay Delay Delay Delay

Q QS

ET

CL

R

D

Q QS

ET

CL

R

D

Q QS

ET

CL

R

D

Q QS

ET

CL

R

D

Q QS

ET

CL

R

D

Q QS

ET

CL

R

D

Q QS

ET

CL

R

D

CLK

Encoder

Step[1] Step[2] Step[3] Step[k] Step[k+1] Step[n-1] Step[n]

OSC_Inv

MUX

N

Delay

Selector

SEL

INV+Delay+MUX

Wave Union Launcher

CLKT

OSCT OSCT

1t

2t

Nt

CLK

Hit

Osc.

3t

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 240

50

100

150

200

N

TD

C B

in

A BC

Signal Processing of the Raw TDC Time

tNtt

tktt

ttt

ttt

tt

NN

kk

)1(

...

)1(

...

2

0

0

303

202

101

CLKOSC TTt

N times Oscillation

N

1ii00 t

N

1t

4 8 12 16 20 24 28 32324

6

8

10

12

14

16

18

N

RM

S (

ps)

test

80 100 120 140 160 180 2000

200

400

600

800

1000

1200

Time Interval (ps)

Cou

nt

RMS: 8 ps

Timing Performance

RMS vs. NActual implementation falls in to Case 2

1 4 8 12 16 200

10

20

30

40

50

60

70

80

N

RM

S (

ps)

σ =0 psσ =10 psσ =30 ps

Uneven of the tap delay + Uncertainty of the Osc. Period①σosc << σcell ②σosc ≈ σcell

③σosc >> σcell

3

21

Simulation

Bin Size scales as 1/N Similar to dither

1 2 3 4 5 6 7 8 9 10 11 12 13 14140

10

20

30

40

50

N

Eff

ecti

e B

in S

ize

(ps)

BIN

Bin VS. N

Timing Performance

0 500 1000 1500 2000 2500 30000

2000

4000

6000

8000

10000

Effective Fine Bin

Fin

e T

ime

(p

s)

N=1 N=2 N=3 N=4 N=5 N=6N=7 N=8N=9 N=10 N=11

N=12

N=13N=14

FPGA TDC Module

~20 ps RMS, 50 ps Bin NIM, USB, other platforms Xilinx, Altera < 10 ps RMS, 12 ps Bin (planed) PXI, VME, USB Xilinx Virtex 4, Virtex 5…

Altera + XILINX <25 ps RMS, 50 ps Bin

The 25-ps FPGA TDC Module

The 10-ps FPGA TDC Module16 + Chnl. <10 ps RMS , ~10 ps BinVirtex 4 / Virtex 5, …Platform: VME, PXI, USB 2.0Others: Trigger Matching

Thank you ~

TDC Resource Used Available Utilization

10-ps TDC

Slice Register

2081 50560 4.1%

4-input LUT

3280 50560 6.5%

20-ps TDC

Slice Register

684 50560 1.4%

4-input LUT

606 50560 1.2%