Technique for preventing stiction and notching effect on ... papers... · rication technology.1–3 Silicon-on-insulator~SOI! wafers are more frequently used for MEMS because the

Technique for preventing stiction and notching effecton silicon-on-insulator microstructure

J. LiSchool of Electrical & Electronic Engineering, Nanyang Technological University, Nanyang Avenue,Singapore 639798, Republic of Singapore

Q. X. ZhangInstitute of Microelectronics, 10 Science Park Road, Singapore Science Park II, Singapore 117684,Republic of Singapore

A. Q. Liu,a) W. L. Goh, and J. AhnSchool of Electrical & Electronic Engineering, Nanyang Technological University, Nanyang Avenue,Singapore 639798, Republic of Singapore

~Received 16 May 2003; accepted 8 September 2003; published 25 November 2003!

The notching ~undercutting or footing! and stiction problem, which widely exists insilicon-on-insulator microstructure were resolved in this study regardless of the feature sizes, by theintroduction of a spacer oxide thin film. In this modified process, the deep reactive ion etching wasdivided into several steps, where conformal plasma enhanced chemical vapor deposition oxidecoating, and anisotropic oxide etch were employed to prevent the notching effect. Dry chemicalrelease was also realized in this approach but the deep etching did not etch through the device layer.The notching or footing effect was exploited for attaining the lateral etching following thedeployment of the anisotropic plasma etching of the inductively coupled plasma. This method wasproven useful for both the uniform and nonuniform feature designs. To validate the proposed etchingmethod, an optical switch was fabricated. The details and benefits of the proposed process and itsextensions to more valuable and flexible design were all discussed in this article. ©2003 AmericanVacuum Society.@DOI: 10.1116/1.1623509#

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I. INTRODUCTION

Microelectromechanical systems~MEMS! is the integra-tion of mechanical elements, sensors, actuators, and elecics on a silicon substrate through the utilization of microfarication technology.1–3 Silicon-on-insulator~SOI! wafers aremore frequently used for MEMS because the structure heis a significant advantage compared to the limited thicknof the polysilicon of surface micromachining. Besides, Ssubstrates are commercially available and are becominexpensive.4 In SOI based process, the device, handle, athe buried insulating layer are all preformed so that the pcess is relatively simple. The single crystal silicon~SCS!mechanical layer thickness is significantly greater and muniform. On top of that, the reliability is high due to thelastic behavior continuing far up to the high yield stressthe SCS which has very few defects. Therefore, the desigflexible and it gives improved performance for some appcations, such as to provide higher edge capacitance. Mover, it is compatible with complementary–metal–oxidsemiconductor process.5 There are, however, two significanproblems for the SOI microstructure fabrication. One isnotching problem during deep etching of the thick devlayer. The other is the stiction problem caused by therelease process.

Deep reactive ion etching~RIE! through the silicon devicelayer is an essential step in microstructure fabrication. Ho

a!Author to whom correspondence should be addressed; [email protected]

2530 J. Vac. Sci. Technol. B 21 „6…, Nov ÕDec 2003 1071-1023Õ200

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ever, plasma etching the silicon over the insulator layerlong been recognized to result in a silicon notching problat the silicon/insulator interface.6–8 This is because of thecharging on the insulator layer regardless of the geometrthe etched structures or their functionality as shown in Fi1~a! and 1~b!. They are the scanning electron microsco~SEM! micrographs illustrating the notching phenomenfor a SOI device. The poor profile contributed by the notcing may result in resonant frequency variations in the micstructure, leading to degraded performances. As this uncutting is aspect ratio dependent, the profiles andcharacteristics of the final devices may further vary acrthe wafer, affecting the repeatability and reliability, espcially for the thick device wafer.

There are several ways to address this problem, but emethod has limitations. One is to adjust the process pareters dynamically, but this will be time consuming and difcult to control.9 Surface technology systems~STS! have de-veloped a deep plasma-etching machine, which hasdifferent platen frequency sources; 13.56 MHz and 380respectively. By employing low frequency, the ions arelowed to escape after the etching cycle preventing the chaaccumulation. However, this is limited by the hardware itsand it is difficult to detect the end point, especially ftrenches with different aspect ratios. Enhancing heat condtion between helium~He! gas and the processed wafer usiheat conductive paste is only suitable for the cases whwafer bonding is necessary.10 Another method is to preventhe ions scattering at the price of the nonvertical profile.11il:

25303Õ21„6…Õ2530Õ10Õ$19.00 ©2003 American Vacuum Society

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2531 Li et al. : Technique to prevent stiction and notching on SOI 2531

The permanent stiction problem due to the capillaforces that occurs during the rinsing and drying of wetlease is another problem commonly seen in the conventioSOI process.12 This effect has been studied theoretically aexperimentally.13,14 Several modified release approachsuch as the hydrofluoric acid~HF! vapor, liquid HF com-bined with freeze drying, photoresist assisted, or surfmodification had been reported. Unfortunately, these pcesses are not faultless, where some suffer from problsuch as bubbles in the liquid, low yield, less thermal stabiletc. To solve these problems, attention was given to drylease, and hence the development of isotropic silicon etchand dry etching of silicon dioxide. The single crystal reactietching and metallization together with the disadvantagesthe RIE lag may cause different etching depths at both siof a beam.15 The silicon micromachining by single steplasma etching depends strongly on the dosage of the bulayer and the release rate is very low at about 50 nm/mThe black silicon method~BSM! involving multistep one-runincludes both BSM SOI and BSM silicon on insulator osilicon on insulator~SISI! methods. The later approach, BSMSISI, is for solving the issue of high silicon loading problemof the BSM SOI. However, the cost of double SOI wafers fthe BSM SISI process is high. The other disadvantage islow speed involved during wall passivation and oxide etcing, which is 20 and 50 nm/min, respectively.3

In this article, a spacer oxide deposition process wasployed to eliminate the notching effect. Dry release of tmovable structures was also developed. In Sec. II, the pcess and the fabrication results of the spacer oxide coveto prevent the notching effect was described. To verifyeffect, trenches with widths ranging from 0.4 to 200mm onthe 35 mm SOI wafer~device layer is 35mm thick! wereperformed. The dry chemical release process was highlighin Sec. III. Both uniform and nonuniform feature size rleases were described. By employing this modified tenique, an optical switch using 75mm SOI wafer was fabri-cated and the results were all presented in Sec. IV. Tpotential applications of this new process were also dcussed in this section.

II. PROCESS TO ELIMINATE NOTCHING EFFECT

Charging accumulation is the main reason for the noting problem. Its mechanism can be explained explicitlythree phenomena~see Fig. 2!: ~1! electric field effect during

FIG. 1. Notching effect:~a! schematic and~b! SEM micrograph.

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charging transient for which the direction of the impinginions changes;~2! etching reactions of the energetic ions impinging on the bottom surface of the exposed silicon; and~3!the forward scattering effects. On the onset of late

FIG. 3. Modified process flow to eliminate notching effect:~a! first deep RIEetch until the widest trenches to the buried oxide;~b! PECVD oxide depo-sition and anisotropic etch the lateral deposited oxide;~c! deep RIE etch thesecond widest trenches to oxide layer;~d! etch back the deposited oxide othe sidewalls; and~e! repeat the deep etching and remove the deposioxide after process completion.

FIG. 2. Schematic illustrations of:~a! notch on SOI wafer and~b! the mecha-nisms of notch formation.

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TABLE I. Design trench width.

Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2

Trenchwidth~mm!

0.4 0.5 0.6 0.8 1.0 1.5 2.0 2.5 3.0 3.5 4.0 5.0 6.0 7.0 8.0 9.0 10.0 20.0 30.0 40.0 50.0 75.0 100.0

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etching, more and more insulator layers will be exposedthe notching deepens due to the forward scattering of ioMoreover, the oxide surface charges up leading to forwdeflection of ions since more oxide is exposed as etchprogresses.10 Research has shown that the notching effdepends on the aspect ratio, layout, whether the silicon lare electrically connected,9 thickness of the mask layer,16 andthe electron temperature.7 Another significant issue that iunavoidable in the deep RIE process is the RIE lag ofaspect ratio dependent etching. This is a common phenenon in plasma etching of deep structures since the etcrate depends on feature size. The higher the aspect ratioslower the etching rate.17,18 The RIE lag will worsen themicrostructures since over-etching can lead to over-dstructures or the structures cannot be etched to the designdepth if the etching time is insufficient. For SOI wafers, tfeatures may be widened or even destroyed due to the ilator layer under the device silicon. This phenomenon canexplained by the deflection, capturing, and the subseqdepletion of ions.

A spacer oxide thin film technique had been developand the process flow is given in Fig. 3. Plasma enhanchemical vapor deposition~PECVD! silicon dioxide 3.5mmthick was deposited first as the hard mask, which is thenough to protect the device silicon from being etched. Uppatterning the trenches, etching of the device layer wasvided into several steps according to the rate of variouspect ratio trenches. The first etch focused on the fastest eing trenches. As is illustrated in Fig. 3~a!, they were etchedthrough to the buried oxide layer, with the narrow trenchstill not completely etched through. If the etch continuenotching would occur at the bottom of the wide trenches.prevent this problem, PECVD oxide was employed to cothe sidewall of the trenches including their top surfacesthe trench bottoms. To continue with the etch for the ottrenches, anisotropic oxide etching by Applied MateriP5000 Mark II was employed to remove the lateral deposoxide where CHF3 is used to etch the oxide and the resultgiven in Fig. 3~b!. The STS inductively coupled plasm~ICP! deep RIE was used again until the device layer wetched through for the second widest trenches@see Fig. 3~c!#.For the narrowest trenches with the slowest etching rate,oxide conformal coverage, lateral silicon dioxide removand deep RIE etching through were repeated again. Hever, to assure vertical profiles and smooth sidewalls ofbeams, the previous spacer oxide was removed beforenext deposition, as demonstrated in Fig. 3~d!. In this way, thedeposited oxide would not accumulate to a thick layer, whwould induce a step at the interface between the vari

J. Vac. Sci. Technol. B, Vol. 21, No. 6, Nov ÕDec 2003

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etchings. Finally, the spacer oxide was removed by isotroetch @refer to Fig. 3~e!#.

Using the above technique, different aspect ratio trencwithout the notching problem can be realized on a Swafer. This is accomplished by dividing the deep etching inmore steps, and by using the oxide deposition and latoxide removal steps in-between to protect the side wall.order to verify this process, a special mask with trenwidths varying from 0.4 to 200mm as shown in Table I wasdesigned. Etching was carried out on a silicon waferwell as a 35mm SOI wafer, both with and without the modfication, using STS ICP with the same conditions listedTable II.

After 30 min of etch on the silicon wafer, the cross setional views of the various trenches were taken and the Smicrographs are shown in Fig. 4. Obviously, the narrotrenches experienced different etching depths with the sconditions for the same time as evident in Fig. 4~a!. On theother hand, almost the same etching depths were obtainetrenches with widths greater than 20mm @see Figs. 4~b! and4~c!#. The relation between etching rate and trench widthgiven in Fig. 5~a!, which formed the basic data for propetime distribution of the multiple steps etching on the Swafer ~to be discussed in the following paragraphs!. It isclear from Fig. 5~b! that the etching rate depends stronglythe trench widths which fall below 20mm.

The RIE lag effect will cause another problem for strutures on the SOI wafer, due to the underlying insulatorneath the device layer. Because the etching of the nartrenches is still half way when the wide grooves reachburied layer, positive charges will build up at the silicon aoxide layer interface of the completed wide grooves. Tlateral etching that takes place could give rise to footproblem. This will be discussed in detail in Sec. III.

For the silicon wafer, the average etch rate of the 4.0mmwide trench was 1.155mm/min under the conditions listed inTable II. To etch through this trench on a 35mm SOI wafer,the expected etching time is 30 min and 18 s. PresenteFig. 6 are the cross sectional view of continuous etchresults of all trenches on a 35mm SOI wafer. Obviously, the

TABLE II. Silicon etch parameters for the deep RIE process.

Process step

Gas flow~sccm!

Power~W!

Cycle time~s!C4F8 SF6 O2 Coil Platen

Etch 30 120 5 600 0 9.0Passivate 150 0 0 600 14 6.0

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4.0 mm trench was just etched to the buried oxide layHowever, the etching depths of trenches narrower thanmm were less while the trenches with widths ranging fro5.0 to 10mm encountered a serious notching at the interfabetween silicon and insulator layer. With regards to ttrenches wider than 20mm ~see Fig. 7! no prominent notch-ing or other side effects were noted. This was attributedthe strong dependence of the notching effect on the asratio.

The aspect ratio dependent charging is due to the ditionality difference between ions and electrons whenproaching the wafer surface. The positively charged ionsrive nearly normal to the wafer plane because of the effecthe sheath field, whereas the electrons face a decelerafield. The higher energy electrons tend to be deflectedthe lower energy electrons are turned back though boththem start with uniform distribution in all directions at thsheath edge. The published result of the Monte Carlo simlation had verified that electrons arrive at an uncharged wasurface with a near isotropic distribution, but in a high aspratio structure, most of the directional ions could reachbottom of the trenches, while the electrons end up monear the top of the device layer.9

FIG. 4. Trenches differing in widths and depths on the normal silicon wa~a! trenches with widths from 0.4 to 10mm; ~b! trenches with widths from10 to 75mm; and~c! trenches with widths 100 and 200mm.


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According to the etching rates obtained on the silicon wfer, the multiple steps etching process was carried out to etrenches with different widths to prevent the notching effeThe notching problem can be neglected for trenches withan 20mm and narrow trenches that are 0.4–1.0mm are toonarrow for deep etching. The trenches ranging from 2.0 tomm are the main focus in this study and the target iseliminate the notching effect on the 35mm SOI wafer. Thefirst etching was concentrated on the 10mm trench, whoseetching time was expected to be 27 min and 30 s basedthe rate obtained from silicon wafer etching. After this steall of the trenches were etched to different depths. The 1

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FIG. 5. Etch rates vs widths of trenches:~a! trench widths varying from 0.4to 200 mm and ~b! significant dependence between the etching rate atrench width for narow trenches.

FIG. 6. Etched trenches from 0.4 to 20mm on the SOI wafer after 30.3 min.

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mm wide trench was the deepest, at 35mm deep, and wasetched through first. Then, PECVD was employed to coall the exposed surfaces, including the top, bottom, and sof the trenches, by decomposition of tetraethoxysila~TEOS! oxide, followed by anisotropic etch of silicon oxidon the lateral surfaces, both the top and bottom whileoxide on the side wall is left. The sidewalls of the 10mmtrench were covered by PECVD TEOS oxide and the trenbottom was the buried thermal oxide. For the narrowtrenches, the sidewall was covered while the bottom silicwas exposed to be etched. The second deep RIE was caout to etch through the trenches with widths ranging fromto 9.0 mm. The oxide deposition, anisotropic exposed tbottom silicon and the third deep etch was repeated targetrenches with widths of 2.0, 2.5, 3.0, 3.5, and 4.0mm, beforewhich the previous sidewall oxide layer was removedisotropic etching. The final cross sectional views of the s

FIG. 7. Etched trench from 20 to 200mm on the SOI wafer after 30.3 min

FIG. 8. Improved etching results on 35mm SOI wafer:~a! all trenches~from0.4 to 20mm wide! and ~b! bottom of the 5mm wide trench.


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cially designed trenches are presented in Fig. 8~a!. Obvi-ously, trenches that were of less than 2.0mm were not etchedthrough, whereas trenches with widths of 2.0, 2.5, and fr5.0 to 10.0mm, were etched through already, eliminating thnotching problem. However, undercutting still existed at tfoot of the 3.0, 3.5, and 4.0mm trenches. This was the resuof the pronounced etching rate variations, for patterns wcritical dimensions of 2.0mm, 2.5, 3.0, and 3.5mm. How-ever, this phenomenon could be eliminated if more etch stwere employed. Another phenomenon observed wasrounded bottom trenches@Fig. 8~b!# and could be due to tworeasons. The first reason was the overetch during the antropic etching of the deposited oxide for the purpose of eposing the bottom SCS well for the deep RIE etching, whiresulted in a little etching of the buried oxide. The secoreason could be the silicon etching using multiple steps.though the etch selectivity between silicon and oxidegreater than 65 under such conditions, the exposed buoxide would be etched profoundly after long exposure todirectional high-energy plasma. Nonetheless, the loss olittle buried oxide posed no side effects on the process orproperty of the devices since the next process in most cais to release the structures.

A key step for this process is the PECVD oxide coveragDeposition must be conformal over all of the surfaces, escially the sidewall and the bottom. To verify this, cross setion SEM micrographs are necessary. However, the dielecoxide film induces charging of the electrons during scannimaking inspection of the thin oxide layer extremely difficuIn view of this, an extra polycrystalline silicon layer wadeposited on top of the oxide layer. The sample was thdipped in buffered oxide etchant to etch the PECVD Si2

thin film after cutting the cross section, to obtain a hollolayer between the SCS and the deposited polycrystallinecon. Figures 9~a! and 9~b! illustrate the white hollow oxidelayers at the bottom and sidewalls that were previously cered by the polysilicon. It is clear that both the bottom athe sidewalls of the trenches were all well covered by tPECVD oxide. This confirms that the process is reliable.

The above described fabrication approach can now pthe role as a base line for MEMS devices on SOI wafewhich provides more flexibility for microstructure designSeveral different feature sizes of microstructures can besigned and fabricated, eliminating the limitation of only un

FIG. 9. SEM micrographs of the deposited oxide on the trenches:~a! bottomand ~b! sidewall.

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form size for each process. Another benefit derived from tprocess is the very much enhanced profile of the deep mistructure, which is the key requirement for the micro-mirrof the optical switch.

III. DRY RELEASE BY NOTCHING

In this section, a more flexible fabrication method to rlease movable structures on a SOI wafer with no stictproblem is reported. Spacer oxide thin film is utilized and tnotching effect is exploited for dry chemical release, to hresolve problems associated with wet chemical releaseother reported dry gas releases which were previouslycussed in Sec. I. The notching effect or undercutting is eployed for its lateral directional etching. The depth of tnotching depends on many factors such as the over-etctime, the material type, as well as the thickness of the siwalls passivation, and the size of the feature. Other vations are electron temperature, ion energy, and theelectron current at the surface.

The deep RIE makes use of both etch and passivatioattain the deep trenches. The sidewall is to be covered bypolymerized CF2, but this thin polymer-like layer cannoprotect the silicon trench sidewall from etching by the hienergy repelled ions from the exposed silicon dioxide layWhen a trench is over-etched, the depth of the movastructures will be sacrificed and the performance of thevices will be degraded. Since the etch rate selectivitytween SCS and oxide is greater than 65, the oxide canused to protect the silicon sidewall from the impinging potive ions. On the other hand, the release depth can be

FIG. 10. SEM micrographs of the dry released beams:~a! released group ofbeams and~b! released single beam.


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trolled by the coverage depth of the oxide layer even ifrelease time is exceeded. Incidentally, the proposed proallows release of both uniform and nonuniform beamwhich will be discussed in the next section.

A. Uniform beam release

Beams with uniform trenches can be released by emping the notching effect. After patterning the features onSOI wafer, deep RIE was employed to etch the device lato within 1.0–2.0mm from the buried oxide layer. The exposed surfaces were then covered by the PECVD oxideetch the remaining silicon and to release the beams, theeral deposited oxide was removed by anisotropic etchwhile the sidewall oxide remained. Then the deep RIE wused again. This plasma etching step is a critical step ofuniform dry release process. It plays two important roles:etch through the device layer until reaching the buried oxlayer and to release the features via the notching effCompared with other dry releasing methods, the processtolerance here is much more flexible. In conventional detching, over-etching can mean scarification of beam depBut because of the sidewall oxide coverage, the structucan endure long over-etching time since the selectivitytween silicon and silicon oxide is high.

In order to verify this process, 35mm SOI wafers wereused to demonstrate the release. After patterning the sttures, deep RIE was carried out for 25 min to etch ttrenches to about 33mm followed by the thin PECVD oxidelayer deposition. The lateral oxide was etched anisotropic

FIG. 11. SEM micrographs of insufficient and over-release beams;~a! groupof not released beams and~b! group of over-released beams.

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FIG. 12. Notching on various trenches~a! 20 and 10mm wide trenches;~b!9.0 and 8.0mm wide trenches;~c! 7.0and 6.0mm wide trenches; and~d! 5.0,4.0, 3.5, and 3.0mm wide trenches.

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using the Precision 5000 Mark II~ETCH MXP! etcher fromApplied Materials. Overetching is required to assure exsure of the bottom silicon for the vertical etch. Finally, deRIE etching for 12 min was employed again to etch throuthe trenches and also release them. The released strucare shown in Figs. 10~a! and 10~b!. Obviously, the beamswere released well without any sign of stiction or other seffects. The edges at the foot of the wide beams wereserved to be etched. This is because the notching effeccurs at both sides of the trenches. In the event of insufficetching, undercutting will occur only at both sides of tbeam foot, therefore the beams cannot be totally release

FIG. 13. Notch depths for various trenches.


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The depth of the released microstructures can be adjuby combining the deep RIE etching and oxide thin film tecnique. By allowing sufficient etching time for the secondeep RIE etching, the beam height achieved will be equa

FIG. 14. Notch rates for various trenches.

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that of the initial etched depth, whose sidewall is protecby the PECVD TEOS oxide. Therefore, by adjusting the fietching time, suspended microstructures of various decan be obtained.

B. Nonuniform beam release

Notching is strongly related to the aspect ratios ofpatterns~see Fig. 6!. Under the same process conditiostated in Table II, the notching effect was significant ftrenches with aspect ratio~ratio of depth to width! greaterthan 1.75. No apparent undercutting for features with aspratios on the order of 1.5 or less was noted, as the electare able to bombard at the lower part of the etched structand at the bottom surface. The charge buildup and the reing notching effect were precluded. The extreme high aspratio patterns~greater than 20! are too narrow for the etchangas to enter deeply or for the product gas to escape. Therate then dropped significantly and the interface betweenconductive silicon and the insulative thermal oxide wasexposed, since the etching time was not long enough to rethe silicon–oxide interface. The notching effects for the fetures with aspect ratios of between 1.75 and 20~with widthsranging from 20 to 2.5mm on the 35mm SOI wafer! dependstrongly on the pattern. This can be observed amongSEM micrographs of Fig. 12, where various trench dimesions are illustrated. The notching was so small in Fig. 12~a!that it could be neglected for the 20mm wide trench. How-ever, as the aspect ratio increased the notching depth deas the distance of the lateral notching increased alsonotching depth of 4.335mm for the trench with aspect ratiof 3.50 is observed in Fig. 12~a!, and a depth of 4.230mmfor the aspect ratio of 3.89 in Fig. 12~b!. The depth reducedto 2.140mm when the aspect ratio increased to 7.00@see Fig.12~d!#. The notch depth dependence on the trench widthplotted in Fig. 13. We can see that the notching effect caneasily controlled by tailoring the aspect ratios of the etchfeatures.

Different etch durations are necessary for different trendimensions in order to etch through the 35mm SOI devicelayer. Without different etch durations, etch results woulddifferent. Trenches with different aspect ratios undersame etching conditions presented different lateral underting as shown in Fig. 6. The lateral etching rates~ratio ofnotching depth over notching time! for the trenches withwidths ranging from 4.0 to 10.0mm are shown in Fig. 14

TABLE III. Notching depths and rates for various trenches.

Trench~mm!

Etch rate~mm/min!

Time for 35mm ~min!

Overetch time~min!

Notch depth~mm!

Notch rate~mm/min!

4.0 1.155 30.300 0 0 —5.0 1.222 28.651 1.466 2.140 1.4606.0 1.242 28.178 1.939 3.035 1.5657.0 1.256 27.856 2.261 3.675 1.6258.0 1.277 27.408 2.709 3.980 1.4699.0 1.283 27.277 2.840 4.230 1.48910.0 1.296 26.996 3.121 4.335 1.389


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which is uniform in this range. This uniform notching rateattributed to the consistent charge distribution in this aspratio range. Table III lists the notching depth, the oveetching time, and the notching rate of this series of trenchThe amount of over-etching time is thus another importcontributing factor for notching. The etching results wigreater over-etching times are depicted in Fig. 15 for a setrenches with widths of 2.5, 3.0, 3.5, to 4.0mm under thesame etching conditions, except for an additional 5 minetching so as to compare to the previous etching resultshown in Fig. 12. As seen in Fig. 15, the 2.5mm wide trenchwas etched through with the extra 5.0 min of deep RIE eting, while the etching depth would be less than 35mm @seeFig. 12~d!# without the extra 5 min. Then again, becausethe additional 5 min etching, the wider three trenches of F15 suffered from notching. Therefore, structures with diffeent trench widths will result in different notching depths ifsingle etching approach was employed. However, by usthe proposed multistep plasma etching process, the nonform features can be etched and dry released to an edepth. This improved SOI wafer fabrication technique alloflexibility in the design of MEMS devices with possiblvariation in microstructure dimensions as well as maintaing the properties of the MEMS devices.

TABLE IV. Dimensions of the comb drive actuator.

Structures Component Dimension~mm!

Comb finger Width 2.0

Gap of overlap 2.5Gap of nonoverlap 7.0

Folded suspension beam Length 600.0Width 3.0

Trench width beside the beam 33.0

FIG. 15. Notches on 2.5, 3.0, 3.5, and 4.0mm trenches after 35 min ofetching.


FIG. 16. SEM micrographs of the dryreleased actuator:~a! comb fingers and~b! suspension beam.

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For nonuniform design with wide and narrow trencheoxide spacer coverage was employed to avoid excesnotching. The process could be described as follows. Fall the trenches were patterned on the top mask. Thentrenches were etched but not to the silicon and oxide inface, even in the case of the widest trenches. All the pattwere then conformally covered by PECVD TEOS, followby plasma etching, the lateral deposited PECVD oxideorder to continue on the vertical etching as well as to reathe lateral release. The last step was crucial as it plaseveral key roles. It etched through the widest trenchesdeepened the narrow trenches. With the progress of etchreleasing the beams with wide trenches started due tonotching effect while the narrow trenches became deeWhen the narrow trenches were etched through to the inface of the buried oxide, the beams with wide trenches wohave suffered some degree of notching or lateral etchHence, the beams with wide trenches were released towhile notching began for the beams with narrow trenchContinuing the undercutting of the narrow beams, thepelled positive ions could not react with the spacer oxidethe beams so that the depth of the beams with wide trenwould not etch further. The deep RIE etching was stoppwhen the narrow beams were completely released. Thusdeep RIE anisotropic etching and dry gas release that muse of the notching effect were both realized.

IV. APPLICATIONS AND DISCUSSION

The proposed method of multistep deep RIE etching cobined with the PECVD TEOS spacer oxide protection areleases the microstructures through the use of the notceffect. The spacer oxide protects further lateral etchingso the complete process can be used to fabricate high aratio suspended structures for many MEMS devices appltions, such as the optical switch, variable optical attenuaand rf switch.

In order to validate our proposed scheme, optical switcto be driven by comb drive actuators, with dimensionsfined in Table IV, were fabricated on a 75mm SOI wafer.The comb fingers and the folded suspension beams werericated by etching various trenches with widths ranging fr2.5 to 33 mm. The beams were released by the notcheffect, and PECVD oxide thin film was used to protect tsidewalls of the wide trench suspension beams to pre


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over-release. SEM micrographs of the comb fingers andfolded beam were taken and provided in Figs. 16~a! and16~b!, respectively. The features obtained were excellenclean with no stiction and are all of the same depth. Tdisplacement measurement was performed on the actuatoapplying a ramping voltage that ranged from 0 to 36 V btween the electrodes of the fixed and movable finger sFigure 17 is a graph showing the displacement versus vage characteristics. The dots are the tested results andsolid line represents the designed values. The two resagree very well with each other.

This technique enables the height of the microstructuto be designed to be fabricated and realizes more powedevices, since the oxide coverage depth of beams withferent feature sizes can be adjusted accordingly. Forample, if the comb finger has a greater depth than that ofsuspension beam, the driving voltage can be decreased.reverse can also be achieved, whereby the beams with wtrenches can be made deeper than the narrow trench mstructures. The design and fabrication of microstructuresthick SOI wafers are much more flexible and powerful whusing this proposed process.

V. CONCLUSIONS

The notching or footing effect on a SOI wafer duenonuniform trenches was reduced greatly by using multisetching and spacer oxide thin film coating combined wanisotropic plasma oxide etching. Dry release by making

FIG. 17. Movement experiment of the dry released high aspect ratio coactuator:~line! simulation result and~dots! experiment results.

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of notching was realized on a thick SOI wafer for a MEMprocess, where PECVD oxide deposition and anisotropicide etching back were both employed to adjust the depththe beams. The buried oxide layer was used to obtainlateral undercutting. The optical switch was fabricated athe experimental results correspond well with the desigvalues, which validates this dry release process.

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Technique for preventing stiction and notching effect on ... papers... · rication technology.1–3 Silicon-on-insulator~SOI! wafers are more frequently used for MEMS because the