DESCRIPTION OF THE MOXE ANALOG

ELECTRONICS BY

CHRIS FULLER

3/18/91

TABLE OF ·CONTENTS

A. ANALOG CIRCUITRY.........................1

1. POST AMPLIFIER.......................1

2. ANTI-COINCIDENCE AND XY SUM AMPS......5

3. XY SUM SAMPLE AND HOLD...............6

B. DIGITAL CIRCUITRY......................7

1. DISCRIMINATOR.........................7

2. TIME TO ANALOG CONVERTER.............12

3. ANALOG TO DIGITAL CONVERTER..........15

4. BUFFER................................19

C. HOUSEKEEPING CIRCUIT....................23

1. ANALOG PROCESSING MODULE (MOXCHAN CIRCUIT)This circuit consists of the following subcircuits:

A. ANALOG CIRCUITRY1. Post Amplifiers (4)2. Anti-Coincidence Amplifier and XY Summing Amplifier3. XY Sum Sample and Hold Circuit

B. DIGITAL CIRCUITRY1. Discriminator Module2. Time to Analog Converters (2)3. Analog to Digital Converter4. Output Buffer and Control Logic

The overall function of this circuit is to:1. Accept the pulse outputs from the 4 x-ray

detector pre-amplifiers (X+, X-, Y+ and Y- preamps)

2. Generate position (X and Y coordinate) where the X-ray hit on the detector.

3. Generate the ener9y of the X-ray .4. Convert the position and energy to digital

and transfer the converted data to the digital electronics for processing .

There are 6 Analog processing modules in the MOXE experiment, one for each detector .

The MOXCHAN circuit gets its input signals from one detectors pre-amps. The signals from the detector feed the MOXCHAN circuit 5 signals on tri-axial cables. They are the anti-coincidence signal and the 4 signals used to derive position and energy . The outputs of the MOXCHAN circuit consist of a temperature signal, Data Available signal (DAV' ), 16 bit data bus (ADC converted data), 6 bit select bus and a 4 bit rates bus . They are all fed to the Interface Data System(MOXIDS) via a 60 pin header and a backplane bus . The meaning of the signals is:

A. ANALOG CIRCUITRY

1. MOXE POST AMPLIFIER:

The MOXE post amplifier is a bipolar pulse shaping amplifier that is, in effect a bandpass filter .It's purpose is to convert the unipolar output pulse of the pre-amplifier into a bipolar pulse. The zero crossing of the bipolar pulses will allow the determination of position (X and Y coordinate) where the x-ray hit on the detector by the time to analog converter.

There are 4 post-amplifiers for each of the 6 MOXE detectors (two each for the x and y coordinates) for a

total of 24. To determine a coordinate of an x-ray's position (X or Y coordinate) the time difference between zero-crossins of the two post-amp outputs is determined. This processing is done by the Time to Analog Converter discussed in section 6 below.

The design of the post-amplifier follows from the papers written by C.H. Nowlin and M . Kopp . It is a seventh order filter that has been segmented into 3 stages with an additional 4th stage for blocking the D.C. component of the output.

The design has been modified slightly from the written papers to increase the slope of the output signal at the zero crossing. This has been done to reduce possible affects of noise on the output signal, inducing multiple zero-crossins. The design has also been modified slightly to increase the average duration (dwell time) of the output signal of the post amp to 12 microseconds .This is an increase from the 1.505 microsecond dwell time of the detector. This modification causes more of a spread in the zero-crossing times which allows for a more accurate determination of the position of the x-ray.Summing the output of the post-amps results in a signal that is directly proportional to the energy of the x-ray. This summing is done in the XY summing amplifier discussed in section 3 below .

The four stages of the post amplifier are disussed below. The discussion will use the component reference numbers from the MOXPOSTl circuit. The pole-zero constellation from the paper by Nowlin and Kopp for the post amp is discussed below.They are selected using a normalized Noise Corner Time Constant (NCTC) of 1 second. The NCTC is one-seventh of the dwell time of the bipolar pulse . With a dwell time of 12 microseconds (designed-to value) , the actual NCTC is 1.714 microseconds . Thus, the value to use to scale the constellation is the actual NCTC value. The neta parameter used below is a scaing factor that scales the constellation so that it will have an optimum pulse-duration time. For the seventh order constellation filter discussed below, the value of neta is 1.264.

The constellation values below are calculated from information in the article . Afterwards, the act11 l constellation used will be presented.

ZEROS = +jl.8*neta*NCTC = 3.9E-6 (sec)-> Controls undershoot &

symmetry

-jl.8*neta*NCTC = -3.9E-6 (sec)-> Controls undershoot &

symmetry

0 -> Generates bipolar response and blocks DC

Pole-Zero Cancellation zero = zero at NCTC= 1.714E-6 (sec)-> simplifies the noise

power spectral density for the shaping amp.

POLES = -l.5*neta*NCTC = -3.25E-6 (sec)-> Reduces excess peaking

-1.0*neta*NCTC = -2.167E-6 (sec)-> Monotonic step response

(-l+j0.6)*neta*NCTC = -2.167E-6+jl.3E-6 (sec)-> Monotonic step response

(-1-j0.6)*neta*NCTC = -2.167E-6-jl.3E-6 (sec)-> Monotonic step response

(-l-jl.2)*neta*NCTC = -2.167E-6-j2.6E-6 (sec)-> Monotonic step response

(-l+jl.2)*neta*NCTC = -2.167E-6+j2.6E-6 (sec)-> Monotonic step response

(-1-jl.8)*neta*NCTC = -2.167E-6-j3.9E-6 (sec)-> Monotonic step response

(-l+jl.8)*neta*NCTC = -2.167E-6+j3.9E-6 (sec)-> Monotonic step response

a. The first stage consists of the pole at-l*neta*NCTC and the pole-zero cancellation (PZC) zero. The transfer function for the first stage is:

Hl (S) = [s+l/(Cl*Rl*R2)]/[S+ (Rl+R2)/(Cl*Rl*R2) ]

This puts the PZC zero at 2.76 (rad/sec). This is a factor of 2.11E5 less than the computed PZC zero. The pole from the transfer function is at 3 .039E6 (rad/sec). This is a factor of 6.59 greater than the computed value.

The impedance isolating op-amp has again of (R9*R5+R3*R9+R3*R5)/(R3*R5) which computes to 8.68 (V/V) . The positive DC offset is 6*R9/R5 which computes to +3.841 volts .

The resistor-capacitor network (R6-C3) between the inverting and non-inverting inputs of the op amps. The function of these are to provid e

compensation to the op-amp.

b . Second stage

The second stage is where most of the pulse shaping occurs. The transfer function is computed from pgs. 121-123 of System Design by Truxal:

H2 (s) = Yl*Z2*Y3*Z4*Y5*Z6/ [ (Z2*Yl+Z2*Y3+Z4*Y3+Z4*Y5+Z6*Y5)

+(Z2*Yl*Z4*Y3+Z2*Yl*Z4*Y5+Z2*Yl*Z6*Y5+Z2*Y3*Z4*Y5+Z2*Y3*Z6*Y5+Z4*Y3*Z6*Y5)

+Z2*Yl*Z4*Y3*Z6*Y5]

Where: Zl = RlO+s(Ll+L2) Yl = 1/(RlO+s (Ll+L2)) Z2 = 1/(s(C6+C7))Y2

s(C6+C7)Z3 = s(L3+L4) Y3 1/Z3Z4 = l/s(C8) Y4

s(C8) Z5 = s(L5+L6)

/(sA 2 (L5+L6)C9+1)Y5 1/Z5Z6 = Rll/(s(Rll*ClO)+l) Y6 = l/Z6

The resultin9 transfer function is very long and will be detailed on the next revision of this document as I haven't yet solved the equation for the individual pole frequencies. The zeros of the transfer function are at+j/[(L5+L6)*C9J A 0.5 and -j/[(L5+L6)*C9J A 0.5.These correspond to the computed overall transfer function zeros at +jl .8(neta) (NCTC) and-jl.8(neta)(NCTC) , respectively. The zero frequency from the circuit component equation above is l.629E6 (rads/sec). This is a factor of 6.35 times greater than the zero frequency computed from the paper by Nowlin .

The gain of the impedance isolation op-amp is (Rl2+Rl4)/R12, which computes to 21.07(V/V) .

c. Third stage

This stage provides the pole at -l.5 (neta) (NCTC) and a zero at 0. The transfer function is:

H3(s) = s/[s+l/(Rl6*C12)]

The zero at s=O differentiates the signal so that a bipolar pulse is generated. The pole at 1/(R16*Cl2) computes to l.11E6 (rad/sec). This is a factor of 3 .61 greater than the value computed from the paper by Nowlin .

The isolation op-amp provides a gain of(R15+R18)/R15, which computes to l+R18/TBD.

d. Fourth stage

This stage provide low pass filtering and

DC blocking. The circuit is equal in architecture to the third stage, but the size of the capacitor is much larger. This leads to a lower cutoff frequency at 1/(Rl9*Cl4), which computes to1 (Krad/sec).

2. ANTI-COINCIDENCE AMPLIFIER AND XY SUMMING AMPLIFIER (MOXSUM2)

There are two independent circuits contained within this schematic. They are discussed below.

a. Anti-coincidence amplifier: This is the lower circuit. The input is labelled 'VI' and the output is labelled 'AI '. It consists of a two stage amplifier . The overall function of this amplifier is to amplify the Anti-coincidence preamp signal and provide the resulting signal to the discriminator circuit that will compare the signal to a programmable threshold level. If the anti-coincidence signal exceeds the threshold level, the abort signal (ABT) is asserted and fed to the output buffer and control logic to abort transferring the converted data to the digital electronics (Interface Data System) . The abort signal is also fed to the rates bus so that measurement of abort rates can be accomplished.

The first stage of the anti-coincidence amplifier consists of a 2nd order biquad filter with a passband of 2 (Mrad/sec) and quality factor 0.5. The center frequency is 1 (Mrad/sec). The transfer function is:

H (S} = [s-2+s*(l/R91+1/R90)*1/C60+1/(C60*C6l*R90*91)]/[s-2+s*{l/(R91*C60)+1/(R90*C60)+1/(R90*C61)}

+l/(C60*C61*R90*R91)]

The second stage of the anti-coincidence amp consists of a non-inverting amplifier with a gain of:(R97+R94)/R94 . The second stage also uses an op-amp with pole-zero compensation via a resistor and capacitor connected across the input terminals .

The purpose of the summing amplifier is to sum the 4 output signals of the postamps together . This results

in a signal that is directly proportional to the ener9y of the detected x-ray. The summing amplifier consists of two stages. The summing (first) stage and an amplifier (second) stage . The summing stage has atransfer function of H (S) = [(IX+)+ (IX-)+(IY+)+ (IY-)]. The summing stage also has a compensating network connected across its differential inputs. The amplifier stage is an inverting amplifier with a gain of -R87/R84.

3. XY SUM SAMPLE AND HOLD

CIRCUIT TO BE CONTINUED

••••

B. DIGITAL CIRCUITRY

1. DISCRIMINATOR CIRCUIT (MOXDISC)

The MOXE discriminator circuit is used to determine if the x-ray detected is an x-ray (via the anti-coincidence, upper-level and rise- time discriminators). If it is an x-rar, the discriminators verify that the energy of the x ray is within the range that the scientist is interested in before enabling processin9 of the signals detected.The anti-coincidence discriminator is used for determining if a high energy photon or particle has been detected whose energy is beyond the interest of the scientist. One function of the discriminator is to detect when the XYSUM signal (i.e. energy of the x-ray) is at it's peak. This allows the XYSUM SAMPLE AND HOLD circuit to sample and hold the peak value of the XYSUM signal. The voltage references for the discriminators are derived from the+5 volt reference in the TAC. Another function of the discriminators is the determination of when the XYSUM signal crosses the O volt axis. This is used for determining the RTD (Rise Time Discriminator) signal in the MOXBUFF circuit. The indication of the XYSUM signal crossing O volts is indicated by the XYZERO signal.RTD is defined as XYZERO latched on the positive edge of RTDO'. RTDO' is the output of a one-shot timerwhich is started when the peak of the XYSUM signalis detected by the RTDO discriminator. The net effect is: RTD = O if the XYSUM signal O crossing occurs after the one-shot timer times out (i.e. rise time of XYSM within bounds). RTD = 1 if the XYSUM signal O crossing occurs before the one-shot timer times out (i.e. rise time of XYSUM too high) .

The only other function of the discriminator board is to enable the Time to Analog Converters (via the ENX+, ENX-, ENY+ and ENY- signals).

Following is a more detailed description of the discriminator circuit functions :

A. ANTI-COINCIDENCE CIRCUITRY :The anti-coincidence discriminator circuitry is

the circuitry that compares the analog signal from the anti-coincidence amplifier with a dynamically adjustable comparison voltage and issues abort and anti-coincidence discriminator triggers to the MOXE buffer board (MOXBUFF) and rate counters.The adjustable comparison voltage is set by an 8 bit command byte which is written to thediscriminator board. The 8 bit command byte is written to an octal-D flip flop IC when BD' =O and WR 1 transitions from 1 to O. The data byte to be written is asserted on the 1 DBUS' data bus and is defined as follows:

BITO&l FUNCTION

Used to determine the comparison voltage for the low-level discriminator . This is done via the 'A' and 'B 1 digital select lines on the triple 2-channel multiplexerand resistor divider networkson the analog input lines (see LLD description) .

2&3 Determine the comparison voltage for the anti-coincidence discriminator. This is done via the 'C' select line and the A select line andresistor divider networks on the analog input lines (see below) .

4 Determines the comparison voltage for the upper level discriminator. This is done via the B select line and resistor divider networks(see ULD description) .

5 Determines the RC time constant for the RTDO one shot timer.This is done via the C select line and two resistors tied to +5V(see RTD description) .

6 Anti-Coincidence Abort enable (1)

7 ULD Abort enable (1)

The settings of the discriminator levels can be read by digital logic via the octal buffer ICThe octal buffer asserts the threshold level settings on the data bus (in the order they were written) when BD' = 0 and RDT' = 0.

The equation for the voltage at the positive

input to the anti-coincidence discriminator

is: Rsw = ([D2'*R8+D2*R9]A-l+ [D3'*Rll+D3*R12]A -l)A-l

v+ = Vref*Rsw/(R3+Rsw)Vref = +5 volts from TAC referenceThe comparator used for discrimination is

connected in a feedback fashion to generate hysteresis which prevents stray feedback from generating oscillations in the output. The spec . sheet for the LM139 also recommends using input resistors below lOK ohms to reduce the feedback signal levels. Since the LM139 has an open collector output, a pull-up resistor is connected on it's output. The output of the comparator is defined as the signal ALLD'. ALLD' is used in generating the trigger for two one-shot timers.The first asserts the ALLD (Anti-Low Level Discriminator) signal for 0.7*R39*C8 secondsafter ALLD' is asserted.ALLD is fed to the rates bus for rate determination .

The other one-shot timer that is triggered by ALLD' is the ABT (Abort) one-shot . Thisone shot asserts ABT for a duration 0.7*R40*C7 seconds after the upper level discriminator (ULD') is asserted (ULD'=O) or the ALLD' signal is asserted. Thus, the ABT signal is asserted only when the detected particle triggers the upper level and the anti-coincidence discriminators .This should only happen if the input thresholds are set properly and a very high energy particle is detected. The ABT signal is fed to the rates bus for determination of abort rates and to the buffer board (MOXBUFF) to initiate an abort of the data transfer from the MOXBUFF circuit to the digital electronics by suppressing the DAV' signal from being asserted.

B. LOWER LEVEL DISCRIMINATOR CIRCUITRY

The lower level discriminator circuitry is used for determining whether the detected x-ray has the minimum energy that the scientist is interested in studying . The output of the discriminator is then used in enabling the TAC and XYSUM sample and hold circuits. The reference level of the lower-level discriminator is set as discussed above. The reference voltage at the input of the comarator used for low level discrimination is:

Rsw = ([DO '*R4+DO*R5]A -l+[Dl'*R6+Dl*R7J A -l)A-1

V+ = Vref*Rsw/(Rsw+R2)

Vref is +5 volts from the TAC reference

When the input signal at the inverting input(XYSUM) exceeds that at the non-inverting input, LLD' (the output of the comparator) is asserted. The assertion of LLD' triggers two one-shot timers. The first triggered timer asserts the signal LLD after LLD' has been asserted. LLD is asserted for a duration of 0.7*R42*C4 seconds .The LLD signal is fed to the rates bus for the determination of the rate that LLD is asserted. The second timer is used for enabling conversions of the detector pulses into energy and position values. The output signal of the second timer is EN. EN is asserted for a duration 0.7*R43*C2 seconds after LLD' is asserted. EN is also asserted when LLD' is asserted when BUSY' transitions from being asserted to not being asserted.

EN is used to enable the Time to Analog Converter circuit via the ENX+, ENX-, ENY+ and ENY-signals . EN is wire-AND'ed to the XYZERO signal that is used in generating the RTD (Rise Time Discriminator ) signal, which is fed to the MOXE digital electronics in the MOXBUFF circuit.Finall¥, EN is wire-AND'ed to the output of the Rise Time Discriminator whose result isused to start the Rise Time Discriminator one-shot timer (see the discussion on the rise time discriminator circuit for more details).

C. UPPER LEVEL DISCRIMINATOR

The upper-level discriminator is used for determining whether the energy of the detected x ray is greater than a reference energy that the scientist is interested in. The output of the upper level discriminator is used in generating the ABT (abort) signal as discussed in the Anti coincidence discriminator section.

The voltage reference for the upper level discriminator is:

Rsw = (D4'*R13+D4*R14)

V+ = Vref*Rsw/(Rsw+RlO)

Vref is the +5 volt reference from the TAC

When the XYSUM signal exceeds the referencesignal, ULD' is asserted. This triggers the one

shot timer, to assert ULD for a duration of o.7*R41*C5 seconds after ULD' is asserted. The ULD sinal is fed to the rates bus for determination of the rate of upper level discriminator aborts. The ULD' signal is also used in the determination of the ABT (abort) signal as discussed in the Anti-coincidence discriminator discussed above.

E. RISE TIME DISCRIMINATOR

The overall urpose of the rise time discriminator is to determine whether the XYSUM signal is rising faster than an adjustable reference time that is set by bit D5 of the command byte.

The rise time discriminator comparator is used in locating the peak of the XYSUM signal.The XYSUM signal is fed directly into the + input of the comparator which has an offset voltage added by R35 and R36 . The XYSUM signal is fed to the inverting input of the comparator with a capacitor shunting the signal to ground. This effectively delays the signal input to the inverting input. The time constant of the inverting input signal is R33*C6. The output should trigger less than approximately 5*R33*C6 seconds after the peak occurs. The output of the comparator is wire-AND'ed to EN' from the low level discriminator before the one-shot timeris triggered to start. RTDO' is assertedfor a duration set by C9 and a switch selectable resistance determined by the scientist.

The time duration that RTDO' is asserted is the reference time for the XYSUM signal and is given by the formula:

T = 0.7*C9*[D5'*R15+D5*R16]DS = Data bus bit 5 from the command byte

The RTDO' signal feeds the clock of a n-latch in MOXBUFF that latches the XYZERO signal for output to the MOXE digital electronics .

If the reference timer times out after the XYSUM zero crossing comparator triggers, the RD bit that will be read by the MOXE digital electronics will be 1. This indicates that the rise time of the signal is faster than th9reference (i.e. it is too fast). RTDO' is used in the XYSUM sample and hold circuit to start the sample and generate BUSY' .

F. XYSUM ZERO CROSSING DETECTOR

The purpose of this part of the circuit is to detect when the XYSUM signal crosses O volts. The O crossing is indicated by the positive logic signal XYZERO . The XYZERO si9nal is used to generate the RTD (Rise Time Discriminator) signal that appears to the MOXE digital electronics .

This circuit consists of a comparator connected as a zero-crossin9 detector. Shottky diode CR7 ensures that the inverting terminal never goes below approximately -0.3 volts, thenegative voltage input limit of the LM193.

R46 is the pull-up resistor for the output of the comparator. Before the XYZERO is sent to the MOXBUFF circuit, it is wire ANDed to the EN(enable) signal from the low level discriminator.

2. TIME TO ANALOG CONVERTER (TAC)

The functions of the Time to Analog Converter (TAC) are as follows:

1. Generate a precision 9 volt reference for the time to analog conversion via a 5 volt reference (AD586) and a low power, precision op-amp.

2. Enable the starting, stopping and resetting (discharging) of the TAC via zero crossingdetectors and control logic. Signals used as inputs to the circuitry are from the discriminator circuit (ENX+, ENX-, ENY+, ENY-) , postamp outputs (XIN+,XIN+, YIN+, YIN-), XYSUM sample and hold circuit(BUSY) and the buffer board (RST'). There are two TAC converters, one for the x-coordinate and one for the y-coordinate . The only circuitry they share is the +9 volt reference output .

3. Hold the completed TAC conversion value for output to the Analog to Digital converter board via a high speed op-amp (AD644). •

4. Generate sign bits (B6X and B6Y) indicating which input from the postamps (XIN+, XIN-, YIN+ and YIN-) crossed O volts first.

The following sections will discuss the above functions in more detail .

A. GENERATION OF PRECISION 9 VOLTS FOR TAC

This is accomplished by the use of a precision 5

volt reference IC and a precision op-amp The output of the 5 volt reference is fedto the non-inverting input of the op-amp through R61. The output of the precision op-amp is(R62+R64)*Vref/R62. Vref is the output of the +5 volt reference IC.The resistance ratio should be about 1.8. The +5 volt reference IC feeds the discriminator the 5 volt reference it needs to set the reference voltages for the discriminators.

The +9 volt reference feeds both TACs and is actually used in setting the current in the charging capacitor when it is commanded to charge .

B. STARTING, STOPPING AND RESETTING THE TAC

The circuitr¥ that actually does the time to analog conversion consists of two pairs of differential amplifiers for each coordinate. For the x-coordinate, the two pairs are Q2-Q3 and Ql Q4 and their associated biasing circuitry.

For the y-coordinate, the two pairs are Q8-Q9 and Q7- Q10. C24 is the charging capacitor for the x coordinate and C72 is the charging capacitor for the y-coordinate.

The reset command (RST ') from the buffer circuit (MOXBUFF) controls the resetting of the charging capacitors (to approximately O volts) through two JFET's and their associated biasing circuitry.When RST' is asserted low, the JFET's switch on, discharging the capacitor.

The logic to

************ more here

C. HOLDING THE TAC CONVERSION VALUE

D. GENERATION OF SIGN BITS

3. ANALOG TO DIGITAL CONVERTER (MOXADCL )

The function of the MOXE analog to digital converter circuit is to:

1. Generate analog to digital representations of the energy, x-coordinate and y-coordinate of the detected x-ray.

2. Generate timing signals so that the digital data can be passed to the buffer board for storage and transfer to the MOXE digital electronics .

The MOXADCL circuit does this with the following subcircuits:

1. Clocking circuitry for driving all of the above and generating an upper level reset.

2. Volta9e reference, analog to digital converter and circuitry for starting the ADC.

3. . Analog multiplexer with selecting circuitry to select the analog channel for conversion and timing circuitry for transferring the converted data to the buffer board properly.

The followin9 considers the sub-circuits in more detail (also see the timing diagrams for more detail) .

1. CLOCKING CIRCUITRY

A 2 MHZ oscillator (038) is used for providing the primary clock source of the MOXADCL circuit. The Analog to Digital Converter (037) receives its clock directly from the 2 MHZ oscillator after inversion via NOT gate U7E.

The 2 MHZ clock is fed to two cascaded 4 bit binary counters (039 and 040) after being gated by the BUSY' signal. The counters are used to divide down the clock to 1 MHZ and generate an upper level reset (URST'). The 1 MHZ clock comes from pin 3 of the low nybble counter, 039. The 1 MHZ clock feeds the clock of flip flop U30A which is configured to divide the clock by 2. The inverting output signal is labelled 500 KHZ' and the non-inverting output signal is labelled 500 KHZ. These two 500 KHZ clock signals are used by the rest of the circuit for most of it's timing.

The upper level reset signal (URST' ) is output from pin 12 of the upper nybble counter, 040. The purpose of the upper level reset is to generate a time-out analog system reset if the BUSY' signal(used to reset the counters) does not transition back high within 128 microseconds after USY' transitions to low. This will allow the analog system to automatically reset itself if it latches up. The purpose of the upper level reset signal is to trigger the buffer circuit to assert the analog system reset (RST) signal.

2. VOLTAGE REFERENCE, ADC AND STARTING CIRCUITRY

The voltage reference (036) for the ADC is

anAD586, which provides a 5 volt reference to theADC. The ADC (037) is an Analog Devices AD7672,

which derives its operating power from Vss (+5V) and Vss (-12V). An external clock is provided for the analog to digital conversion from the 2 MHZ oscillator. The conversion begins when the RD' input (STADC) of the ADC goes low. During the analog to digital conversion, the BUSY' output of the ADC will be asserted low. At the end of the conversion, it will transition to high. The analog input to the ADC is from the analog multiplexer(U28). The circuitry that starts the analog to digital conversion consists of U31A, U31B and U33B. The circuitry starts the ADC between 1 and 2.03 microseconds after BUSY transition from low to high. It does this by clocking a high state into the output of the flip-flop U31B. The output of U31B feeds the data input to U31A. The clock input to U31A is from a 500 KHZ clock generated by U30A(signal 500KHZ). The output of U31A feeds the input to flip-flop U33B. The clock input to U33B is from signal 500KHZ' , which is a 500 KHZ clock shifted 180 degrees in phase from the clock that feeds U31A. The inverted output of U33B is used to generate the start ADC signal. Thus , the propagation of a high data input signal in theflip-flops is what starts the ADC.

The purpose for delaying the start of the ADC can be found by following the output of U31A to the clock input of U33A. Flip flops U33A, U30B and the NANO gates U25A, U25B and U35A are used for generating the select signals for the analog multiplexer and the output pulses to the buffer board to clock in the converted data from the ADC board. The delay in starting the ADC allows time for settling of the analog multiplexer output on the signal of interest. The clear input to U31B is provided by the circuitry that transfers data to the buffer board. When the last converted value(the Y-coordinate) is passed to the buffer board, the signal BYT3L strobes high. On it's trailing edge, the input to inverter U7A transitions low for approximately one microsecond. This makes the output of the inverter U7B transition to low for approximately one microsecond, clearing 31B and U33A and setting U30B . This results in the remaining MOXADCL circuitry resetting. When BUSY transitions from low to high again, analog to digital conversions and transfers to the bnffer board can begin again. See section 3 below and the timing diagrams for more details .

Notice that the clear line for U31A is connected to the output of NAND gate U35B. The inputs to U35B are the 500KHZ' signal and the output of flip flop U29B. Flip flop U2B and U29B are used for

resetting flip flip U31A which enables starting another analog to digital conversion. They are also used for generating a low pulse on the output of NAND gate U35C, which enables pulse outputs to the buffer board for latching the converted data. When an analog to digital conversion is completed, the BUSY' output of the ADC (037) transitions from low to high . This clocks a high state into the output of flip flop U2B. The high state of output U2B is passed to the output of flip flop U29B, which is clocked by the 500KHZ clock signal. The output of U29B is reset low 2 microseconds after it transitions high due to the clear input of U2B being provided by the inverted output of U29B.

3. ANALOG MULTIPLEXER WITH SELECTING CIRCUITRY AND CIRCUITRY FOR TRANSFERRING THE ADC VALUE TO THE BUFFER CIRCUIT.

The analog multiplexer (028) has input signals from the time to analog converter for the x coordinate (XHLD} and y-coordinate (YHLD). The other input is from the XY sum sample and hold circuit (SUMHLD). The outputs of the analog multiplexer (signals Sl, S2 and S3) are all tied together before being provided as input to the analog to digital converter. Since only one input is selected to be output at a time (by the INl, IN2 and IN3 signals), this doesn't cause a shorting problem.

The selecting signals (INl, IN2 and IN3) close contacts between the input signals (Dl, D2 and DJ) and the output signals (Sl, S2 and SJ) when the state of the respective IN signal is low.

The circuitry that supplies the selecting signals consists of flip flops U33A, U30B and NAND gates U25A, U25B and U35A.

When the output of flip flop U31A first transitions from low to high (indicating that an analog to digital conversion is about to begin) , U33A clocks a high level to it's output. When the output of U33A transitions from low to high, flip flop U30B clocks a low level to it's output. Theoutput of the NAND gates are set by the following table:

OUTPUT (U25A) OUTPUT (U25B) OUTPUT (U35A)

[Q (U33A} *Q' (U30B) ]1

[Q' (U30B)*Q' (U33A}] 1

= [Q (U30B)*Q (U33A) J I

When the output signal is low, the respective analog input to the analog multiplexer is selected.

The SUMHLD signal is selected when the output of U25A is low. The XHLD signal is selected when the output of U25B is low. The YHLD signal is selected when the output of U35A is low.

The two flip flops U33A and U30B are configured so that the outputs of the NAND gates are a state machine with 6 states. The transition between the states is triggered by a low to high transition in the output of flip flop U31A. The state table is as follows:

ST ORT SELECTED

The output of the NAND gates are fed to NOR gates. The other input to the NOR gates is from the NANO gate U35C. The purpose of U35C is to gate the output of the NOR gates is to provide a clock to the respective set of latches in the buffer circuit. The converted value from the analog to digital converter is latched into the buffer circuit on the positive edge of the clock from the NOR gate. On the trailing edge of the last transfer to the buffer circuit (i.e. de-assertion of BYT3L to low) the state machine is reset to its initial state. The de-assertion of BYT3L also resets flip flop U31B , which halts the initiation of analog to digital conversions .

4. BUFFER CIRCUIT

The purpose of the MOXE buffer circuit is to:

1. Transfer the analog to digital converted data to the MOXE digital electronics under control of the MOXE digital electronics.

2. Generate an analog system reset when the data has been read by the MOXE digital electronics or if an abort is generated by the discriminator circuit(ABT signal) or analog to digital converter circuit (URST signal) .

The buffer circuit accomplishes these functions via the following subcircuits :

1. Latches and latch control circuitry for storing the

ATE 0

Q (U25

Q (U25

Q(U35A)

AMUX P NONE1 0 1 1 SUMHLD

2 l 1 1 NONE3 1 0 1 XHLD4 1 1 1 NONE5 1 1 0 YHLD

data passed from the analog to digital converter until the MOXE digital circuitry is ready to read it (including the Rise Time Discriminator).

2. Circuitry for indicating when the analog electronics is ready to transfer data (via the DAV ' signal).

3. Circuitry for processin9 signals from the MOXE digital electronics facilitating transfer of data.

4. Circuitry for generating the analog system reset signal (RST).

The following discusses tne above subcircuits in more detail.

1. LATCH CIRCUITRY

The latch circuitry consists of the octal latches (U22, U45 and U44), the input and output data busses and circuitry provided by the analog to digital board for timing the latching of the data.

Each of the latches is used to store one converted parameter to be read (x-coordinate, y coordinate or energy). The latch circuitry consists of the octal latches (U22, U45 and U44) , the input and output data busses and clocking circuitry provided by the analog to digital circuit for timing the latching of the data.

Each of the latches is used to store one converted parameter to be read (x-coordinate, y coordinate or energy). The latches clock in data on the rising edge of their associated clock signal (BYTlL, BYT2L or BYT3L). The following table details the association of the clock, latch, parameter of interest and order in which they are latched (beginning with the first latched) .

ORDER123

CLOCK BYTlL BYT2L BYT3L

LATCH U44 U45 U22

PARAMETERENERGY (8 BITS)X-COOR. (6 BITS), X-SIGN AND Y-COOR. (6 BITS) AND

-SIGN

RTD

The sign bits are from the time to analog converter and indicate the end of the wire in the detector that the x-ray was detected closest to. When it is O, the x-ray was detected closest to the negative end of the wire. When it is 1, the x-ray was detected closest to the positive end of the wire .

The rise time discriminator signal (RTD) indicates that the signals generated by the

detected x-ray are rising faster than the rise of detected signals in the range of interest. the discriminator for more details on the generation of the XYZERO and RTDO signals.

The XYZERO signal is asserted to 1 when the

time See

signal representing the energy of the detected x ray crosses O volts.

The RTDO' si9nal is asserted to 1 at the end of a programmable interval that allows for a variable range of rise times. The overall result is that RTD is asserted high if the signal rises faster than those of interest. Note that the Rise time circuitry may be eliminated due to the inability of the detector to distinguish x-rays from charged particles. See documentation on the discriminator circuit for more details on the rise time discriminator.

2. DATA AVAILABLE INDICATION

The data available signal (DAV') indicates to the MOXE digital electronics that the analog electronics is ready to transfer the converted data.

DAV' is generated by latches U41A and U41B and NOR gate U24A. DAV' is asserted low when BYT3L clocks high. This means DAV' is asserted low.DAV' is asserted low when the last ADC value (y coordinate) is latched by U22. DAV' is de-asserted high when the analog system reset signal is asserted (RST' is asserted low). DAV' is prevented from being asserted low if the abort signal (ABT') is asserted low. See the timing diagram for more detail .

3. TRANSFER CIRCUITRY

The circuitry responsible for transferring the data to the MOXE digital electronics consists of NAND gates U42A and U42D, NOR gate U6A and NOT gate U7F. They generate the signals SELXY' a™3. SELE', which supply the output enable signals for the octal latch IC's.

The inputs to the circuitry is from the select bus (SELB) of the MOXE digital electronics . The BD' signal is asserted low when the buffer board has been selected for transferring it's data. The RDD' signal is asserted low when one of the registers on the buffer board is to be read.The SAO indicates the register that is to be read, the

I

/: I

i_., 1 ) ',,

·"-l>

Q

:'.) ...... 0

"' --:.f Joi .lo r °'

---- <::),

to ......._

e '-J

.

·N !'\I '""<

(""'\

\'

....... .-_,,.

<::>...c

..i.::::..

1

9J"-....--.....,

('-. I ' 1

""11::...........

" t··,II· · l Ii I ' I

I r III

-f-

\

I

xy register (when SAO = 1) or the energy register(when SAO = O). Although there are four parameters that are read (x-coordinate, y-coordinate, energy and rise time discriminator), they are read by the MOXE digital electronics using 2 registers. The energy register contains the 8 bit analog to digital conversion of the analog energy signal .The energy value is transferred to the MOXE digital electronics via a 16 bit data bus on the least significant byte.

The XY register contains the x coordinate and y coordinate of the location on the detector where the x-ray was detected . The 7 bit coordinate values include 2 sign bits which indicate the quadrant of the detector where the x-ray was detected. The rise time discriminator (RD) bit is also transferred via the XY register. The RD bit is asserted high when the detector detects a charged particle instead of an x-ray. The format of the XY register is as follows:

BIT OF XY REGISTER

-DO .•D5 D6D7D8..D13 D14 D15

MEANING-X COORDINATE X SIGNRTD BITY COORDINATE Y SIGN0

The MOXBUFF registers are read when RDO' and BO' are asserted low. SAO selects the register to be read. The XY register is read first when SAO is asserted high. The energy register is read second when SAO is asserted low.

4. RESET CIRCUITRY

After the energy re9ister is read, NANO gate U43B toggles high. This triggers one-shot U32B to assert the reset (RST) signal high for0.7*R53*Cl0 seconds. This results in a reset of the time to analog converters and XYSUM sample and hold circuitry which prepares the analog circuit to detect another x-ray. The analog system can also be reset if the abort signal from the discriminator circuit (ABT ') is asserted before the y-coordinate is transferred to the buffer board. See the timing diagram for more detail.

C. MOXE HOUSEKEEPING BOARD

The functions of the MOXE housekeeping board are:

1. Turns the detector's high voltage power supply ON or

OFF. Automatically turns off the high voltage power supply and flags an interrupt to the MOXE digital electronics when the overexposure sensor triggers at a preset level (e.g. 5000 detected events per second). The interrupt to the digital electronics is reset when a command is sent to turn the high voltage power supply back on.

2. Set the voltage of the high voltage power supply to a value between approximately 1000 volts and 3000 volts in 128 steps of about 11 volts each.

3. Converts housekeeping signals to digital and sends the dat to the MOXE digital electronics when commanded. The housekeeping signals that are measured are +12 volts, +6 volts, +5 volts, -12 volts, -6 volts, temperature of housekeeping circuit area and the high voltage monitor.

The housekeeping circuit is commanded via a special serial communication IC (the SOR IC, UlO) developed in house. The SOR communicates with the outside world via 3 lines, the clock line, received data line and return data line. The clock and received data lines are inputs to the SDR from the MOXE digital electronics SDX chip (the mate for the SOR). The received data line is the line on which the SDX selects a SDR to communicate with and is the line on which the command data is sent to the SDR. The return data line is the line on which the SDR IC sends data back to the SDX in response to a command.

Since the SDX may communicate with many SDR Cs, an addressing scheme is used to uniquely identify each SDRIC. Each SOR in the housekeeping circuit is hard wired with a unique address (values o to 5) on the SOR address bus via signals AORO through ADR5 on the housekeepingcircuit.

When power is first turned on to the housekeeping circuit, reset circuitry (consisting of R30, C13 and U6A) hold the reset pin (RST) of the SDR IC low for approximately 50 microseconds . This results in the SDR powering up into the proper state.

There are 3 input/output ports on the SOR IC that are used to control the housekeeping circuitry.

The PDO port is an 8 bit output port . Only 4 of the bits of the PDO port are used by the housekeeping circuit. These are labelled CAO through CA3 and are used for controlling the analog multiplexer and high voltage monitor portions of the circuit.

The PDE port is a programmable, bi-directional 8 bit port which has been programmed to be an output . All 8

bits of the port are used for controlling the high voltage power supply. The signal names for the ports signal lines are CBO through CB6 and C7 for the signal from the MSB of the port.

The DB port (named PDI in the documentation on the SDR IC) is an 8 bit input port that is used for reading the results of the analog to digital conversions. All 8 bits of the DB port are used and the signals are labelled DO through 07.

When the MOXE digital electronics SOX IC attempts to communicate with the SDR, it transmits the SDR address, the port that it is interested in (the PDO or the PDB port), whether it wants to write to the port or read back what was previously written to the port and finally it transmits the data that it wants to write into the port .

Once the SDX has transmitted enough information to the SDR so that the SDR knows what to transmit back to the SDX, the transmission back to the SDX begins on the return data line. The returned data will either be the settings on a port that has been requested by the SDX or it will be whatever data is on the DB input port of the SDR (if the read back register command is not given).

When the SDR is commanded to write a new value to one of the output ports, the SDR clocks one of the New Data Ready (NDR) strobes to indicate that the port has been set with the new data and it is available for use. There are two New Data Ready (NDR) strobes. NDRO' strobes low when new data is available on the PDO port. NDRl' strobes low when new data is available on the PDB port. The data on the output port that has been written into is valid on the falling edge of the strobe.

Following is a more complete discussion of the functions of the housekeeping circuit.

A . HIGH VOLTAGE ON/OFF

The high voltage power supply is controlled from two sources, the MOXE digital electronics and the over-exposure sensor in the detector .

Signal C7 from the PDB port on the SDR controls the state of the high voltage supply . When C7 is commanded high by the SDX, the signal '0/0' goes high on the rising (trailing) edge of the NDRl' strobe. The signal '0/0' is the output of the D flip flop (U8A) and is output directly on the CMDO bus to the high voltage supply to turn it on.

Setting C7 low results in the HV supply turning off.

Everytirne the HV supply is turned on, D-flip flop

(U8B) is cleared. The output of U8B is the signal INTO. This signal generates an interrupt on the MOXE digital electronics when it is asserted high. Clearing the flip flop thus deasserts the interrupt.

The only way INTO can be asserted is if the INTI' signal transitions from a low state to a high state. The INTI'signal is from the over-exposure sensor in the detector. INTI' transitions from a low state to high when there is an overexposure condition in the detector. The INTI' transition to a high state causes a positive pulse at the input to an inverter(U6B) which then clears flip flop USA , which results in the HV power supply turning off. The automatic turning off of the HV power results in the deassertion of INTI ' back to a low state . This occurs because the detector is now in an OFF condition preventing any exposure of the detector .Another effect of the assertion of INTI' high is a pulse at the output of U6B, which clocks flip flop U8B, resulting in the assertion of INTO to a high state. A high level on INTO generates an interrupt on the MOXE digital electronics .

To turn off the interrupt (resetting INTO to low), the MOXE digital electronics must turn the HV power supply on.

B. SETTING THE HIGH VOLTAGE LEVEL

Signals CBO through CB6 are used for setting the voltage of the HV power supply. They come from the same port used to turn the power supply on and off(PDB port), so control of the HV power supply can be a one-step operation. The CBO through CB6 signals are fed directly to the HV power supply via the CMDO bus. The HV power supply can be set between approximately 2000 volts and 3000 volts in 128 steps of approximately 11 volts each . 7 bits are provide to generate 128 steps . No information is supplied to the power supply indicating when it's value is to be changed, so the HV power supply operates asynchronously.

C. COLLECTING HOUSEKEEPING SIGNALS

Collecting the housekeeping signals

isaccomplished using three sets of circuitry:Conditioning circuitry, an analog multiplex er and an analo9 to digital converter. The condition ing circuitry normalizes the signal of interest so that the ADC can convert it using it's reference of 5 volts. The conditioning circuitry of each signal will first be considered before proceeding with a discussion of the remaining circuitry.

1. +12 VOLT BUS

The conditioning circuitry for this signal consists of a voltage divider using Rl and R2. This results in a nominal input of 4 volts to port O of the analog multiplexer (U5) .Capacitor Cl is used for reducing spikingeffects.

2. +6 VOLT BUS

The conditioning circuitry for this signal consists of the voltage divider using R3 and R4. This results in a nominal input of 4 volts to port 1 of the analog multiplexer.

3. +5 VOLT BUS

The conditioning circuitry for this signal consists of the volta9e divider R5 and R6.This results in a nominal input of 4 volts to port 2 of the analog multiplexer.

4. -12 VOLT BUS

The conditioning circuitry for this signal consists of an inverting amplifier (Ul) configured to have a 9ain of -R9/R8 . This results in a nominal input of approximately 4 volts to port 3 of the analog multiplexer.

5. -6 VOLT BUS

The conditioning circuitry for this signal consists of an inverting amplifier (U2) configured to have a gain of -R13/R14. This results in a nominal input of 4 volts to port4 of the analog multiplexer.

6. TEMPERATURE SENSOR

The temperature sensing circuitry far this signal consists of a temperature seRsor(AD590) that is modelled by a high impedance current source that varies at 1 micro-ampere per degree celsius . It generates 298.2 micro-amperes at 298.2 Kelvin (25 degrees celsius).

The circuitry that converts this temperature signal to voltage consists of an op-amp (U7) configured as a current to voltage converter. The transfer function of the converter is:

Vout = A*R22*R20*[1/R18+1/R21+1/R20]-6*R20/R18

= 66.945*10A3* (A - 260.53*10A

-6) A = CURRENT IN THE TEMPERATURE

SENSOR

The voltage ranges from o volts, whichcorresponds to -13 degrees celsius to 5 volts, which corresponds to +61 degrees celsius. The voltage output at room temperature (25 degrees celsius) is 2.5 volts. The expected operating temperature range of MOXE is -10 degrees celsius to +20 degrees celsius.

Thus, all expected temperatures can be measured.

7. HIGH VOLTAGE MONITOR

The high voltage supply provides the housekeeping circuit with a monitor signal that is proportional to the voltage setting on the high voltage power supply . The output voltage of the HV power supply provides the difference signal MO+ and MO-whose potential difference ranges from approximately 3.1 volts to approximately 5.3 volts . The output of the HV power supply is not constant over temperature , so the monitored voltage must be compared with a table of HV output voltages over temperature to determine the actual output voltage of the high voltage supply .

The conditioning circuitry for the HV monitor signal consists of an instrumentation amplifier (U9) whose gain and offset can be modified by signal CA3 from the PDO port on the SOR IC.

When signal CA3 is low (0 volts ), the transistor-inverter Ql turns off resulting in +12 volts on the gate of Q2. Because there is no way for the drain of Q2 to go higher than 6 volts, the voltage between the gate and drainof Q2 is always higher than -2 volts (threshold voltage ), resulting in Q2 turning on.The resulting transfer function is:

Vout = [(MO+)-(MO-) ]*R26*[1/R23+1/R25+1/R26]

-6*R26/R23

Vout = (2.277)*{[(MO+)-(MO-) ] - 3.1} (VOLTS}

This transfer function in effect 'stretches' the HV monitor signal out by subtracting an offset of 3.1 volts and amplifying the

resulting signal by a factor of 2.277 (V/V) . This allows a more accurate determination of the output voltage of the HV power supply.The input range actually covered by theinstrumentation amp actually exceeds the input range expected.It was designed this way to compensate for component tolerances, aging and to allow ·measurement of potentially anomalous HV monitor signals. A table of input voltages to port 6 of the analog multiplexer follows:

HV MONITOR (MO+)-(MO-)

3.14.25.3

Vout02.5

5

When signal CA3 is high (+5 volts), the transistor-inverter Ql turns on. This draws down the voltage on the collector and thus the voltage on the gate of MOSFET-switch (Q2) to about O volts . When Q2 is turned off, the voltage on the drain of Q2 is set by resistor divider R23 and R25 at about 5.5 volts . This makes the gate to drain voltage of Q2 about -4.5 volts. The threshold voltage of Q2 is 2 volts (maximum) , so Q2 will turn off.This configures the instrumentation amplifier to have a gain of 1 (unity) and noadded offset. Thus, the voltage input to port 6 of the analog multiplexer with signal CA3 high is between MO+ and MO- ranges between 3 .1 volts and 5 volts .

8. ANALOG GROUND

The only other input to the analog multiplexer is analog ground . This is fed to port 7 of the analog multiplexer . This is anunused port as it will always read o voltsbecause the analog to digital converter uses analog ground for its ground reference.

Now that the conditioning circuitry has been discussed, other subsystems will be discussed. The three selecting lines for the analog multiplexer (U3) are signals CAO through CA2 from the PDO port of the SDR IC. The selected analog channel is fed to the analog to digital converter via the COM/IO port of the analog multiplexer .

The analog to digital converter (US) is configured so that its output data bus is

never tri-stated (the latest conversion is always available). It receives a 5 volt reference from the 5 volt reference IC (U4) . The signal to start an analog to digital conversion is from the New Data Ready flag for the PDO port of the SDR (NDRO' ). On the rising edge of the NDRO' signal (its trailing edge), the ADC conversion begins. It is completed after 730 microseconds (maximum) .Since the clock frequency at which the SDX and SDR communicat e is only 2KHz, the analog to digital conversion is available long before a command to read the ADC could occur.

Following is a summary of commands that can be sent to the housekeeping circuit, the responses to the commands and command sequences to accomplish various tasks.

COMMANDS TO THE CA PORT (PDQ PORT ON SDR IC)

RETURNEDINPT TO SDX

.----o:::=F=--cc=Ax -

MEANING OF ABOVE ABBREVIATIONS:

ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC DC DC DC

OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT

ADC

CMD # = COMMAND NUMBER FOR REFERENCING THE COMMAND. CAx PDO OUTPUT SIGNALS ON HOUSEKEEPING BOARD NDF = NEW DATA FLAG. INDICATES WRITE TO PDO PORT.NDRO' = NEW DATA READY STROBE FOR THE PDO PORT ON THE SDRSTART? = YES, IF AN ANALOG TO DIGITAL CONVERSION IS

STARTED BY THIS COMMAND (NDRO' TOGGLING STARTS ADC) .

ADC INPTHVmo GAIN

SOX RET. DATA

= ANALOG INPUT TO ADC SELECTED BY THE COMMAND .= GAIN OF THE INSTRUMENTATION AMPLIFIER.= DATA TRANSMITTED BY THE SDR BACK TO THE MOXE DIGITAL ELECTRONICS SOX IC. 'STATE OF CAx' MEANS SETTINGS ON PDQ SENT TO SDX. 'PREV ADC OUTPUT' MEANS ADC OUTPUT FROM A PREVIOUS COMMAND SENT.

CMD-#- 012345

.6.,I

89

CA3)(

0000000011

CA2)(

0000111100

CAl)(

0011001100

CAO)(

0101010101

NDF()1111111111

BS

00000000000

NORD'

1CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK

ADC START?NO YES YES YES YES YES YES YES YES YES YES

ADC DATA

PREV STATE+12V PREV+6V PREV+5V PREV-12V PREV-6V PREV TEMP PREV HVmo PREVAGND PREV+12V PREV+6V PREV

1112

11

00

11

01

11

00

CLK CLK

YES YES

+5V PREV-12V PREV

13 1 1 0 0 1 CLK YES -6V PREV14 115 116 1

111

011

101

111

CLK CLK CLK

YES YES YES

TEMPHVmo AGND

PREV A PREV

BS = ALWAYS O FOR ABOVE TABLE. INDICATES SOX WANTS TO TALK TO PORT PDO.

COMMANDS TO THE CB PORT (PDB PORT ON SDR IC)

CMD IN C7 CB6. NDF BS NDRl' HV INTO HV HV DATA

RETURNED# TI .CBO STAT OUT MON TO SDX 17- 0 ){ xx () 1 1 PREV PREV PREV PREV STATE OF CBx

PREV ADC OUTPUT

MEANING OF ABOVE ABBREVIATIONS:INTI = SIGNAL FROM OVEREXPOSURE SENSOR (ASSERTED HIGH) C7= MSB OF PDB PORT ON SDR

CB6..CBO = BITS ON PDB PORT ON SDR. <V> IS THE DECIMAL REPRESENTATION OF THE VALUE ON THE BITS.

NDRl' = HV STAT =

INTO = HV OUT =

HV MON =

BS

NEW DATA READY FLAG FOR PDB PORT ON THE SDR STATUS OF HIGH VOLTAGE POWER SUPPLY (ON/OFF) INTERRUPT SIGNAL TO MOXE DIGITAL ELECTRONICS VOLTAGE OUTPUT OF HV SUPPLY. *1 INDICATES THAT THEVOLTAGE WILL BE APPX <V>*20+2100 (VOLTS). SEE TABLE. VOLTAGE MONITOR RETURNED FROM HV SUPPLY . *2 INDICATES THAT THE VOLTAGE WILL BE <V>*l/7/128+3.3 (VOLTS).ALWAYS 1 FOR ABOVE TABLE. INDICATES THAT SDX WANTS TOTALK TO PORT PDB.

COMMAND SEQUENCES

1. SELECT A SIGNAL FOR ADC CONVERSION AND READ ITA. Send one of the commands numbered 1 through 16 after

finding signal of interest (in the 'ADC INPT ' column) and the gain on the instrumentation amp. of interest (if HV monitor is selected as the input signal) .

B. OPTIONALLY : Send command number O to verify the analog multiplexer and instrumentation amplifier mode.

c. Send a command for a new signal of interest andinstrumentation amp. mode (one of commands 1 through 16). The data that will be read back by the SDX after the command will be the results of the analog to digital conversion on the signal selected in step A above.

2. HIGH VOLTAGE OFFA . Send command number 19 to turn off HV supply . B. OPTIONS :

1. Send command number 17 to verify that HV supply was commanded off.

2. Send command sequence 1 above for HV monitor signal (commands 7 or 15) to verify HV supply turned off.

3. HIGH VOLTAGE ONA. Send command number 20 with CBO ..CB6 set to the

voltage desired to turn on HV supply.

1819

10

x0

xx xxx1

11

xCLK

OFF OFF

1PREV

00

00

NONE

20 0 1 <V> 1 1 CLK ON 0 *1 *2 PREV ADC OUTPUT

B. OPTIONS:1. Send command number 17 to verify that the HV

supply turned on and that the settings are as desired .

2. send command sequence 1 above for HV monitor signal (commands 7 or 15) to verify HV supply was set to the desired voltage.

MOXE ANALOG/DIGITAL ELECTRONICS INTERFACE DOCUMENT

2/14/91

HOUSEKEEPING MODULE

1. The SDR chip bi-directional port shall be configured as an output port. So configured, the SDR chip shall consist of two 8-bit command latches and one 8-bit data latch.

2. The two command latches shall be designated as CA and CB. The New Data Ready on port O (NDRO) strobe is associated with the CA latch. The New Data Ready on port 1 (NDRl) strobe is associated with the CB latch. Command data is valid on the leading edge of the NDR strobe and is stable on the trailing edge of strobe pulse .

3. Command bits CAO, CAl and CA2 control the select inputs of the analog multiplexer which routes the housekeeping signals to the ADC. Strobe NDRO starts the ADC conversion on it's positive going edge (trailing edge). AFter approximately 100 microseconds, the ADC data is presented to the input latch of the SDR circuit for transmission back to the digital electronics for inclusion in the telemetry.

4. Command CA3 allows the HV Mon operational amplifier to operate in either unity gain or normalized gain for o to 5 volt output . Bits CA4, CA5, CA6 and CA7 are not used.

5. The multiplexer commands will enable the analog signals to be monitored in the following manner :

0 0 l x SELECT +6V FOR ADC0 1 0 x SELECT +5V FOR ADC

0 1 1 x SELECT -12V FOR ADC1 0 0 x SELECT -6V FOR ADC1 0 1 x SELECT TEMP . FOR ADC1 1 0 0 SELECT HVMON FOR ADC 1 1 1 1

CAO CAl CA2 CA3 SIGNAL

0 0 0 x SELECT +12V FOR

NEW COMMANDING SCHEME FOR THE MOXE HOUSEKEEPING BOARD

3/12/ 92FILE = HSKPGC

The following describes changes in the housekeeping board design.

1. COMMANDING THE ELECTROMETER ENABLE

The electrometer in the new housekeeping board will be enabled by commanding bit 4 (CA4) of port o to logiclow. In the old design it was enabled with a logic high.

2 . COMMANDING THE HIGH VOLTAGE POWER SUPPLY

The new circuit to turn the high voltage on consists of a flip-flop and control logic .

A. The Q output of the flip flop generates the ON/OFF signal to the HV supply.

B. The User commands HV on or off using the same command in the previous design (i.e. commanding the high bit (C7) of port 1 high or low, respectively) .

c. The CLEAR- input of the flip flop is generated by NOR gates which implement the logic function:

CLEAR- = RST*(INTI- + CA4)

The '-' following the signal name indicates logic inversion. The truth table for this function is as follows :

INTI I CA4 I RST I I CLEAR- I EXPLANATION-- -- --- -------------------------------- ---------------------

From the table you can see that HV is turned off at power on to the housekeeping board and when the electrometer is enabled AND asserted.

00

00

01

01

TURN ON RESET.-ELECTR. ENABLED, NOT ASSERT D

0 1 0 0 TURN ON RESET0 1 1 1 ELECTR. NOT ENABLED OR ASSERTED1 0 0 0 TURN ON RESET1 0 1 0 ELECTR. ENABLED & ASSERTED1 1 0 0 TURN ON RESET1 1 1 1 ELECTR. NOT ENABLED, IS ASSERTED

3. GENERATION OF ELECTROMETER INTERRUPT SIGNAL :

The new circuit toenerate an interrupt to the 8086 board (INTO signal) consists of a flip flop and control circuitry.

A. The INTO signal is cleared to logic LOW when:

1. A write is issued to port 1 of the SDR IC (i.e. the High voltage control port).

2. Power to the housekeeping board is turned on and the RST signal is asserted low, clearing the flip-flop via the CLEAR- input to the flip-flop.

B. NOR and NAND logic are used to implement turn on SET- input to the INTO flip-flop. The signals consist of the function:

SET- = INTI- + CA4 + RST-

The truth table for this circuit is the following:

INTI I CA4 I RST I I SET- I EXPLANATION0 0 0 1 ELECTR. ENABLED, NOT ASSERTED0 0 1 1 ELECTR. ENABLED, NOT ASSERTED0 1 0 1 ELECTR .NOT ENABLED0 1 1 1 ELECTR .NOT ENABLED1 0 0 1 ELECTR .ENABLED & ASSERTED , RST 1 0 1 0 ELECTR. ENABLED & ASSERTED, NO 1 1 0 1 ELECTR. NOT ENABLED1 1 1 1 ELECTR . NOT ENABLED

4. INSTRUMENTATION AMP COMMANDING:

The instrumentation amp is no longer commandable. The instrumentation amplifier has been replaced by aunity gain differential op-amp circuit.

5. COMMANDING THE PULSER

The pulser circuit consists of logic to allow a single pulse or a train of pulses to be sent to the detector. The two signals CA3 and CA5 from port O of the SDR IC are used for commanding the pulser circuitry. Analog circuitry is used to generating a fast rising and slow decaying pulse for the detector from a digital pulse signal. The digital pulse signal is generated by the following logic function:

PULSE = CA3- * (CA5 + CCLK)

The truth table for this function is as follows:

CA3 I CAS I CCLK I I PULSE I EXPLANATION0 0 0 0 PULSE ENABLED, CLOCK ENABLED0 0 1 1 PULSE ENABLED, ENABLED0 1 0 1 PULSE ENABLED, CLOCK DISABLED0 1 1 1 PULSE ENABLED, CLOCK DISABLED1 0 0 0 PULSE DISABLED1 0 1 0 PULSE DISABLED11

11

01

00

PULSE

DISABLED DISABLE

0 0 CLK CLK PULSE ENABLED, CLOCK ENABLED0 1 CLK 1 PULSE ENABLED, CLOCK DISABLED1 0 CLK 0 PULSE DISABLED1 1 CLK 0 PULSE DISABLED

The commands for the pulsing mode desired are as

follows : A. Single pulse mode:

1. Send command to housekeeping board to set CA3 to logic LOW and CA5 to logic HIGH. This forces the PULSE signal to be logic HIGH regardless of the logic level of the CCLK signal . •

2. Send command to housekeeping board to set CAJ to logic HIGH. This forces the PULSE signal to be logic LOW regardless of the logic level of CA5 or the CCLK signal. NOTE that a logic HIGH to LOW transition at the input to the analog circuitry generates a pulse.

B. Multiple pulse mode :

Send command to housekeeping board to set CA3 and CA5 both to logic LOW . This allows the CCLK signal to drive the analog circuitry.