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System Aspects of ADC Design. SHANTHI PAVAN Assistant Professor Department of Electrical Engineering Indian Institute of Technology, Madras. Prakash Easwaran, C Srinivasan Cosmic Circuits. 05/18/01 V4.3. A-to-D Converters Terminology & Architectures. 05/18/01 V4.3. - PowerPoint PPT Presentation
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System Aspects of ADC Design
SHANTHI PAVAN
Assistant Professor
Department of Electrical Engineering
Indian Institute of Technology, Madras
05/18/01 V4.3
Prakash Easwaran, C Srinivasan
Cosmic Circuits
A-to-D Converters Terminology & Architectures
05/18/01 V4.3
PRESENTATION OVERVIEW
• ADC System Overview
• ADC Metrics
• Flash & Folding Converters
• Two Step Flash Converters
• Pipeline & Delta-Sigma ADCs
• Power efficiency of ADCs
• Conclusions
A GENERIC MIXED-SIGNAL SYSTEM
THE A-D CONVERSION PROCESS
• Anti-alias filter limits input bandwidth to fs/2
ADC OPERATIONS : SAMPLING
• Input typically stored
as charge on a
capacitor
• Tracking bandwidth
• Aperture
• Hold pedestal
QUANTIZER BASICS
• Quant. error assumptions– uniformly distributed– uncorrelated with input !– white !
][2
,2
eq
12
22 eq
0eq
OFFSET ERROR
• Benign when relative accuracy is desired
- Cancelled digitally
Ideal
Actual
GAIN ERROR
• Benign when relative accuracy is desired
-Correct using AGC- in the analog/digital domains
Ideal
Actual
DIFFERENTIAL NONLINEARITY (DNL)
• Nonmonotonicity & missing codes • Monotonic if |DNL| <
INTEGRAL NONLINEARITY (INL)
• Measures deviation from a line• |INL| < 0.5 sufficient condition for a monotonic characteristic
DNL & INL REMARKS
• DNL & INL should be measured with the best fit line
for good repeatability
• DNL - picture of local variations in quantizer
thresholds
• INL - picture of long range variations in quantizer
thresholds
DYNAMIC PERFORMANCE METRICS
• Signal to Noise Ratio (SNR)– Signal to quantization noise
• (6N + 1.76) dB for a sine wave • 1/2 the step size means ¼ the noise power
• Signal to Noise + Distortion Ratio (SNDR)– Signal to everything else
• Spurious Free Dynamic Range (SFDR)– Signal to the largest spectral spur
• Effective Number of Bits (ENOB)–
02.6
76.1SNDR
SPURIOUS-FREE DYNAMIC RANGE
Input Tone
Quantization Noise
HARMONIC DISTORTION
Distortion is related to INL
SFDR DEPENDENCE ON “N”
• Amplitude is • Frequency ~ f
• Amplitude is • Frequency ~ 2f
¼ the power over twice as many harmonicsPeak harmonic goes down by ¼ ½ = 9 dB SFDR ~ 9N dB
FLASH A-D CONVERSION
• (+) Parallel technique - low latency
• (+) References – resistor ladder
• (-) Complexity - O(2N)
• (-) Excessive power/area for N > 6
THE CLOCK SKEW ISSUE
• Sampling is distributed
• Problem : Clock skew causes different comparators to sample inputs at different instances
• Result : Poor performance at high input frequencies
• Solution : Make all comparator inputs see “held” inputs
PRACTICAL FLASH ADC
• T/H for good
dynamic
performance.
• Offset correction
in comparators.
BACKEND LOGIC
THE FOLDING ADC PRINCIPLE
• Motivation : Reduce latches & back end logic
WHITHER FLASH & FOLDING ?
• Disk drive read-channels• Low precision (6 bits)• Very high speed (Gbps)• Need very low latency (for timing recovery)
TWO STEP FLASH ADC
• Motivation: – Reduce number of comparators in a flash ADC
• Idea:– In a flash ADC, only comparators “near” the input give useful information– Use a coarse ADC to estimate where the signal is, then use a fine ADC placed “around” the coarse estimate for better accuracy
TWO STEP FLASH ADC
• Number of comparators : (2Nc + 2Nf – 2) • Resolution Nc + Nf bits• ADCs & DAC must be good to (Nc + Nf) bits
RESIDUE PLOT : A CLOSER LOOK
Slope = 1 ADC thresholds
Code : -2 -1 0 1
RESIDUE PLOT : A CLOSER LOOK
Code : -2 -1 0 1
DAC LSB
]DAC )5.0(Code [ V V LSBADCinr
]DAC )5.0(Code [ V V LSBADCrin
ISSUE : ADC THRESHOLD OFFSET
Fine ADC Range
Fine ADC overload !
ADC THRESHOLD OFFSET : FIX
• Extend the range of fine ADC by adding extra levels• Redundancy in fine ADC relaxes coarse ADC errors• Often called “Digital Error Correction”
ISSUE : DAC INACCURACY
)](DAC )5.0(Code [ V V LSBADCinr
Slope = 1 DAC level error
Fine ADC range not exercised
• DAC level too small : Missing codes• DAC level too large : Non-monotonicity
TWO-STEP FLASH SUMMARY
• Example : – 10-bit flash needs 1023 comparators– (5 + 5) bit 2-step flash needs only 62 comparators
• Lower hardware compared to a flash
• More latency (2 conversions, pipelined)
• Used for ~8-10 bit resolutions
• Coarse ADC resolution can be poor if extra levels are used in
the fine ADC
• DAC must be accurate to the resolution of the entire ADC
IMPROVED TWO-STEP FLASH ADC
• The fine ADC operates on a small input– Offset requirements for the fine ADC can be relaxed if the
input signal swing was larger– Amplify the input to the fine ADC
PIPELINE ADC PRINCIPLE
Recursive implementation of the fine ADC
PIPELINE ADC PRINCIPLE
• Nc bits per stage
• Issue with ADC threshold error
- Digital error correction • DAC & Interstage amplifier implemented with
switch-capacitor circuitry
STAGE 1 STAGE 2
OVERSAMPLING A-D CONVERSION
Oversampling ADC
)(2/
OSRRationgOversamplif
f
s
sig
Signal
Quantization Noise
Nyquist rate ADC
OVERSAMPLING & NOISE SHAPING IDEA
• Quantization noise is pushed out of the signal band• Digital filter required to eliminate out of band noise• Very high SQNR possible with a poor quantizer• Also referred to as ADCs
MODULATOR BLOCK DIAGRAM
• Discrete time input & output• Quantization modeled as additive noise
MODULATOR BLOCK DIAGRAM
Noise Transfer Fn. (NTF)Signal Transfer Fn. (STF)
)()(1
1)(
1)(
)()( zE
zLzV
zL
zLzV inout
Make L(z) large in the signal band
DELTA-SIGMA WAVEFORM EXAMPLE
Analog Input
Quantizer Output
OUTPUT SPECTRUM
Signal Bandwidth
Signal Tone
Shaped Quantization Noise
OTHER LOW SPEED ARCHITECTURES
• Algorithmic ADCs– Reuse a single stage of the pipeline
• Successive Approximation ADCs
• Dual-slope ADCs
HIGH SPEED : “SYSTEM” IDEAS
• Time – interleaving
multiple ADCs– N slow converters to
get one fast ADC– Sample and hold of
each converter must be good up to fs/2
– Gain & Offset mismatch– N times speed for N
times power
ADC FIGURE OF MERIT
• FOM Units : Joules per level resolved
• Small FOM means more power efficiency
• Higher speed – more power
• Higher resolution – more power
• ENOB : Effective number of bits for a Nyquist input
sfENOB2
Power FOM
FIGURE OF MERIT : COMMENTS
• For the same ADC spec, FOM usually improves with
technology (& skill of the designer !)
• Ponder this : If “X” can design a 10-bit 500 Msps ADC in a
certain process with 400 mW, does this mean that he/she can
design a 10-bit, 1Gsps ADC with 800 mW ?
sfENOB2
Power FOM
POWER EFFICIENCY OF ADCs
• Flash ADCs are least efficient– But unavoidable when latency cannot be
tolerated
• Pipelines more efficient than a flash– Reduced hardware at the expense of
latency
• Delta-Sigma more efficient than a pipeline– but only suitable for low bandwidth signals
REFERENCES
• M. Gustavsson, J. Wikner & N. Tan, “CMOS Data Converters for Communications”, Kluwer, 2000
• R. van de Plassche, “Integrated Analog-to-Digital & Digital-to-Analog Converters”, Kluwer, 1994
• R. Schreier, S. Norsworthy & G. Temes, “ Delta-Sigma Data Converters – Principles, Design & Applications”, Wiley, 1998
A-to-D Converters Specifications from
System Aspects
05/18/01 V4.3
ADC Parameters
• Sampling Frequency
• Resolution
• SFDR
• Input Bandwidth
• Latency
System Aspects…
• Signal Bandwidth
• System SNR requirements
• Signal characteristics– Dynamic Range– Interferers present– Single/Multi Carrier
Typical Real world signals
ADC requirements derived from Strengths of the Signal
and interferers.
-114dBm Noise
-104dBm
-14dBm
-40dBm
Blocker
Weak Signal
Sampling Frequency
Filters: DSL
30KHz 130KHz 1.1MHz
Upstream Downstream
FDM filters: Filters to filter-off the local-echo in a Frequency-Division-Multiplexed system
Filtering: Wireless signals
Filter to remove adjacent channel and other interferers.
-114dBm Noise
-104dBm
-40dBm
Weak Signal
Sampling Freq - Filtering
• Ideal anti-aliasing filter placed before an ADC – infinite attenuation for frequencies above
the cutoff frequency.
– sampling at fs=2fmax with no aliasing
• Very High order filters
– Typically > 8th order filters !!
High order filter
• High sensitivity, tougher to implement
• Process variation: requires calibration of filter
• High Power and Silicon area
• Non-linear phase response
• Effective solution is digital filters for anti-aliasing.
Receive channel
• Oversample the ADC– Simpler Lower order Analog filter– Anti aliasing done by the digital filter
• Filter –ADC complexity trade off
• ADC up in the signal chain– Signal processing in Digital domain
ADC
Digital filter Analog Filter ReceiverA/D Converter
Resolution
Resolution Specs
• SNR requirement
• Dynamic range of the input signal
• Signal characteristics:– Peak to Average (crest factor)
• Interferers present
ADC Requirement for DSL
SNR for QAM Modulation
(3dB/bit; 15 bits)
45dB
Crest Factor for clipping < 10-8 15dB
Dynamic Range lost due to Echo 0dB
Margin from ADC 10dB
70dB
System optimisation
Filter - ADC trade off
-114dBm Noise
-40dBm
Weak Signal
-90dBm
• Interferer higher power than the signal.
• For the signal to use the dynamic range of the ADC– Sufficient attenuation of the interferer ( < signal power)– AGC to gain the signal post filtering
• High order filter
-114dBm Noise
-40dBm
-90dBm
Filter - ADC trade off
-114dBm Noise
-40dBm
Weak Signal
-90dBm
• Trade off between filter order and dynamic range lost
in the ADC
-114dBm Noise
-40dBm
Weak Signal
-90dBm
SFDR
SFDR
• Caused by Harmonics and Intermodulation
products
SFDR
• Important parameter when digitizing
broadband multicarrier signals
• Desired signal then is obtained by using a
narrowband digital bandpass filter
• The SNR is improved by this digital-filtering
process – Advantage of oversampling
SFDR Performance of the ADC
• a spurious component may fall within the bandwidth of the digital filter
• SFDR: noise added in-band– does not improve with digital-filtering.
• SFDR spec > than the SNR after the digital filtering
• Example: 15b 65MSPS ADC with – SNR = 73dB– SFDR = 85dB
Frequency
Power
Spectrum
Missing Tone Test
180KHz 1104KHz
SFDR in a multi-tone system (DSL)
Input Bandwidth
• Critical parameter for systems that use
undersampling.
• Direct sampling of the IF signal in a wireless
system– Eg: 14b 125MSPS ADC sampling a
200MHz IF
• Jitter performance of the sampling clock for
this high input frequency..
Latency
• systems that use the ADC in control loops
• In communications– ADC used for AGC, power control
ADC: Bits vs. Speed Chart
5 10 15 20
1MHz
10MHz
100MHz
500MHz
1GHz
AD
C S
pee
d
Resolution (Bits)
Flash/Folding
Pipeline
Sigma-Delta
Basestations, Graphics
WLAN, DSL
Bluetooth
UWB, Disk Drives, Instrumentation
Pipelined A/D Converters
PIPELINE ADC PRINCIPLE - RECAP
Advances in ADC Speed
ADC Speed for 14-bit Resolution
100
150
200
2002 2003 2005
Year
Sp
eed
(M
SP
S)
• ADC speed increase driven by desire to bring ADC closer to antenna
Advances in Power Dissipation
ADC Power for 14-bit 105MSPS ADC
0
500
1000
1500
2000
2002 2004 2005
Year
Po
wer
(m
W)
• ADC power reduction driven by portability, SOC integration
• Near 2X reduction every 18 months
Continuous-time A/D Converters
C-T ADC: BASICS
• Architecture trades off speed for resolution; Ideal for applications where signal bandwidth is relatively small (example: Bluetooth, DSL, DVB-H)
• Signal sampled by the internal ADC free anti-alias filtering by the loop filter
• Important limitations are SNR degradation due to clock jitter (DAC) and stability concerns in higher-order loops due to excess delay (loop filter + internal quantizer)
ADCLoop Filter
H(s)
DAC
gm
vin bits
Advances in Power Dissipation
ADC Power for 12-bit ADC
0
50
100
150
2003 2005
Year
Po
wer
(m
W)
BW=40MHz; 74dB SNR
BW=10MHz; 67dB SNR
• Significant advances in the last two years; 4X improvement in speed, 5X reduction in power dissipation