Tutorial: Key Design and Application for Testing SoC & … · Tutorial: Key Design and Application ... Data Converter Architecture: Delta-Sigma ADC ADC Architectures. ... SAR ADC

Tutorial: Key Design and Application for Testing SoC & SiP AC Interface

Jin-Soo KoTeradyne Inc.

[email protected]

2009-06-24

mailto:[email protected]

Jin-Soo Ko 2009-6-24

Agenda

• SoC/SiP/PoP • Architecture and Packaging Introduction

• AC Interface: Data Converter • Architecture and Design

• AC Interface Design• Power, Ground, and Reference• Clock Source and Jitter • Signal Capture• Signal Source


Low Cost Device Design

• New communication and application-processing architecture and the Game, Medical, and Automotive control markets drive new technology• Integrate Memory, Analog, RF• Need to reduce the number of components

• Solutions:• System on Chip (SoC)• System in package integration (SiP)

Stacked Die Solution• Package-on-package integration (PoP)

The Stacked Package Solution


SoC/SiP: Reducing Cost

Memory2003 2005One Chip SoC & Memory only


SiP: Stacked Die


SiP: Stacked Die ExampleBlackBerry


SiP: iPhone PoP Technology

PoP technology: adds seriously large amounts of memory:iPhone Processor (Samsung S5L8xxx)

• First PoP• Copackaged 1Gbit DRAM die (commodity DRAM)

+ a processor (Integrates about 1.2M of e-DRAM along withabout 375K of more traditional SRAMSoC memory)

• Uses two independently packaged devices andstacks them.

• 1.3mm high (not including solder ball height atsystem PCB interface)

• 90 nm technology + a camera and the image sensor module• Advantages:

• Allows package and test of cheap commodity DRAM independent of more valuable high performance logic IC.

• Creates flexibility in test programs and allows a kind of “final” test on each packaged device before marrying them into the system-in-package (SiP)

• Big manufacturing cost advantage• Low profile package and a very small price

http://www.semiconductorblog.com/wp-content/uploads/2007/10/iphone-pro-package.png


SoC: PS2 Embedded Memory

Graphics chips in game systems that have started using embedded DRAM:

Device: Sony PlayStation 2 (PS2) and Microsoft Xbox 360Technology: 90 nm process split in commodity DRAM,

uses capacitors formed by trenches in the substrate (“trench” DRAM) or the capacitors above the substrate surface (“stack” DRAM).

SONY PS2 “EmotionEngine + GraphicsSynthesizer” SoC chipFabricated using Sony’s ASC9 process includes 72 Mb of embedded DRAM


SoC: Full HD 1080P DTV and AC


SoC: Sensor for Game, Medical & Automotive


SoC: Sensor Input Stage Design


Data Converter and SoC interface

Digital Analog


DAC Architectures

Data Converter Architecture: Simple DAC Design

R-2R ladder DAC determines the analog signal by- R-2R network connection to +Vref or -Vref- Summing amplifier operation by RF and R-2R network - Thevenin analysis


Flash Converter – Compare Ain with 2**N-1 comparators and decoding- Fast conversion- Low resolution

Data Converter Architecture: Flash Converter

DAC Architectures


Delta-Sigma (ΔΣ) converters determine the digital word by - Oversampling- Digital filtering and Decimation

Data Converter Architecture: Delta-Sigma ADC

ADC Architectures


Multi-order Delta-Sigma (ΔΣ) modulator and the noise shaping results

Data Converter Architecture: Modulator

ADC Architectures


Delta-Sigma (ΔΣ) Digital Filter and high frequency noise reduction

Data Converter Architecture: Digital Filter

ADC Architectures


Delta-Sigma (ΔΣ) Digital Filter output and Decimation (Averager)

Data Converter Architecture: Decimation

ADC Architectures

Next


Delta-Sigma (ΔΣ) Decimation function and pickup and dump


ADC Architectures


Delta-Sigma (ΔΣ) Decimation by 4 frequency domain


ADC Architectures


DAC Architectures

Data Converter Architecture:Delta-Sigma (ΔΣ) DAC

Delta-Sigma (ΔΣ) 1 Bit DAC determines the PWM bitstream by- Digital Delta-Sigma (ΔΣ) modulator- 64 time oversampling for Audio signal- Get analog signal by low-pass filtering 64 x 48 kHz = 3072 kHz

Class D amplifier using Delta-Sigma (ΔΣ) PWM


SARs determine the digital word by- Sampling the input signal- Using an iterative process

Data Converter Architecture: SAR ADC

ADC Architectures


Rin 10Kohm, Cin 0, and check the chargingcurrent effect by the ADC S/H

Needs Buffer and charging Cap Cin.

Data Converter Architecture: SAR ADC Front End

ADC Architectures


Pipeline converter determine digital word by- Undersampling- With Sample/Gain Algorithm Topology- Multiple stages/Large Cycle-latency

Data Converter Architecture: Pipeline ADC

ADC Architectures


DAC Architectures

Data Converter Architecture: IDAC

-Current steering DAC determine the analog signal by- Multi-different current source combination - High speed switching


DAC Architectures

Data Converter Architecture: IDAC Source

-Current steering DAC Current source stage


Data Converter Application

Low noise High performance Data Converter application design


• General ADC Test Application Diagram

ADC

OVDD-Digital I/O power

AVDD-AC Power

DVDD-Digital Power

Reference

Power sourceDC30HDVS

LDO out

Buffer DSSC

ClockGND

Signal Synthesizer

Power Source assignment•Isolated analog power supply with Digital power supply by LC filer•Or use separate power source with decoupling caps and ferrite core•Separate AVDD and DVDD with the digital output interface supply OVDD –high power driver•Very low noise and fast slew power source for testing high precision 18-24 bit converters

Decoupling Capacitor application• Bulk capacitance at entry of power to PCB• 10 µF evenly distributed across the PCB• 1 µF close to the device • Use 0.01 µF to 100 pF as you get to the chip• Mix values of 0.068 µF to 0.001 µF, also for lower pF values

Power: Converter Power Pin Application


AGND DGND

System MECCA

DC-DCConv

AC Power

AC DIGITAL

- 60/50 Hz AC power noise capture on the AC and Digital separated ground plane

60Hz 180Hz120Hz

Ground: Low Noise Ground Plane Design

• Single or Separate Ground plane?- Separated ground plane will capture AC or switching power supply noises- Ground noise is directly coupled to converter input and output signal


Ground: FLEX DIB Noise Floor Measure

60 dB Offset

Actual FLEX DIB noise floor

• FLEX system noise floor

AGND DGND

System MECA

DC-DCConv

AC Power

PGA202 G=1000

BBAC Cap

GND

BBAC Cap


• Low noise data bit grounding

Ground: Separate the Data Bit Control GND


Reference: Low Noise Ref Source Design

• Use DC Reference device• Need very stable and low drift DC source• Decoupling between REF and REFGND using ESR

tantalum capacitor with minimum parasitic inductance• Use programmable DC Ref module or use external fixed

voltage reference• Use reference buffer for sharing the reference level to

other converters • Good external reference source improves converter

SNR performance 0.5 - 2.0 dB


DC Reference Module output over 2 hours

minutes

ΔV Output

Need >30 min the module warm-up time for proper level driving.Measuring the data converter accurately requires a stable external reference source

<7 µVpp drift/2 hrs

• Teradyne Reference source module level drift and settling time

Reference: Low Drift Ref. Source Module


Clock Jitter and Signal• Clock jitter and Signal

Output

Time

Analog signal

Distribution of sampled

signal

Equivalent noise = 2πFanalog tjmrs

Clock jitter distribution

Slope = πFanalog

Jitter amplitude = tjmrs

- Low jitter PicoClock spectrum

- High jitter clock spectrum


Theoretical Jitter to ENOB Table

Clock Jitter: SNR and Tj Calculation• Theoretical Minimum Jitter for ENOB ‘N’

Tj = 10 /(2*π*Fi)SNRideal/20

SNRideal = -(6.02 * N + 1.76) dB

Tj: RMS Jitter of Conversion ClockN: Data Converter Bit sizeFi: Conversion Frequency


ADC BufferSignal

SynthesizerDSSC

Clock

PowerUP and Down converter

Optional BPF& Single to diff

converter

Clock Jitter: Low Jitter Source Application

• Clock jitter noise directly coupled to the data converter SNR performance.

• Need low phase and jitter clock source for high performance and high speed data converter testing

• UltraFLEX 100MHz system ref. clock

Clock sourceHSD channelPicoClockSystem reference clockExternal synthesizer

<500 fs jitter clock


AC Signal Capture: Precision DAC

• High performance 24 bit audio DAC signal capture

LPF Embedded


Single GND

AC Signal Capture: 24 Bit DAC

• WM 8740 24 bits

DVDD

DIB LPF

Filtering Options

Turbo ACNotchFilter

AVDD

HDVS or DC30AVDD 5V

•Power: Separate Analog and Digital power•Ground: Single GND for the all device ground pins•Data and Clock source: Low jitter performance•LPF for output signal noise cutoff & embedded LPF•Notch filter and gain amp. to increase capture dynamic range•AC Capture, DSP, and Sync-Link for DUT limited time-only test

Serial 24 Bits

DSSC HSD

HSD Clock

8740 DAC

HDVS or DC30DVDD 5 V

Sync-Link™

DC

Instrument

AC Instrument

DSPEngines

DigitalInstrument

BBACCapture

Background DSP™

WM8740

Single GND


Apply gainApply notch filter at fundamental

Extend Capture Dynamic Range for DAC Test

AC CaptureDACLow Pass

Filter

Raw Capture

AC Capture

Instrument Dynamic Range

Notch Filter

Gain Stage(s)

+-


Single GND

AC Signal Capture: 16 Bit 100 MHz BW DAC

• AD9779 800MSPS

DVDD

DIB LPF

Filtering Options

NotchFilter & 30-50dB

Amp.

AVDD

HDVS or DC30AVDD 5V

•Data and Clock source – Ext Low jitter clock•LPF for output signal noise cutoff & embedded LPF•Notch filter and gain amp. to increase capture dynamic range•AC Capture, DSP, and Sync-Link for DUT limited time-only test

Parallel 16 Bits

DSSC HSD

Ext Clock

9779 DAC

HDVS or DC30DVDD 5 V

Sync-Link™

DC

Instrument

AC Instrument

DSPEngines

DigitalInstrument

VHFACor

GigaDigCapture

Background DSP™


AC Signal Source: Precision ADC Test

• Signal source • Low phase noise signal generation using high performance BPF

or LPF• Turbo AC has filters for sourcing high performance signal

generation• Or use GPIO option and control line for external options.

- Single to Differential converter use highperformance and speed transformer

Signal Synthesizer

ADC under test DSSC

Power

LPF or Band-pass

filter

Single-ended to

differentialGPIO

Signal sourceBBACTurbo ACHDACTODC30HSD channelExternal synthesizer

Clock

Buffer


• Low noise >100 MHz CW signal by BPF

AC Signal Source: Low Noise CW

•BPF: TTE KC8-250M-38M-50-1405

CW

AWG

Ext. Src

Ext. Clk

HSD

PicoClk

BPFDIGCAP

DIGCAP

DUT

TX


AC Signal Source: Dual Tone

• High quality dual tone generation• Improve IMD performance using 2

independent sources• Use combiner + splitter• For Multisite Parallel Testing• No filtering

• Low IMD 250 MHz band dual tone signal generation

CW2

CW1

Splitter

f1

f2f1 f2

f1 f2f1

f2To Site #0

To Site #1

Combiner


Q&A

Jin-Soo Ko

[email protected]

600 Riverpark Drive,North Reading, MA01864 USA

mailto:[email protected]


Notch Results: DAC TestPre-Harm2: -113.368 dB

Notch-Harm2: -116.826 dB

Pre-Harm3: -116.764 dB












THD10 -110.878 dBTHD10(notch) -114.436 dBTHD5 -111.624 dBTHD5(notch) -115.374 dB


Notch Results: Precision DAC Test

~70 dB Attenuation


• 14-bit Converter Clock jitter and noise simulation

10ps20ps

100ps

0ps

Clock Jitter: Clock Jitter Effect Simulation

F(t) = sin [2*PI*Fi*(t+Tj)/Fs], Fi = 2MHz, Clock jitter 0, 10ps, 20ps and 100ps


255 ps rms Clock Jitter

20 ps rms Clock Jitter

• Fi 2MHz, 14 bit ADC noise floor

Clock Jitter: 14 Bit DAC Test Result


AC Signal Capture: Normal DC Power Supply

• AC signal harmonic distortion by DC power setup


AC Signal Capture: High Speed DC Power Supply

• High speed DC regulation reduces harmonics

3rd Harmonic

• Teal – DC30 BW = 500Hz, Pink – DC30 BW = 50K in

Hi-Reg Mode

Documents

Tutorial: Key Design and Application for Testing SoC & … · Tutorial: Key Design and Application ... Data Converter Architecture: Delta-Sigma ADC ADC Architectures. ... SAR ADC