Understanding Design and Operation of Successive ... · PDF fileUnderstanding Design and Operation of Successive Approximation Register ... SAR ADC Different SAR ADC topologies Comparison

Understanding Design and Operation of Successive Approximation Register (SAR) ADC

ECE 614 - Spring ‘08

April 28,2008

By Prashanth Busa

2

Talk Outline

� Various ADC Architectures

� SAR ADC Introduction and Operation

� Charge Redistribution SAR ADC

� Different SAR ADC topologies

� Comparison with other ADCs

� Summary

3

Various ADC Architectures

� Plot of Resolution vs Conversion rate.

� SAR ADCs are available from 8-18 bits resolution with sampling rates up to 5Msps.

� Higher accuracy, low power and used in medium speed/medium-high resolution applications.

Figure from ref [2]

4

SAR ADC History

� First commercial converter, 1954 "DATRAC" 11-Bit, 50-kSPS SAR ADCDesigned by Bernard M. Gordon at EPSCO.

� Today, the state of the art SAR ADC reported is 18 bit, 2Msps fully differential with a single power supply of 2.5v.

5

Successive Approximation ADC

� Implements Binary search algorithm

� Initially, DAC input set to midscale (MSB =1)

� VIN < VDAC , MSB remains 1

� VIN > VDAC , MSB set to 0

� Algorithm is repeated until LSB

� End of algorithm, DAC [input] = ADC [output]

� N cycles required for N-bit conversion

Simplified SAR ADC Architecture

Figure from Maxim semiconductors ref [3]

6

SAR Operation

DAC [in]=ADC [out] =101000

A 6-bit SAR ADC Example, VIN = 5/8 VREF

Start -100000

VDAC = VREF /2

Simplified SAR ADC Architecture

7

SAR Timing diagram

� The positive going edge of CONVST indicates the start of conversion, the input sample and hold is in the hold mode from this edge andvarious bits are determined using SAR algorithm.

� When CONVST goes low the busy signal goes high and the BUSY linegoes low at the end of conversion process.

Figure from Analog Devices, ref[4]

8

A simple Charge Redistribution DAC

Assuming C1=C2

Discharging C1,C2 – S3 and S4 closed

Charging C1 to Vref, C2 grounded

Charge sharing C1,C2 –> V0 = Vref/2

Figures from ref[2]

9

Simple Charge redistribution DAC cont’d

If bit =1, S2 is closed

=0, S3 is closed

Depending on input,

V0 =(Vref/2 + Vref/4) for S2 closed (b=1)

= Vref/4 for S3 closed (b=0)

Figures from ref[2]

10

Charge Redistribution SAR ADC

� Provides inherent T/H operation.� Initially, Sreset is grounded and all the capacitors connected to VIN.� MSB top plate is opened and MSB cap bottom plate connected to VREF

resulting in –VIN + VREF/2 on the input of comparator.� If –VIN + VREF/2 > 0 ,MSB =0 else MSB =1.� Next cycle MSB-1 bit is connected to VREF ,algorithm is repeated until

LSB.

Figure from ref[2]

11

Charge Redistribution SAR ADC Cont’d..

� Comparator offset needs to addressed.� Switch S1 is closed, S2 is grounded, storing the offset voltage across

the capacitor.� Now, Vx > Vos result in Vout going high and Vx < Vos results Vout going

low.� Parasitic capacitance on the top plate is not a concern due to the

presence of global negative feed back.

Comparator Offset Cancellation

12

INL and DNL Calculations

� Linearity of the ADC depends on the capacitor ratio (matching).

� Process should have good capacitors.

� INL is defined as,

|INL|max = 2N-1(C+|∆C|max,INL)- 2N-1 C = 2N-1|∆C|max,INL

� For INL to be less than ½ LSB, maximum ∆C is

|∆C|max,INL= C/2N

� DNL is defined as,

|DNL|max = (2N – 1) |∆C|max,DNL.

� For DNL to be less than ½ LSB, maximum ∆C is

|∆C|max,DNL= C/(2N+1-2).

� MSB capacitor accuracy is more critical in determining the DNL!!

From ref[1]

13

Charge Redistribution SAR Tradeoffs

Advantages:

� Low power dissipation.

� Inherent T/H operation.

� Offset cancellation is incorporated.

� Requirement of less analog circuitry.

Disadvantages:

� Need of good capacitive material.

� Large capacitors, making matching difficult.

� Not inherently monotonic.

14

Other Charge Redistribution topologies

� Resistor DAC for MSBs and Capacitors for LSBs.

� Operation starts by closing SF and charging top plate to VIN - VOS.. Next SF is opened and a search is performed in the resistive divider. Finally bottom plates of capacitors are switched from SA and SB to converge to VOS.

� ADC is inherently monotonic and there will be no missing codes.

SAR hybrid ADC Architecture

Figure from ref [5]

15

SAR ADC Configurations

� A commonly used Figure of merit (FOM) for ADC’s in terms of resolution, bandwidth and power dissipation is given by,

(SNR[dB]-1.78[dB]) Sampling rate10 x ( )

2FOM = power dissipation

� Lower power dissipation gives higher FOM, hence techniques like Switched opamp, reset opamp circuits and boot-strapping techniques have been explored using Successive Approximation ADC’s operating at lower VDDs.

From ref [6]

16

SAR vs other ADCs

� A pipelined ADC introduces latency, consumes more power and takes up more area for same resolution. Also requires calibration for more than 12 bits resolution like SAR.

� Flash ADC is much faster, less accurate and takes more silicon area due to the number of comparators 2N for N bit resolution.

� Oversampled/Σ-∆ ADCs have low conversion rates, high precision, averaging noise and no requirement for trimming or calibration even up to 16 bits of resolution.

� Power dissipation of SAR ADCs vary with the sampling rate unlikeFlash and Pipeline architectures. Hence find applications in PDAs.

17

SAR Summary

� Critical components are DAC and comparator.

� Settling time of DAC must be less than ½ LSB and determines the speed of conversion.

� Accuracy of the DAC is critical since an incorrect decision could result in ending up the value in wrong leg of binary tree.

� Comparator should resolve small differences between VIN and VDAC.

� The clock frequency should be equal to the sampling frequency multiplied by the number of bits.

� SAR ADCs are efficient, easy to understand and ideally suited for modern CMOS processes.

18

References

� [1] R. J. Baker, CMOS Circuit Design, Layout, and Simulation, Revised Second Edition, Wiley-IEEE, 2008

� [2] http://webcast.berkeley.edu/EE 247

� [3] http://www.maxim-ic.com/appnotes.cfm/an_pk/1080

� [4] http://www.analog.com/

� [5] David A. Hodges, Bahram Fotouhi “High-Resoultion A/D conversion in MOS/LSI” IEEE Journal of Solid-State Circuits, vol. SC-14, no 6, December 1979

� [6] R. Thewes J. Sauerbrey, D. Schmitt-Landsiedel “A 0.5-V 1-uW Successive Approximation ADC ” IEEE Journal of Solid-State Circuits, vol. 38,no 7,July 2003

Questions ??

Slide 1

Pipeline ADCPipeline ADC

Bill FilipiakBill Filipiak

ECE 614ECE 614

Slide 2

OverviewOverview

• Basic Operation

• Advantages/Disadvantages

• Ideal/Non-Ideal Switching Points

• INL/DNL

• S/H Design

• 1.5 Bits/Stage

• Summary

Slide 3

Basic OperationBasic Operation

Figure 29.30

Slide 4


Figure 29.30

Subtract VREF/2 if MSB is

high since MSB=VREF/2

Multiply by 2 since the

next stage is worth half

as much (VREF/4)

Subtract VREF/2 if this

bit is high since we

multiplied by 2

Digital Value (2.5V for a 1 and 0 V for a 0) + ½ of the analog

output must always equal the input for each stage

Slide 5


VREF=5V

2.5V 2.5V

2.5V

clk

D2 D1 D0

Adapted from Figure 29.30

Slide 6


VREF=5V

2.5V 2.5V

2.5V

clk

D2 D1 D0

2V2V2V2V 2V2V2V2V

OOOO

2V2V2V2V 4V4V4V4V

Cycle vin Output

1 2V

clk

Cycle=1

Slide 7


VREF=5V

2.5V 2.5V

2.5V

clk

D2 D1 D0

3V3V3V3V 3V3V3V3V

1111

O.5VO.5VO.5VO.5V 1V1V1V1V 4V4V4V4V

1111

1.5V1.5V1.5V1.5V

OOOO

3V3V3V3V

Cycle vin Output

1 2V

2 3V

clk

Cycle=2

Slide 8


VREF=5V

2.5V 2.5V

2.5V

clk

D2 D1 D0

4.5V4.5V4.5V4.5V 4.5V4.5V4.5V4.5V

1111

2V2V2V2V 4V4V4V4V 1V1V1V1V

OOOO

1V1V1V1V

1111

2V2V2V2V

1111

11111111OOOO

Cycle vin Output

1 2V

2 3V

3 4.5V 011

3V3V3V3V

clk

Cycle=3

Slide 9


VREF=5V

2.5V 2.5V

2.5V

clk

D2 D1 D0

4V4V4V4V

1111

1.5V1.5V1.5V1.5V

1111

3V3V3V3V

OOOO

OOOOOOOO1111

Cycle vin Output

1 2V

2 3V

3 4.5V 011

4 100

2V2V2V2V

clk

Cycle=4

Slide 10


VREF=5V

2.5V 2.5V

2.5V

clk

D2 D1 D0

1111

111111111111

Cycle vin Output

1 2V

2 3V

3 4.5V 011

4 100

5 111

3V3V3V3V

clk

Cycle=5

Slide 11

AdvantagesAdvantages

• Low number of comparators (N comparators)

• Flash ADC requires 2N-1 comparators

• Two-step ADC requires 2(2N/2-1) comparators

• High throughput – One conversion is completed

per clock cycle

• Two-step ADC requires two clock cycles per

conversion

Slide 12

DisadvantagesDisadvantages

• Latency of N clock cycles before the ADC

outputs comparison data

• Errors propagate through system since each

stage operates on the residue passed from

previous stage

• Accuracy of most significant stages becomes

more important than downstream stages

Slide 13

Ideal Switching PointIdeal Switching Point

2.5V 2.5V

2.5V

clk

D2 D1 D0

Switches when

REFIN VV2

1=

INVV =1

Slide 14


2.5V 2.5V

2.5V

clk

D2 D1 D0

Switches whenSwitches when

REFIN VV2

1=

INVV =1

REFREFIN VDVV 22

1

4

1+=

−= REFIN VDVV 222

12

Slide 15


2.5V 2.5V

2.5V

clk

D2 D1 D0

Switches when

Switches whenREFREFIN VDVV 2

2

1

4

1+=

−= REFIN VDVV 222

12

REFREFREFIN VVDVDV8

1

4

1

2

112 ++=

−

−= REFREFIN VDVDVV 1232

1

2

122

Switches when

REFIN VV2

1=

INVV =1

Slide 16


• 1st comparator switches when:

• 2nd comparator switches when:

• 3rd comparator switches when:

• Nth comparator switches when:

REFIN VV2

1=

REFREFIN VDVV 22

1

4

1+=

REFREFREFIN VVDVDV8

1

4

1

2

112 ++=

REFNREFNREFNREFNREFNIN VVDVDVDVDV2

1

2

1...

8

1

4

1

2

111321 +++++=

−−−−

Slide 17

QuantizationQuantization

Digital Input Range Input Voltage

Output (VREF=5V)

000 0→0.625V

001 0.625V→1.25V

010 1.25→1.875V

011 1.875→2.5V

100 2.5→3.125V

101 3.125→3.75V

110 3.75→4.375V

111 4.375→5V

REFV8

10 →

REFREF VV4

1

8

1→

REFREFREF VVV8

1

4

1

4

1+→

REFREFREF VVV2

1

8

1

4

1→+

REFREFREF VVV8

1

2

1

2

1+→

REFREFREFREF VVVV4

1

2

1

8

1

2

1+→+

REFREFREFREFREF VVVVV8

1

4

1

2

1

4

1

2

1+→+

REFREFREFREF VVVV →+8

1

4

1

2

1

Slide 18

QuantizationQuantization

0.625 1.25 1.875 2.5 3.125 3.75 4.375 5 vin (V)


Slide 19

NonNon--Ideal Switching PointIdeal Switching Point

2.5V 2.5V

2.5V

clk

D2 D1 D0

Switches when

112

1SOSCOSREFIN VVVV −+=

11 SOSIN VVV +=

Slide 20


2.5V 2.5V

2.5V

clk

D2 D1 D0


112


11 SOSIN VVV +=

( )2212

1

2

1

2

1COSSOSSOSREF

REFIN VV

AVVD

A

VV −−−+=

22122

1SOSREFSOSIN VVDVVAV +

−+=

Slide 21


2.5V 2.5V

2.5V

clk

D2 D1 D0


Switches when

112


11 SOSIN VVV +=

( )2212

1

2

1

2

1COSSOSSOSREF

REFIN VV

AVVD

A

VV −−−+=

22122

1SOSREFSOSIN VVDVVAV +

−+=

−−−−−+= REFCOSSOSSOSSOSREF

REFIN VVA

VA

VA

VA

VDVDV

2

1111

2

1

2

132322112

3122132

1

2

1SOSREFSOSREFSOSIN VVDVVDVVAAV +

−+

−+=

Slide 22


• 1st comparator switches when:

• 2nd comparator switches when:

• 3rd comparator switches when:

• Error from first sample-and-hold propagates through and causes a

larger error at the last stage of the converter

• This analysis only includes major sources of error (sample-and-hold and

comparator)

• It also assumes that the gain of each amplifier is A, although in reality,

each amplifier may have a different gain error

112


( )2212

1

2

1

2

1COSSOSSOSREF

REFIN VV

AVVD

A

VV −−−+=

−−−−−+= REFCOSSOSSOSSOSREF

REFIN VVA

VA

VA

VA

VDVDV

2

1111

2

1

2

132322112

Slide 23

INLINL


0.625 1.25 1.875 2.5 3.125 3.75 4.375 5 vin (V)

Ideal

INL

Slide 24

INLINL

• INL is calculated by subtracting the ideal switching point

from the non-ideal switching point

• For the first stage:

Ideal:

Non-Ideal:

INL:

• For the second stage:

INL:

• For the third stage:

INL:

REFIN VV2

1=

112


111 SOSCOS VVINL −=

( )2212

1

2

11

2COSSOSSOS

REF VVA

VA

VINL −−−

−=

−+−−−−

−=4

11

2

111

2

11

2 23232213A

VV

AV

AVA

VA

VINL REF

COSSOSSOSSOSREF

Slide 25

INLINL

• Worst case addition of offsets must be <1/2 LSB

to be N-bit accurate

• Offsets of later stages are divided by a large

gain so they are less important than the first

stage

• Less accurate designs can be used for later

stages to save power and area

Slide 26

DNLDNL


0.625 1.25 1.875 2.5 3.125 3.75 4.375 5 vin (V)

Ideal Step Width = 1 LSB

DNL

Slide 27

DNLDNL

• DNL is calculated by subtracting the ideal step width (1 LSB) from the

actual step width

•

• Worst case DNL tends to occur at the midpoint (switching from 011 to 100)

• which is the point where the MSB switches minus

the point where the LSB switches (to get 011) minus 1 LSB

• Knowing that the worst case output is 011 for VIN,SW3:

• Notice that the comparator of the first stage and the sample-and-hold of the

second stage have the largest impact on the worst case DNL

• DNLMAX must be less that ½ LSB to have N-bit resolution

82

REF

N

REF VVLSB ==

83,1,

REFSWINSWINMAX

VVVDNL −−=

82

1111

2

1

2

1323221

REFREFCOSSOSSOS

REFCOSREFMAX

VVV

AV

AVAA

VVVDNL −

−+++−+=

Slide 28

SimulationSimulation

No Offset

Slide 29


200mV offset on first S/H

Slide 30


200mV offset on last S/H

Slide 31


Slide 32

S/H DesignS/H Design

Figure 29.30

Standard S/H

Want to integrate subtraction and

amplification x2 into S/H

Note that input to S/H is not fully differential so we will use a single ended design

Slide 33



VCI

VCM

Slide 34


•

•

•

•

•

•

( )OSCMINFIFI VVVCQ ±−= ,

1

,

φ

( )OSCMCIII VVVCQ ±−=3φ

( )OSCMOUTFF VVVCQ ±−=3φ

3311 φφφφFIFI QQQQ +=+

CI

F

IIN

F

IOUT V

C

CV

C

CV −

+= 1

+

F

I

C

C1 ( )CI

F

I VC

C

+

F

I

C

C1

1+I

F

CI

C

C

V

+−

+=

1

1

I

F

CI

F

IOUT

C

C

VVin

C

CV

Slide 35


• We want to multiply VIN by 2, so CI=CF

• The final output is:

• We want to subtract VREF/2 from the input, but this

implementation will divide VCI by 2

• This means we need to supply VREF on VCI instead of VREF/2

for this implementation to work

• VCI will be either VREF or GND, depending on the state of the

switch

• Notice the op-amp offset is auto-zeroed out, but there is still

offset from the switches

−=2

2 CIINOUT

VVV

Slide 36


VREF=5V

5V 5V

2.5V

clk

D2 D1 D0

Slide 37


Slide 38

1.5 Bits/Stage1.5 Bits/Stage

• Traditional design uses a single comparator, which results in a single

bit per stage and two levels (0 or a 1)

• Two bits per stage would result in four levels (00, 01, 10, 11)

• 1.5 bits per stage means that we use three levels which is based on a

thermometer code (00, 01, 11)

• 1.5 bits per stage requires two comparators per stage instead of one

as used in the basic design

Slide 39



VCI

S/H with

subtractor/x2

amp

+VCMVOUT

VIN

( ) CMCMCMINOUT VVababVabVV +−−−= 202

a

b

−−+=2

3

222 CMCMCM

INOUT

Vab

Vab

VabVV

This does not account for the fact that

the S/H will divide VCM by 2, so these

would need to be compensated

Difficult to add and subtract using

single sided design

Slide 40


Figure 34.50

Swings around VCM

for single ended case

Slide 41


Figure 34.42

+

−−−

+= −+

−+

1

)()(1

I

F

CICIinin

F

IOUT

C

C

VVVV

C

CV

−−−= −+

−+2

)()(2 CICI

ININOUT

VVVVV

Slide 42


Digital Value + ½ of the analog output must always equal the

input for each stage, just like the standard implementation

Slide 43


−−+=2

3

222 CMCMCM

INOUT

Vab

Vab

VabVV

3.85V3.85V3.85V3.85V

VVVVCMCMCMCM=2.5V=2.5V=2.5V=2.5V

3V3V3V3VCMCMCMCM/2=3.75V/2=3.75V/2=3.75V/2=3.75V

VVVVCMCMCMCM/2=1.25V/2=1.25V/2=1.25V/2=1.25V

11111111

0.2V0.2V0.2V0.2V

00000000

2.9V2.9V2.9V2.9V

01010101

Slide 44


−−+=2

3

222 CMCMCM

INOUT

Vab

Vab

VabVV

1.15V1.15V1.15V1.15V

VVVVCMCMCMCM=2.5V=2.5V=2.5V=2.5V

3V3V3V3VCMCMCMCM/2=3.75V/2=3.75V/2=3.75V/2=3.75V

VVVVCMCMCMCM/2=1.25V/2=1.25V/2=1.25V/2=1.25V

01010101

----0.2V0.2V0.2V0.2V

00000000

2.1V2.1V2.1V2.1V

01010101

Wrong Decision!Wrong Decision!Wrong Decision!Wrong Decision!

Digital+1/2*Analog =InputDigital+1/2*Analog =InputDigital+1/2*Analog =InputDigital+1/2*Analog =Input

Okay if fully

differential

Slide 45


• Advantage:

Comparators can be “sloppy” and can make mistakes

without ruining the entire conversion

• Disadvantage:

Requires 2N comparators instead of N comparators

Requires extra logic overhead to convert 2 bit output to

single bit output

Slide 46

SummarySummary

• Basic Operation

• Pipeline with a S/H, comparator, subtractor, and x2 amplifier

• Each stage operates on residue of previous stage

• Advantages/Disadvantages

• N comparators, one computation per clock cycle

• Latency of N clock cycles, errors propagate

• Ideal/Non-Ideal Switching Points

• INL/DNL

• Accuracy of early stages more important than later stages

• S/H Design

• Integrate subtractor and x2 amplifier in S/H

• 1.5 Bits/Stage

• Increase accuracy at the cost of area

Slide 47

ReferencesReferences

• Baker, R.J., CMOS Circuit Design, Layout, and Simulation, Second

Edition, Wiley-IEEE, 2008.

• Baker, R.J., CMOS Mixed-Signal Circuit Design, First Edition, Wiley-

IEEE, 2002.

Slide 48

Questions?Questions?

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Understanding Design and Operation of Successive ... · PDF fileUnderstanding Design and Operation of Successive Approximation Register ... SAR ADC Different SAR ADC topologies Comparison