Switches Transmission gates Advanced Digital Logic Design

Advanced Digital Logic Design – EECS 303

http://ziyang.eecs.northwestern.edu/eecs303/

Teacher: Robert DickOffice: L477 TechEmail: [email protected]: 847–467–2298

Transistors in digital systemsHomework

Two-level logicHomework

SwitchesCMOSAND and OR are harder than NAND and NORTransmission gates

Switch-based design representation

A switch shorts or opens two points dependant on a control signal

Used as models for digital transistors

Why is using normally open and normally closed particularlyuseful for CMOS?

NMOS and PMOS transistors easy to model

4 Robert Dick Advanced Digital Logic Design




Switch-based definitions

control

normally openswitch

true

closed switch

false

open switch

control

switch

open switch

closed switch

normally closed

true

false





Microwave control example

halt

microwave

water vaporsensed

at least fiveminutes elapsed

cancel buttonpressed

true

What happens if the cancel button is not pressed and fiveminutes haven’t yet passed?

The output value is undefined.





Constraints on network output

Under all possible combinations of input values

Each output must be connected to an input value

No output may be connected to conflicting input values





Switch-based AND

ba

false

output

true

Note that this requires

Normally closed switches that transmit false signals well

Normally open switches that transmit true signals well





Relationship with CMOS

Metal Oxide Semiconductor

Positive and negative carriers

Complimentary MOS

PMOS gates are like normally closed switches that are good attransmitting only true (high) signals

NMOS gates are like normally open switches that are good attransmitting only false (low) signals





NAND gate

Therefore, NAND and NOR gates are used in CMOS design instead ofAND and OR gates

ba

output

true

false

=

ba

output

true

false

=

NMOS

PMOS





Transistors

Basic device in NMOS and PMOS (CMOS) technologies

Can be used to construct any logic gate





NMOS transistor

gate

silicon bulk (P)

drain (N)source (N)

oxide

gate

silicon bulk (P)

drain (N)source (N) channel

oxide





NMOS transistor

Metal, oxide, semiconductor (MOS)

Then it was polysilicon, oxide, semiconductorNow it is metal, hafnium-based low-k dielectric, semiconductor

P-type bulk silicon doped with positively charged ions

N-type diffusion regions doped with negatively charged ions

Gate can be used to pull a few electrons near the oxide

Forms channel region, conduction from source to drain starts





CMOS

NMOS turns on when the gate is high

PMOS just like NMOS, with N and P regions swapped

PMOS turns on when the gate is low

NMOS good at conducting low (0s)

PMOS good at conducting high (1s)

Use NMOS and PMOS transistors together to build circuits

Complementary metal oxide silicon (CMOS)





CMOS NAND gate

VSS

VDD

A B

Z

VSS

VDD

A B

Z

PMOS

NMOS

VSS

VDD

A B

Z

VSS

VDD

A B

Z

pull−up network

pull−down network





CMOS NAND gate layout





CMOS inverter operation

VDD

VSS

A B

VDD

VSS

A=0

B=1

A B

VDD

VSS

A B

VDD

VSS

A=1

B=0A B

VDD

VSS

A B

VDD

VSS

A B

A=?

B=?





NAND operation

VSS

VDD

A B

Z

Z=1

B=0A=0

VSS

VDD

A B

Z

B=1

VSS

VDD

A B

Z

Z=1

A=0

blockedVSS

VDD

A B

Z

A=1

VSS

VDD

A B

Z

Z=1

B=0

blocked

VSS

VDD

A B

Z

Z=0

B=1

A=1

VSS

VDD

A B

Z

VSS

VDD

A B

Z





NOR operation

VSS

VDD

A B

Z

Z=1

B=0

A=0

VSS

VDD

A B

Z

B=1Z=0

VSS

VDD

A B

Z

blocked

A=0

VSS

VDD

A B

Z

A=1

Z=0

VSS

VDD

A B

Z

B=0

blocked

VSS

VDD

A B

Z

A=1 B=1Z=0

VSS

VDD

A B

Z

VSS

VDD

A B

Z





Non-ideality of NMOS/PMOS transistors

Recall that NMOS transmits low values easily. . .

. . . transmits high values poorly

PMOS transmits high values easily. . .

. . . transmits low values poorly






VT , or threshold voltage, is commonly 0.7 V

NMOS conducts when VGS > VT

PMOS conducts when VGS < −VT

What happens if an NMOS transistor’s source is high?

Or a PMOS transistor’s source is low?

Alternatively, if one states that VTN = 0.7 V and VTP = −0.7 Vthen NMOS conducts when VGS > VTN and PMOS conductswhen VGS < VTP





NMOS transistor

gate

silicon bulk (P)

drain (N)source (N)

oxide






If an NMOS transistor’s input were VDD (high), for VGS > VTN ,the gate would require a higher voltage than VDD

If an PMOS transistor’s input were VSS (low), for VGS < VTP ,the gate would require a lower voltage than VSS





Implications of non-ideality

VSS

VDD

A B

Z

Z=1

B=0A=0

NAND/NOR easy to build in CMOS





Implications of non-ideality

AND/OR requires more area, power, time





CMOS transmission gates (switches)

NMOS is good at transmitting 0s

Bad at transmitting 1s

PMOS is good at transmitting 1s

Bad at transmitting 0s

To build a switch, use both: CMOS





CMOS transmission gate (TG)

B

C

C

A





Other TG diagram





What can we build with TGs?

Anything. . . try some examples.




AssignmentDetails

Lab one

Walks you through the design and simulation of an exclusive-or(XOR) gate

Due on 2 October

Start early, especially if you are not familiar with Unix

This lab requires a lot of tasks that are extremely easy the secondtime you do them, but slow and error-prone the first time through




AssignmentDetails

Timing diagram for half adder

100 200

A

B

SUM

CARR Y

sum propagationdelay

100 200

A

B

SUM

CARR Y

100 200

A

B

SUM

CARR Y

sum propagationdelay

100 200

A

B

SUM

CARR Y

100 200

A

B

SUM

CARR Y

glitch

100 200

A

B

SUM

CARR Y

Delay between input and output changes

Delay is sensitive to circuit path

Outputs may temporarily be incorrect before stabilizing

Glitches – caused by hazards




AssignmentDetails

Block diagrams

Sum

Cout

A

B

Cin

A

B

Sum

Carry

HA A

B

Sum

Carry

HA

Full adder composed of half adderblocks

Sum

Cout

A

B

Cin

A

Cin

Sum

Cout

F A B

Full adder block

Structural organization of the design

Hierarchical functional black boxes with input/output connections

Concentrates on how the components are organized by wiring




AssignmentDetails

Mentor Graphics tools introduction

The Mentor Graphics CAD system has many components

You will use a portion of the tools in this course

Falcon Design FrameworkDesign Architect for entering logic designsQuicksim for simulating the designsQuickHDL for entering and simulating the VHDL designs

You will soon be working on lab 1, a Mentor Graphics tutorial




AssignmentDetails

Mentor Graphics introduction

Typing “source /vol/ece303/mgc.env” in the ECE filesystem willset up environment for ECE 303 labs

Typing “dmgr” for Design Manager will open a window allowingseveral other Mentor Graphics to be run

Mentor Graphics is not a single tool tool but a series of designtools that uses object oriented data representation to simplify thedesign process




AssignmentDetails

Mentor Graphics introduction

Data created in one tool (e.g., Design Architect) can be exportedto another tool (e.g., Quicksim) for simulation

A schematic is a diagram of a circuit

Warning: Don’t use OS commands to move directories or files

Design Manager needs to update other files when things aremoved




AssignmentDetails

Component definition

b

a

Sum

Cout

A

B

Cin

A

B

Sum

Carry

HA A

B

Sum

Carry

HA

Sum

Cout

A

B

Cin

A

Cin

Sum

Cout

F A B

Data created by Design Architect is saved as components

Models describing functional and graphical aspects

Component data is composed of a schematic and a symbol

A symbol is a graphical model with input and output pins

A schematic is a functional model describing the relationshipbetween output and input values




AssignmentDetails

Viewpoint definition

A viewpoint is a set of rules specifying a design’s configuration

Specifies the subset of data to use as input for a specific tool

Allows a block to be described in different ways within differentviewpoints

One can evaluate the impact of a low-level design decision onhigh-level designFor now, one viewpoint per design should be sufficient




Boolean algebraSimplificationKarnaugh maps

Boolean algebra

Set of elements, B

Binary operators, { [ AND, ∧, *, · ], [ OR, ∨, + ] }

We’ll prefer · and +· frequently omitted

Unary operator, [ NOT, ’, o ]





Axioms of Boolean algebra

∃x , y ∈ B s.t. x 6= y

closure ∀x , y ∈ B xy ∈ B

x + y ∈ B

commutative laws ∀x , y ∈ B xy = yx

x + y = y + x

identities 0, 1 ∈ B,∀x ∈ B x1 = x

x + 0 = x





Axioms of Boolean algebra

∃x , y ∈ B s.t. x 6= y

distributive laws ∀x , y , z ∈ B x + (yz) = (x + y)(x + z)x(y + z) = xy + xz

compliment x ∈ B xx = 0x + x = 1





DeMorgan’s laws

(a + b) = a b

ab = a + b

f (x1, x2, . . . , xn, ·,+) = f (x1 , x2 , . . . , xn ,+, ·)

Those xs could be functions

Apply in stages

Top-down





DeMorgan’s laws example

a + bc

a · (bc)

a · (b + c )





Representations of Boolean functions

Truth table

Expression using only ·, +, and ’

Symbolic

Karnaugh map

More useful as visualization and optimization tool





AND

a b a b

0 0 00 1 01 0 01 1 1

b

a

a AND b = a bWill show Karnaugh map later





OR

a b a + b

0 0 00 1 11 0 11 1 1

a

b

a OR b = a + b





NOT

a a

0 11 0

a

NOT a = a





Different representations possible

A

B

C

D

T 2

T 1

Z A

B

C

D

T 2

T 1

Z

Z = ((C + D) B ) A

Z

A

B

C

D

Z = (C + D) A B





Simplifying logic functions

Minimize literal count (related to gate count, delay)

Minimize gate count

Minimize levels (delay)

Trade off delay for area

Sometimes no real cost





Proving theorems = simplification

Prove XY + XY = X

XY + XY = X (Y + Y ) distributive law

X (Y + Y ) = X (1) complementary law

X (1) = X identity law





Proving theorems = simplification

Prove X + XY = X

X + XY = X1 + XY identity law

X1 + XY = X (1 + Y ) distributive law

X (1 + Y ) = X1 identity law

X1 = X identity law





Literals

Each appearance of a variable (complement) in expression

Fewer literals usually implies simpler to implement

E.g., Z = AB C + A B + A BC + B C

Three variables, ten literals





NANDs and NORs

Can be implemented inCMOS

More on this later

X NAND Y = XY

X NOR Y = X + Y

Do we need inverters?





Karnaugh maps (K-maps)

Fundamental attribute is adjacency

Useful for logic synthesis

Helps logic function visualization





Karnaugh maps

0 1a

a

0 1

0 1a

a

0 1

b

a

00 01

10 11

0

1

1

a

b0

0 1a

a

0 1

b

a

00 01

10 11

0

1

1

a

b0

bc

0

1a

c

a

b

10110100

0 1a

a

0 1

b

a

00 01

10 11

0

1

1

a

b0

bc

0

1a

c

a

b

10110100

ab

10110100

00

01

11

10

cd

a

b

c

d





Sum of products (SOP)

0 1

10

1 10

0

0 1

10

1 10

0

0 1

10

1 10

0

0 1

10

1 10

0

(

a b)

+ (a b)





Implicants

0

1

00

10

1 1 1 1

1

01 11 10

implicant

0

1

00

10

1 1 1 1

1

01 11 10

implicant

0

1

00

10

1 1 1 1

1

01 11 10

implicant

0

1

00

10

1 1 1 1

1

01 11 10

prime implicant

0

1

00

10

1 1 1 1

1

01 11 10

essential prime implicant

0

1

00

10

1 1 1 1

1

01 11 10

0

1

00

10

1 1 1 1

1

01 11 10

0

1

00

10

1 1 1 1

1

01 11 10

Prime implicants are not covered by other implicants Essential primeimplicants uniquely cover minterms





K-map example

Minimize f (a, b, c , d) =∑

(1, 3, 8, 9, 10, 11, 13)

f(a, b, c, d) = a b + b d + a c d





K-map simplification technique

For all minterms

Find maximal groupings of 1’s and X’s adjacent to that minterm.

Remember to consider top/bottom row, left/right column, andcorner adjacencies.

These are the prime implicants.






Revisit the 1’s elements in the K-map.

If covered by single prime implicant, the prime is essential, andparticipates in final cover.

The 1’s it covers do not need to be revisited.






If there remain 1’s not covered by essential prime implicants,

Then select the smallest number of prime implicants that coverthe remaining 1’s.

This can be difficult for complicated functions.

Will present an algorithm for this in a future lecture.





Product of sums (POS)

0 1

10

1 10

0

0 1

10

1 10

0

0 1

10

1 10

0

0 1

10

1 10

0

0 1

10

1 10

0

(a + b) ·(

a + b)





POS K-map techniques

Direct reading by covering zeros and inverting variables

Or

Invert function

Do SOP

Invert again

Apply DeMorgan’s laws





POS K-map example

Minimize f (a, b, c) =∏

(2, 4, 5, 6)

f (a, b, c) = (b + c)(a + b)





Six-variable K-map example

z(a, b, c , d , e, f ) =∑

(2, 8, 10, 18, 24, 26, 34, 37, 42, 45, 50, 53, 58, 61)






CD

EF

CD

EF

AB =00

AB =01

00 01 11 10

00

01

11

10

00 01 11 10

00

01

11

10

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

16 20 28 24

17 21 29 25

19 23 31 27

18 22 30 26

CD

EF

AB =11

00 01 11 10

00

01

11

10

48 52 60 56

49 53 61 57

51 55 63 59

50 54 62 58

CD

EF

AB =10

00 01 11 10

00

01

11

10

32 36 44 40

33 37 45 41

35 39 47 43

34 38 46 42

CD

EF

CD

EF

AB =00

AB =01

00 01 11 10

00

01

11

10

00 01 11 10

00

01

11

10

CD

EF

AB =11

00 01 11 10

00

01

11

10

CD

EF

AB =10

00 01 11 10

00

01

11

10

1

1 1

1

1 1

1 1

1 1

1 1

1 1






z(a, b, c , d , e, f ) = d e f + ad e f + a C d f





Don’t Care logic

All specified Boolean values are 0 or 1

However, during design some values may be unspecified

Don’t care values (×)

At ×s allow circuit optimization

Incompletely specified functions allow optimization





Don’t Care values

0

0

0 1

10

1 1

0

0

0 1

10

1 1

0 1

10

1 1

0 1

10

1 1

0 1

10

1 1

Instead, leave these values undefined (×)

Also called Don’t Care valuesAllows any function implementing the specified values to be usedE.g., could use

(

a b)

+ (a b)However, best to use simpler 1





Satisfiability Don’t Cares

0

0 1

10

1 1wheelsensor

brakesensor

output

0 0

10

1

1

decision

8

32

apply brake

pulse brake

invalid output

release brake

0

1

b

ab

aa b

Input can never occur

This can happen within a circuit

Some modules will not be capable of producing certain outputs





Observability Don’t Cares

<

0 1

1

0 1

10

1

0 1

1

0

0

0 0

1

0 1

1

0 0

1

r

c

a

b

c

ar(a,c)

c(a,b) a

b

c’(a,b) a

b

c(a,b) = a ∧b c’(a,b) = b

Output will be ignored for certain inputs





Don’t-care K-map example

Minimize f (a, b, c , d) =∑

(1, 3, 8, 9, 10, 11, 13) + d(5, 7, 15)

f (a, b, c , d) = a b + d





CMOS

Refer to M. Morris Mano and Charles R. Kime. Logic and

Computer Design Fundamentals. Prentice-Hall, NJ, fourthedition, 2008

http://www.writphotec.com/mano/

CMOS supplement

Optimization supplement

qm.py at http://ziyang.eecs.northwestern.edu/∼dickrp/tools.html




Intractable problems reading assignment

Michael R. Garey and David S. Johnson. Computers and

Intractability: A Guide to the Theory of NP-Completeness. W. H.Freeman & Company, NY, 1979

Chapter 1, Sections 1–5

Introduces the concept of intractable problems

Many problems in digital design are intractable

Too hard to solve optimally in a reasonable amount of time

Use heuristics




Computer Geek Culture

Python and perl


Documents

Switches Transmission gates Advanced Digital Logic Design