Surface Potential and Threshold Voltage Modeling of Pocket … · 2019-06-28 · ii | P a g e CERTIFICATION The thesis titled “SURFACE POTENTIAL AND THRESHOLD VOLTAGE MODELING OF

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Surface Potential and Threshold Voltage

Modeling of Pocket Implanted Asymmetric

n-Channel MOSFETs

A thesis submitted to

the Department of Electrical and Electronic Engineering

of

Bangladesh University of Engineering and Technology

in partial fulfillment of the requirement

for the degree of

Master of Science in Electrical and Electronic Engineering

By

S.M. Naeemul Islam

Department of Electrical and Electronic Engineering

Bangladesh University of Engineering and Technology

2012

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CERTIFICATION

The thesis titled “SURFACE POTENTIAL AND THRESHOLD VOLTAGE MODELINGOF POCKET IMPLANTED ASYMMETRIC N-CHANNEL MOSFETS” submitted by S.M. Naeemul Islam, Roll No.: 1009062086P, Session: October, 2009 has been accepted assatisfactory in partial fulfillment of the requirements for the degree of MASTER OF SCIENCEIN ELECTRICAL AND ELECTRONIC ENGINEERING on May 22, 2012.

BOARD OF EXAMINERS

1.____________________________________________(Dr. Md. Ziaur Rahman Khan) ChairmanAssociate Professor, (Supervisor)Department of Electrical and Electronic Engineering,Bangladesh University of Engineering & Technology,Dhaka-1000, Bangladesh.

2.(Dr. Md. Saifur Rahman) MemberProfessor and Head, (Ex-Officio)Department of Electrical and Electronic Engineering,Bangladesh University of Engineering & Technology,Dhaka-1000, Bangladesh.

3.______________________________________________(Dr. A. B. M. Harun-Ur-Rashid) MemberProfessor,Department of Electrical and Electronic Engineering,Bangladesh University of Engineering & Technology,Dhaka-1000, Bangladesh.

4. _____________________________________________(Dr. Md. Anwarul Abedin) MemberProfessor, (External)Department of Electrical and Electronic Engineering,Dhaka University of Engineering & Technology,Gazipur, Bangladesh.

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DECLARATION

It is hereby declared that this thesis or any part of it has not been submitted elsewhere for the

award of any degree or diploma.

Signature of the candidate

________________________

(S. M. Naeemul Islam)

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DEDICATION

This dissertation is dedicated to my parents and in the memory of my friend Tanim who is always

been my inspiration as ever forever. May Allah bestow peace upon him.

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Contents

List of Figures viii

List of Tables xi

List of Abbreviations xii

List of Symbols xiii

Acknowledgement xv

Abstract xvi

Chapter 1 : Introduction 1

1.1 Introduction 1

1.2 Literature Review 2

1.3 Objectives 7

1.4 Methodology 7

1.5 Thesis Layout 8

Chapter 2 : MOSFET Operation 9

2.1 Introduction 9

2.2 MOSFET Operation 9

2.2.1 Energy Band Diagram 10

2.2.2 Flat Band voltage 13

2.2.3 Effect of VGS on surface condition 15

2.2.3.1 Accumulation 15

2.2.3.2 Depletion and Inversion 16

2.2.4 Potential balance and charge balance 20

2.2.5 Threshold Voltage 20

2.2.6 Current Voltage characteristics 22

2.3 Short Channel MOSFET 25

2.3.1 Channel Length Modulation 26

2.3.2 Threshold Voltage Roll Off 27

2.3.3 Punch Through 28

2.3.4 Drain Induced Barrier Lowering 28

2.3.5 Avalanche Breakdown 29

2.3.6 Hot Carrier Injection 31

2.4 Combating Short Channel Effects 31

2.4.1 Retrograde Well 32

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2.4.2 Punch through stop implant 33

2.4.3 Threshold adjust implant 33

2.4.4 Pocket implantation 33

2.4.5 Lightly Doped Drain 34

2.5 Summary 34

Chapter 3 : Numerical Modeling of Asymmetric n-MOSFET 35

3.1 Introduction 35

3.2 Fabrication Process 36

3.3 Software Overview 38

3.4 Simulation Methods 38

3.4.1 Structure Specification 39

3.4.2 Materials Model Specification 42

3.4.2.1 Boltzman Model 43

3.4.3 Numerical Method Specification 45

3.4.3.1 Bi- Conjugate Gradient Method 46

3.4.3.2 Bi- Conjugate Gradient Method Algorithm 46

3.4.4 Solution Specification 47

3.4.5 Result Analysis 47

3.5 ATLAS Modeling Summary 48

3.6 Threshold Voltage Extraction 48

3.6.1 Algorithm of Double Differentiation Method 48

3.7 Summary 49

Chapter 4 : Analytical Modeling of Asymmetric n-MOSFET 50

4.1 Introduction 50

4.2 Surface Potential 50

4.3 Architecture Overview 51

4.4 General Mathematical Derivation of Surface Potential 52

4.4.1 Mathematical derivation in Region 1 55

4.4.1.1 Homogeneous Solution of ψS1(x) 57

4.4.1.2 Particular Integral of ψS1(x) 57

4.4.2 Mathematical derivation in region 2 58



4.4.5 Calculation of constant A 62

4.5 Threshold Voltage Modeling 66

4.5.1 Algorithm to Find Threshold Voltage, VTH 67

4.6 Summary 72

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Chapter 5 Simulation Results and Discussions 73

5.1 Introduction 73

5.2 Process Parameters 74

5.3 Surface Potential Model Validation 75

5.4 Surface Potential Variation with Channel Length 84

5.5 Surface Potential Variation with Pocket Length 85

5.6 Surface Potential Variation with Pocket Implant Concentration 86

5.7 Surface Potential Variation with VBS 87

5.8 Surface Potential Variation with VGS 88

5.9 Surface Potential Variation with VDS 89

5.10 Comparison of Analytical Surface Potential Model with that of [18] 90

5.11 Threshold Voltage Model Validation 91

5.12 Threshold Voltage Extraction Technique 94

5.13 Threshold Voltage Variation with Pocket Length 95

5.14 Threshold Voltage Variation with Pocket Implant Concentration 96

5.15 Threshold Voltage Variation with VDS 97

5.16 Threshold voltage variation with VDS at different channel length 98

5.17 Threshold voltage model comparison with some literatures 99

5.18 Summary 100

Chapter 6 : Conclusion 101

6.1 Conclusion 101

6.2 Limitation 102

6.3 Scopes of Future Work 102

References 103

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List of Figures

Figure 1.1: Number of transistor in recent Intel Processors 1

Figure 1.2: Threshold voltage with Channel length reported in [14] for LP= 20 nm,

NP=1.75x1018 cm-3, VDS= 0 V, VBS=0 V 4

Figure 1.3: Threshold voltage with Channel length reported in [16] for LP= 24 nm,

NP=1.906x1018 cm-3, VDS= 1 V, VBS=0 V 5

Figure 1.4: Drain current vs Drain voltage reported in [18] 6

Figure 2.1 : Long channel enhancement type n-channel MOSFET 9

Figure 2.2 : MOSFFET with no gate voltage 10

Figure 2.3 : Energy band diagram (a) before contact (b) after contact 11

Figure 2.4 : Flat Band Voltage 14

Figure 2.5: Accumulation (a) structure (b) energy band diagram 15

Figure 2.6: Depletion (a) structure (b) energy band diagram 16

Figure 2.7: Energy band diagram of MOSFET (a) VGS=0, (b) 0VT 19

Figure 2.9 : MOSFET operation (a) small VDS, (b) ID-VDS for a, (c) VDS increased, (d) ID-VDS for

c, (e) VDS=VDSsat, (f)ID-VDS for e, (g) VDS>VDSsat, (h) ID-VDS for g 23

Figure 2.10: Channel length modulation 26

Figure 2.11: Depletion regions (a) long channel MOSFET, (b) short channel MOSFET 27

Figure 2.12: Energy band diagram for (a) long channel MOSFET, (b) short channel MOSFET

due to DIBL 28

Figure 2.13: Curvature effect on electric field 29

Figure 2.14: Secondary effect by parasitic bipolar transistor 30

Figure 2.15: Snapback breakdown effect 30

Figure 2.16: Effect of hot carrier injection 31

Figure 2.17: Retrograde well and conventional well profile distribution 32

Figure 3.1: Asymmetric pocket implanted n-channel MOSFET 36

Figure 3.2: Fabrication process flow 37

Figure 3.3: Five groups of operations in order to simulate a device 39

Figure 3.4: Components of Structure Specification in an ordered manner 39

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Figure 3.5: Grid points or nodes in a device structure 40

Figure 3.6: Regions and electrodes in a device structure 41

Figure 3.7: Net doping in a device structure 42

Figure 3.8: Components of materials model specification in an ordered manner 42

Figure 3.9: Summarization of device modeling in ATLAS 48

Figure 3.10: Example of extraction of threshold voltage using double differentiation method 49

Figure 4.1: Asymmetric n-channel MOSFET 51

Figure 4.2: Cubic Gaussian surface 53

Figure 4.3: Close view of region 1, here it is assumed that the doping of source, source

extension, pocket and p type substrate are Nd1, Nd2, Na and Na1 respectively 55

Figure 4.4: Closer look at region 2 expands from L1 to L2 along the x direction 58

Figure 4.5: Close view of region 3 between L2 and L3 along x axis; assuming the concentration

of LDD is Nd3 per cm3 60

Figure 4.6: Close view of region 4 61

Figure 4.7: Flow chart of determination of VTH using surface potential 68

Figure 4.8: Flow chart of modified version of figure 4.7 to determine VTH 69

Figure 5.1: Asymmmetric MOSFET with process parameter notation 74

Figure 5.2: Surface potential distribution of a 100 nm device with LP= 20 nm, NP= 2x1018 cm-3

[other parameters given in Table 5.1] 76

Figure 5.3: Analytical and numerical model data of a device where NP=2x1018 cm-3, LP= 25 nm

(a) L =100 nm, (b) L= 130 nm, [other parameters are given in Table 5.1] 78

Figure 5.4: Analytical and numerical model data of a device where NP=2x1018 cm-3, LP= 25 nm

(a) L =150 nm, (b) L= 200 nm, [other parameters are given in Table 5.1] 79

Figure 5.5: Analytical and numerical model data of a device where NP=2.25x1018 cm-3, LP= 25

nm (a) L =100 nm, (b) L= 130 nm, [other parameters are given in Table 5.1] 80







Figure 5.9: Surface potential along the channel for different channel length 84

Figure 5.10: Surface potential along the channel at different pocket length 85

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Figure 5.11: Surface potential along the channel at different pocket implant concentration 86

Figure 5.12: Surface potential along the channel at different body to source voltages 87

Figure 5.13: Surface potential along the channel at different gate to source voltages 88

Figure 5.14: Surface potential along the channel at different drain to source voltages 89

Figure5.15:Surface Potential across the Channel with VDS=1.5 V, VGS= 0.8 V,

NSUB=0.5×1018cm-3, NP=4×10

18cm-3, NSE=2×1018cm-3, NLDD=1×10

18cm-3,L=200 nm, LSE=0.05

µm, LP=0.15 µm, LLDD=0.1 µm [other parameters are given in Table 5.1] 90

Figure 5.16: Threshold voltage vs Channel length for a device with NP= 1.5x1018 cm-3 and LP=

25 nm [other parameters are given in Table 5.1] 92



Figure 5.18: Threshold voltage vs Channel length for a device with NP= 2x1018 cm-3 and LP= 20

nm [other parameters are given in Table 5.1] 93



Figure 5.20: Threshold voltage extraction technique 94

Figure 5.21: Threshold voltage vs Channel length for a device with NP= 1.75x1018 cm-3 at

different pocket length [other parameters are given in Table 5.1 ] 95

Figure 5.22: Threshold voltage vs Channel length for a device with LP= 25 nm at different

pocket implant concentration [other parameters are given in Table 5.1 ] 96

Figure 5.23: Threshold voltage vs Channel length for a device with NP= 1.75x1018 cm-3 and LP

=20 nm at different drain to source voltages [other parameters are given in Table 5.1 ] 97

Figure 5.24: Threshold votlage vs Drain to source voltage 98

Figure 5.25: Threshold voltage vs Channel length for NP=1.75x1018 cm-3, LP=20 nm, VDS= 1 V,

VBS=0 V 99

Figure 5.26: Threshold voltage vs Channel length for NP=1.906x1018 cm-3, LP=24 nm, NSUB=

2.175x1017 cm-3, VDS= 1 V, VBS=0 V 100

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List of Tables

Table 2.1: Work function of some metals..................................................................................... 11

Table 2.2: Electron affinity of some semiconductors ................................................................... 11

Table 5.1: A typical process parameters with notations and typical values ................................. 75

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List of Abbreviations

Abbreviated Word Elaboration

DIBL Drain Induced Barrier Lowering

FET Field Effect Transistor

LDD Lightly Doped Drain

MOSFET Metal Oxide Semiconductor Field Effect Transistor

RSCE Reverse Short Channel Effect

SCE Short Channel Effect

SE Source Extension

TCAD Technology Computer Aided Design

ULSI Ultra Large Scale Integration

VLSI Very Large Scale Integration

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List of Symbols

µn - mobility of electron

B – Body terminal

COX – Oxide capacitance per unit area

D – Drain terminal

Dn – Diffusion con-efficient for electron

Dp - Diffusion con-efficient for hole

E – Electric field

EC – Conduction band energy

EF – Fermi level energy

EFi – Intrinsic Fermi level energy

EG – Band gap energy

EV – valance band energy

G – Gate terminal

gd – Conductance of MOSFET

gm- Transconductance of MOSFET

Gn – Generation rate of electron

GP - Generation rate of hole

ID – Drain current

Jn – Current density due to electron

Jndrift – Current density due to drift

electron

Jp - Current density due to electron

Jpdrift - Current density due to drift hole

k – Boltzman’s constant

L – Channel length

LP – Pocket length

n – Total electron concentration in the

device

n0 – Thermal equilibrium electron

concentration

NA – Acceptor impurity concentration

ND – Donor impurity concentration

ni – Intrinsic concentration

Nit – Interface trap charge concentration

NP – Pocket implant concentration

nsurface – Electron concentration on

surface

p – Total hole concentration

p0 - Thermal equilibrium hole

concentration

q – Electron charge

Q0 – Oxide trap charge

QB – Depletion layer charge

QC – Total charge due to depletion and

inversion

QI – Inversion layer charge

rj – Junction depth of source/drain

implant

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Rn – Recombination rate for electron

RP - Recombination rate for hole

S – Source terminal

T – Operating temperature

tOX – Oxide thickness

VBS – Body to source voltage

Vd – Depletion layer voltage

VDS - Drain to source voltage

VFB – Flat band voltage

VGS - Gate to source voltage

Vit – Interface trap charge voltage

VOX – Oxide layer voltage

VTH - Threshold voltage

W – Width of the MOSFET

YD – Depletion width of MOSFET

ϵOX – Permittivity of oxide

ϵS - Permittivity of silicon

ρ – Charge density

Φbulk – Contact potential on bulk

ΦFN – Fermi potential of n-type region

ΦFP - Fermi potential of p-type region

Φgate - Contact potential on gate

ΦM – Metal work function

ΦS - Semiconductor work function

ψS – Surface potential

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Acknowledgement

In the name of Allah, the most Gracious, the most Compassionate.

I would like to convey my sincere gratitude and profound respect to my thesis supervisor Dr.

Md. Ziaur Rahman Khan, Associate Professor, Department of Electrical and Electronic

Engineering (EEE), Bangladesh University of Engineering and Technology (BUET), for his

continuous guidance, suggestion and wholehearted supervision throughout this research work. I

am grateful to him for his encouragement and patience. I would like to thank him for giving me

extra sessions from his invaluable time, even in holidays. I am deeply indebted to him in

fulfilling this research work which would be impossible to materialize without his support.

I am also grateful to the Committee of Advanced Studies and Research (CASR), BUET and

members of Board of Post Graduate Studies (BPGS) for giving me invaluable suggestion and

correction.

I also express my gratitude to Dr. Muhibul Haque Bhuyan, Associate Professor, EEE, Daffodil

International University, Bangladesh for giving me suggestions and invaluable source of

materials. I also want to express thanks to Mr. Shehrin Sayed for helping me to familiarize with

TCAD software.

I want to thank my friends Shafin, Rajib, Mirza and many others who were always been there to

support and encourage me. Last but not the least I would like to express my deepest gratitude to

my parents and family members, without their encouragement, I would not have come this far.

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Abstract

The use of asymmetric MOSFET has availed seeking new perspective in nanotechnology. There

are various difficulties and challenges in pursuit of high functional density in such low

dimension. The conventional symmetric long channel MOSFET device often fails to meet up the

challenges and that makes the demand of contemplation of asymmetric MOSFET. It has been

observed that asymmetry on MOSFET device brings superior control on threshold voltage roll

off, drain induced barrier lowering and other short channel effects which are the challenges

offered in the low dimension. So analysis and physical reasoning of nano scale MOSFET device

is important. This research presents an analytical modeling of surface potential model of nano

scale asymmetric n-channel enhancement type MOSFET device. The analytical model of surface

potential is further devised to achieve threshold voltage values for corresponding device. An

asymmetric MOSFET can be generally described as a planar MOSFET having a laterally non

uniform body profile (channel asymmetry) with or without different source or drain regions

(source/drain asymmetry). The device under analysis of this work, consists both channel and

source-drain asymmetry incorporating retrograde wells. The architecture contains pocket

implantation only on source side unlike the popular symmetric configuration of pocket implant

on both source and drain side. The absence of pocket implant at the drain side ensures

comparatively weaker electric field near the drain. Due to less electric field, the hot carrier

injection problem, one of the short channel effects, can be mitigated. The architecture also

contains source extension at source side and deep lightly doped drain (LDD) at drain side.

Highly doped source extension reduces parasitic resistances and ensures a better drive current

performance of the device. On the other hand LDD structure at drain side averts abrupt change of

electric field and reduces hot carrier injection effect. The analysis of such sublime device has

been performed by solving Poisson’s equation considering appropriate boundary conditions.

The analytical model of surface potential and threshold voltage, established by solving Poisson’s

equation has been investigated and verified by numerical modeling of the corresponding device

in a process simulator. The device performance and underlying physics are analyzed varying a

wide range of process parameters. The modeling accuracy is further verified by comparing with

the data of manufactured device reported in recent literature. The analytical model shows a good

and consistent accuracy with the numerical model data and the data reported in recent literature.

Chapter 1: Introduction 1 | P a g e

Chapter 1 : Introduction

1.1 Introduction

It was 1958 when Noble Laureate Jack Kilby first designed a prototype of an Integrated Circuit

(IC). After the invention of transistor in 1947, an extensive research was conducting to

miniaturize electrical circuit using transistors which eventually replaced vaccum tubes. However,

integrating a huge number of transistors and making contacts in the electrical circuit was a

daunting task and put forth a challenge in the advancement of the technology. In that time, it

seemed that advanced circuits containing so many components and connections were impossible

to implement. Jack Kilby, as a new employee, with no vacation in the summer started to delve in

order to find a solution to the problem working alone in the lab of Texas Instrument and finally

implemented an integrated circuit deriving from a single semiconductor- it was a groundbreaking

invention. Intel co-founder Robert Noyece then furnishes the crude prototype proposed by Kilby

and started the mass production of optimum design. That was the dawn of semiconductor

industries. Since then, research and development in semiconductor industry made the evolution

of IC a remarkably fast. Today in a 1.5×1.5 inch dimension Intel processor, millions of

transistors are integrated together and this number tends to increase with ever growing demands.

In fact, another co-founder of Intel Gordon Moore speculated that the number of transistors in a

processor doubles in every two years, which is known as Moore’s law. In Figure 1.1 typical

advancement of Intel cores in ten years has been shown.

Figure 1.1: Number of transistors in recent Intel Processors

It is interesting to witness that similar challenges still exists like Kilby’s day in order to advance

in this IC technology. Today a Core i7 Intel core contains 995 million transistors following 32

0

200

400

600

800

1000

1200

mil

lion


nm technologies, which means minimum channel length of semiconductor is not less than 60 nm.

With the progress of time, the minute scaled semiconductor device is in demand in order to build

low consumption, enhanced speed devices. The channel length of such semiconductor devices

can be less than 50nm. But reducing channel length of the device exhibits different challenges

and problems. Extensive researches are being conducted to cope with the problems and pursue

optimum design. However, question remains, how further scaling of semiconductor device can

be pushed? Such question often implies that the death of Moore’s law is approaching.

This dissertation will focus on modeling of nano meter size MOSFETs (Metal Oxide

Semiconductor Field Effect Transistors). In order to cope with short channel device challenges,

conventional architecture of transistor is changed a lot by incorporating non uniform doping

throughout the channel. The impact of such asymmetry in characterization of MOSFET will be

analyzed and visualized here.

1.2 Literature Review

Since the inception of the idea of integrated circuit back in late 1950’s, the advancement of

transistor and FET technology has been evolved in a way that a FET device in nano dimension is

available. The miniaturized size of devices makes a high packing density and high scale of

integrated circuit which is often referred as Very Large Scale Integration (VLSI) or more

advanced, Ultra Large Scale Integration (ULSI). The fabrication of FET device in nano meter

range is important to obtain low power and high speed performance devices, which is after all

pledges of all semiconductor industries for the modern technology. However, scaling down of

MOSFET devices is not a trivial task to follow. In such atomic scale, the quantum character of

the carrier in the device becomes significant and sometimes dominant. There are many

technological challenges to meet in order to fabricate nano meter sized MOSFET device. One of

daunting challenge is the threshold voltage, VTH shift which is reported qualitatively in [1] where

channel length is considered to be a few hundred nano meter. But advanced research work on

VTH shift is found in [2, 3] where channel length is considered to be less than 100 nm and even in

50 nm range. Similar effect has also been reported with emphasizing analog behavior of

MOSFET device in [4]. As in the long channel, the depletion width of p-type bulk

semiconductor near the surface is the dominant factor and extends almost all over the channel

length. As the channel reduces, channel length to junction depth (L/rj) is also reduced. As a

result, the depletion width of source and drain becomes significant and can no longer be

neglected. Due to the incorporation of this source and drain depletion charges, small induced

charge on gate terminal is sufficient to form an inversion channel on the surface, thus reducing

the threshold voltage. With more decreasing of channel length, the depletion width of drain and

source may become dominant and overlap each other. In this state, the device cannot be

controlled by applying voltage on gate terminal. A worst case scenario is flow of electron from

source to drain freely without giving any voltage on gate electrode. This effect is well known as

punch through effect which is reported in [5]. The effect is triggered by application of reasonable


high drain voltage. With the increase of drain voltage, depletion due to drain increases and

extends to the source. As a result the barrier for electron flowing from source to drain reduces.

This phenomenon is known as Drain Induced Barrier Lowering (DIBL). This effect is broadly

discussed and characterized in [6]. Moreover, with the increase of drain voltage, electric field

strength increases in the channel in a direction from drain to source in an n-channel MOSFET.

With the scaling of channel length, bias condition must also be scaled down to ensure device

normal operation. But, scaling down of bias condition in such a small level may not always be

viable. So, with a reduced dimension and comparatively higher bias condition may lead to high

electric field. Electric field may be as high so that charge inside depletion region may collide

with each other and generated secondary particles. This phenomenon is known as impact

ionization. Electrons generated by impact ionization may gain sufficient energy to exceed the

barrier and go beyond the surface and enter to the oxide. As a result oxide charge will be altered

and it will adversely affect threshold voltage characteristics. This phenomenon is known as hot

electron injection effect and this effect is reported in [7, 8]. In these literatures it has been shown

that the effect is more adverse in a channel length less than 150 nm. It is reported in [8] that in

such miniaturized dimension, along with impact ionization effect, tunneling effect can also occur

that will lead to similar result. Introduction of this quantum effect will further deteriorate device

performance.

New advanced technology in semiconductor realm, various techniques, fabrication process,

alteration of profile orientation, multi layer structure formation has been devised in promise of

combating above effects which is often termed as Short Channel Effects (SCE). Extensive

research and various literatures focused on combating SCE by introducing complex structural

device. The bulk p-type semiconductor on interface end has been altered and a complex impurity

profile is introduced in numerous literatures. Most common approach is to place high acceptor

impurity on the vicinity of source and drain region while in the bulk normal impurity prevails [9,

10]. The introduction of pocket implant i.e high impurity concentration near the surface as

reported in [11], give rise high voltage due to depletion and inversion of the device. As the

threshold voltage is directly related to these two terms and increases with the increase of these

two voltages. So using pocket or sometimes called halo implantation is an effective way to

prevent threshold voltage shift. As reported in [9], lateral channel engineering has been operated

on a 100 nm channel length of n-channel MOSFET device. The literature mainly focused on VTH

roll off effect and emphasized on improving it. The literature deduced a surface potential

equation by solving Poisson’s equation along the channel. The surface potential equation has

been used to extract threshold voltage of the device. The obtained results showed a better

performance on combating VTH roll off effect and it related VTH roll up factor proportional to

NP1/4 /LP where NP and LP are pocket implant concentration and pocket implant length

respectively. The result is validated by model data extracted from SUPREM-IV process

simulator. However, the analytical model shown in [9] introduced a fitting parameter in

threshold voltage calculation with less insight in it. Moreover, the research did not focus on other

SCEs that may alter the device performance. In [10], the literature explored the characterization


of n-channel MOSFET device in sub 100 nm channel length with a linear impurity profile

distribution. Similar to [9], the literature derived an analytical surface potential model by solving

Poisson’s equation along one direction. The simulated results was validated by comparing with

experimental results of other types of profile distribution like hyperbolic and Gaussian profile

found in literature [12] and [13] respectively. On the basis Bhuyan M.H. et al in [14], an

analytical model of threshold voltage had been deduced for the same architecture. Threshold

voltage variation with channel length reported in [14] has been shown in Figure 1.2. The figure

shows that threshold voltage of the device remains positive even in about 60 nm channel length.

The finding

threshold vo

Channel Eff

[9], this lite

voltage char

distribution

distribution.

energy of im

result a non

been given

bounding ch

those six re

Figure 1.2: Threshold voltage with Channel length reported in [14]18 -3

of the literature is very promising and in some respect, it has been observed that

ltage even increase at nano scale. This phenomenon is known as Reverse Short

ect (RSCE) which is completely opposite to the SCE. However, alike Bin Y. et al in

rature did not focus on improvement of other SCEs rather than improving threshold

acteristics. Furthermore, the literature considered a linear gradual change in impurity

along the surface, rather considering more complex hyperbolic or Gaussian

Ions are implanted varying two parameters 1) dose of the implantation and 2)

plantation. The fabrication technique is very advanced and complex that it may

linear distribution profile along the surface. In literature [15], a broad insight had

in complex impurity distribution. The architecture proposed contains six regions

annel to depletion width. The device has been analyzed varying concentration in

gions. The analysis led to an optimum profile distribution device which exhibits

for LP= 20 nm, NP=1.75x10 cm , VDS= 0 V, VBS=0 V


better performance in sub threshold region. So the literature made a scope to work with similar

analysis for above threshold region. In [16], Yun-Sup P. et al derived an analytical model of 100

nm n-channel MOSFET and validated the data by MEDICI process simulator. The analysis

based on the charge sheet approximation [17] with considering no fixed oxide charge. Figure 1.3

shows a threshold voltage variation with channel length as reported in [16].

As fixed oxide ch

potential, it cannot

So far the discussio

device. Hot elect

greater extent. Mo

not been reported.

proposed and a com

The architecture c

doped drain (LDD)

introduction of hig

by both channel as

and LDD). The po

hand, LDD on dr

reduced. Furtherm

electric field in dr

Figure 1.3: Threshold voltage with Channel length reported in18 -3

arge is an important factor in determining threshold voltage and surface

be neglected.

n in literatures is confined in threshold voltage improvement of short channel

ron effect improvement, prevention of punch through is not investigated in

reover, the optimum design of short channel device and their limitations are

In a recent literature [18], a highly complex asymmetric architecture had been

parison between its counterpart symmetric architecture had been highlighted.

ontains only source side pocket implantation while along the drain a lightly

extension had been implanted. The structure becomes more complex with the

hly doped source extension region. The asymmetry of the device is achieved

ymmetry (pocket implantation) and source/drain asymmetry (source extension

cket implantation is more obvious that it helps to roll up VTH. On the other

ain side, reduces the doping concentration and thus electric field is been

ore, as there is a gradual change in drain doping, an abrupt high to zero

ain junction will not occur. These effects enhance hot carrier improvement.

[16] for LP= 24 nm, NP=1.906x10 cm , VDS= 1 V, VBS=0 V


The analysis in the literature was based on the data of recently manufactured device. The

analysis is done on drift diffusion TCAD and based on physical reasoning and Lundstrom’s

scattering theory.

The analysis showed that asymmetric MOSFET shows better performance on hot carrier

improvement. Moreover, the architecture exhibited improved drain saturation current (drive

current), increase output resistance, increase trans-conductance and thus high voltage gain in

analog circuits. Figure 1.4 shows the better driving current performance in asymmetric device

compared with symmetric device as reported in [18].

On the other hand, s

[19], VTH mismatch

high drain saturati

insignificant in short

ome disadvantages of asymmetric channel device had also been noted. Noise

[20, 21], parameter variability [22] are among them. Another disadvantage is

on voltage had been noted for asymmetric device though it is quite

channel device.

Figure 1.4: Drain current vs Drain voltage reported in [18]


1.3 Objectives

The objectives of this work are:

i. To derive analytical model to find surface potential of asymmetric pocket implantedn-MOSFET

ii. To find threshold voltage of the device using the derived analytical model of surfacepotential

iii. To analyze the dependence of surface potential and threshold voltage on different processparameters like channel length, pocket implantation concentration, pocket implantationlength etc

iv. To develop a 2D structure of the device in TCAD software SILVACO 2007 and extractsurface potential and threshold voltage of the structure

v. To validate the accuracy of analytical model comparing with surface potential andthreshold voltage values extracting from SILVACO 2007 and the results reported in [18]

1.4 Methodology

At first the device is divided into different regions along the surface which cover source

extension region, pocket implantation region, bulk p type semiconductor region, drain extension

region etc. In each region a rectangular box is drawn through the channel and Gauss law is

applied which gives one dimensional Poisson’s equation of surface potential. Boundary

conditions of surface potential at initial and final point of the channel are calculated based on the

physical reasoning. The Poisson’s equation is solved based on known boundary conditions and

continuation of surface potential and electric field along the surface. Surface potential model is

used to calculate threshold voltage of the device. The effect of device parameter on surface

potential and threshold voltage of an n-channel asymmetric MOSFET is analyzed. Finally the

device is modeled in TCAD software SILVACO 2007 and the surface potential and threshold

voltage of the device are extracted. These values and the values reported in [18] are used to

validate the accuracy of proposed analytical models.


1.5 Thesis Layout

The research work in this thesis has been described in five chapters. This chapter introduces with

the problem in hand and the methodology to solve the problem. The upcoming chapters unveil

conventional MOSFET operation and short channel device operation challenges.

Chapter 2 mainly focuses on conventional long channel enhancement type n-channel MOSFET

operation. The analysis on Chapter 2 contains both qualitative concept discussion and derivation.

The chapter helps to explore the short channel device and the challenges that appear using short

channel devices in circuit operation.

Chapter 3 focuses on the numerical analysis of the research using TCAD software SILVACO

version 2007. The chapter unveils the process and methodology in order to define complex

structure in process simulator like ATLAS. After the definition of the device electrical properties

like bias condition and etc., numerically surface potential can be extracted for that device using

Tony Plot. Except the surface potential, ID-VGS curve for different conditions are also extracted

from Tony Plot.

Chapter 4 focuses on analytical modeling of the proposed complex asymmetric MOSFET

architecture. Based on physical reasoning and mathematical manipulation, 1st order Poisson’s

equation is solved in order to obtain surface potential equation. Later, an algorithm has been

employed to extract threshold voltage from the derived surface potential.

In chapter 5, the equations established in chapter 4 is simulated in MATLAB 2009b to obtain

surface potential and threshold voltage for nano scale asymmetric n-channel enhancement type

MOSFET varying different process parameters. The result of numerical solutions described in

chapter 3 is also investigated and the result of analytical and numerical solutions is compared.

The result is also compared with the data found in a recent work [18] where such device has been

manufacture.

Finally in chapter 6 concludes the thesis of this dissertation by depicting scopes and limitations

of this work.

Chapter 2:MOSFET Operation

Chapter 2 : MOSFET Operation

2.1 Introduction

This chapter will mainly focus on the operation of conventional long channel MOSFET. The

characterization, analysis and some derivation of important parameters of the device is given in

this chapter. The chapter will also focus on the sho

short channel devices like short channel effects and some non ideal effects will be explored. The

strategies and procedures to combat these effects can also be known.

2.2 MOSFET Operation

It is important to build a background or review conventional long channel MOSFET operation

and its analysis before moving to analyze short channel MOSFETs. The section will review a

simple long channel enhancement type n

analysis of other kinds of MOSFETs like depletion type n

p-channel MOSFET etc are similar to the analysis conducted here.

F

MOSFET Operation



this chapter. The chapter will also focus on the short channel devices. The impediments of the


strategies and procedures to combat these effects can also be known.

build a background or review conventional long channel MOSFET operation


simple long channel enhancement type n - channel MOSFET as shown in Figure

analysis of other kinds of MOSFETs like depletion type n-channel MOSFET, enhancement type

channel MOSFET etc are similar to the analysis conducted here.

9 | P a g e



rt channel devices. The impediments of the


build a background or review conventional long channel MOSFET operation


Figure 2.1. However,

channel MOSFET, enhancement type

igure 2.1 : Long channel enhancement type n: Long channel enhancement type n-channel MOSFET


As shown in Figure 2.1 a typical n

namely Source (S), Gate (G), Drain (D) and Substrate (B). Often to avert body effect which is an

impediment in normal MOSFET characterization, source and substrate are tied together so no net

voltage appears between substrate/body to source. Gate terminal is the controlling terminal of the

device. The voltage between gate and source (

conduct or not. On the other hand there is another bias condition between drain and source (

This voltage along with specified

applied VGS voltage is greater than certain voltage which

source and drain will form a channel between them and an inversion will rise on Si

interface. After inversion, the electrons can propagate from source to drain depending upon their

velocity determined by voltage V

turned on.

Operation of MOSFET is described in broad in next sub sections.

2.2.1 Energy Band Diagram

In Figure 2.2 a front cross section of typical long channel MOSFET is shown where the bulk is p

type semiconductor. It is assumed that the source and body termina

shorted. So the voltage between gate and substrate as

the figure, no voltage is applied

state has been depicted in Figure

individual material before making contact.

In Figure 2.3 (a), the Φm

electron affinity, ΦFP is Fe

bandgap energy, conductio

a typical n-channel enhancement type MOSFET contains four terminals,


ET characterization, source and substrate are tied together so no net


device. The voltage between gate and source (VGS) is deciding factor whether the device

conduct or not. On the other hand there is another bias condition between drain and source (

This voltage along with specified VGS characterizes the operation of the device. In brief, if

voltage is greater than certain voltage which is known as threshold voltage, the

source and drain will form a channel between them and an inversion will rise on Si

interface. After inversion, the electrons can propagate from source to drain depending upon their

VDS. As the electron flows, a current will rise and the device gets

Operation of MOSFET is described in broad in next sub sections.

nergy Band Diagram

a front cross section of typical long channel MOSFET is shown where the bulk is p

type semiconductor. It is assumed that the source and body terminal are tied together and

between gate and substrate as shown in Figure 2.2 is denote

the figure, no voltage is applied i.e. VGS=0. For this state of the device, the energy band diagram

Figure 2.3 (b) while Figure 2.3 (a) shows the band diagram of

e making contact.

is Fe

energy, conductio

10 | P a g e

channel enhancement type MOSFET contains four terminals,


ET characterization, source and substrate are tied together so no net


) is deciding factor whether the device will

conduct or not. On the other hand there is another bias condition between drain and source (VDS).

characterizes the operation of the device. In brief, if

is known as threshold voltage, the

source and drain will form a channel between them and an inversion will rise on Si-SiO2interface. After inversion, the electrons can propagate from source to drain depending upon their

. As the electron flows, a current will rise and the device gets

a front cross section of typical long channel MOSFET is shown where the bulk is p

l are tied together and

is denoted by VGS. In

=0. For this state of the device, the energy band diagram

(a) shows the band diagram of

energy, conductio

is the metal work function,

rmi potential on bulk p type semiconductor,

n band energy, valance band energy, Fermi level energy, intrinsic

Figure

is the metal work function, ΦS is semiconductor work function,

rmi potential on bulk p type semiconductor, EG, EC, E


Figure 2.2 : MOSFFET with no gate voltage

is semiconductor work function, χ is

EV, EF and EFi are



Fermi level energy of p type semiconductor.

is characteristics property of different semiconductor material. The ener

characteristics properties of different materials.

Table

Table 2.2 shows electron affinity for some semiconductors.

Table 2.2: Electron affinity of some semiconductors

Work function of metal and that of semiconductor are not necessarily same and while depicting

Figure 2.3 (a), it is assumed that

MOSFET device is drawn after contact has been made. As contact is given and no external

voltage is given which implies MOSFET device is in equilibrium state. To do so, the Fermi

energy level of metal and that of semiconductor must be in the same level. In other word it can

be written –

߶ݍ =

(a)

Fermi level energy of p type semiconductor. Φm is a characteristics property of different metal,

is characteristics property of different semiconductor material. The energy parameters are also

characteristics properties of different materials. Table 2.1 shows work functions for some metal.

Table 2.1: Work function of some metals

Element ΦmSilver 4.26Aluminium 4.28Gold 5.1Chromium 4.5

shows electron affinity for some semiconductors.

: Electron affinity of some semiconductors


(a), it is assumed that Φm> ΦS. In Figure 2.3 (b), the energy band diagram of the


which implies MOSFET device is in equilibrium state. To do so, the Fermi


ൌ …ௌ߶ݍ … … … … … … … … … . . (2. 1)

Element χGe 4.13Si 4.01GaAs 4.07

(b)

11 | P a g e

is a characteristics property of different metal, χ

gy parameters are also

shows work functions for some metal.


(b), the energy band diagram of the


which implies MOSFET device is in equilibrium state. To do so, the Fermi


Figure 2.33 : Energy band diagram (a) before

contact (b) after contactcontact (b) after contact

Chapter 2:MOSFET Operation 12 | P a g e

Work function of semiconductor can be written as

ௌ߶ݍ = ߯ݍ +ீܧ

2ൗ + ி߶ݍ … … … … … … … … … … . . (2. 2)

So putting the value of ΦS in equation (2.1), it can be written –

߶ݍ ௦ = ߶ݍ − ൭߯ݍ +ீܧ

2ൗ + ி൱߶ݍ = 0 … … … (2. 3)

Where Φms is the work function difference between metal and semiconductor

Fermi potential energy,ݍ�߶ிor ிே߶ݍ of both p type and n type semiconductor in a p-n junction

is defined as the difference between Fermi energy and intrinsic Fermi energy level.

Fermi potential is directly related to doping concentration. Let’s assume in a p-n junction the

doping of acceptor in p type semiconductor is NA and donor concentration on n region is ND then

߶ி =݇ܶ

ݍ݈݊ ൬

ܰ

݊൰… … … … … … … … … … . . (2. 4)

and

߶ிே =݇ܶ

ݍ݈݊ ൬

݊

ܰ൰… … … … … … … … … … . . (2. 5)

Where, k is Boltzman’s constant (k=2.23×1023J/K) and T is operating temperature (T=300 K for

room temperature) and ni is intrinsic semiconductor concentration which is approximately

1.5×1010 cm-3for silicon.

EG is the band gap energy and defined by-

ீܧ = ܧ − ܧ … … … … … … … … … … . . (2. 6)

When the materials contact are given, then ideally the energy band diagram will not be a flatter

one, rather energy band diagram will bend as shown in Figure 2.3 (b). This is due to the

difference between metal and semiconductor work function. When contact is given and VGS is not

applied to achieve equilibrium, the energy band diagram of MOSFET will bend. The difference

between work function between metal and semiconductor is not only the reason. There are other

reasons for this bending like oxide fixed charge, interface trap charge etc. This phenomenon is

well understood from the concept of flat band voltage which will be described in the next

section.


2.2.2 Flat Band voltage

The gate material of a MOSFET is not necessarily the same as that of substrate. In fact, different

materials usage is more common realistically. So short circuits between gate and body terminal,

several contact potentials are faced. However, contact potential only depends on the first and the

last materials, being independent of other intermediate materials. So contact potential between

gate and bulk can be written as-

݊ܿ ܽݐ ݁ݐ�ܿݐ −௧߶�=݈ܽ݅ݐ݊ ߶௨ … … . . (2. 7)

So though voltage is not applied, there is a potential difference exists between metal and

semiconductor. So to compensate this contact potential an opposite of this voltage has to be

applied on the gate terminal. So a potential Φms is needed such that –

߶ ௦ = ߶௨ି߶௧… … … … … … … … … . . (2. 8)

Contact potential is measured as just the opposite of the Fermi potential in a semiconductor. For

an example, if the Fermi potential of p type semiconductor is ΦFP then –

߶௨ = −߶ி … … … … … … … … … … … . . . . (2. 9)

Moreover, there may be positively fixed oxide charge in the insulator on Si-SiO2 interface. This

may occur due to various reasons like presence of contamination while fabricating the device,

radiation, photoemission etc. Besides fixed oxide charge there are other parasitic charges that

may affect charge distribution inside the insulator. The parasitic charges are-

Fixed oxide charge

Oxide trapper charge

Mobile ionic charge

Interface trap charge

Though present day, the fabrication of the device is occurred in high care and in a clean

environment, the probability of incorporation of these charges in insulator has greatly reduced

but not fully diminished.

Let’s assume the fixed oxide charge is Q0 as shown in Figure 2.4 on the Si-SiO2 interface. To

compensate the positively charged Q0, equal amount of opposite charge is needed and should be

applied on gate terminal. So to compensate the Q0, a gate voltage has to be applied which will

create – Q0 on metal surface.


Let’s assume the fixed oxide charg

unit are will be

ைܥ =

Assume, ை߳ is the permittivity o

compensate Q0 will be

ைܸ =

To compensate contact potential

voltage has to be applied in the ga

eventually balance all charges and

Figure 2.4, flat band voltage, VFB

Furthermore, one other parasitic

should not be neglected. If the i

must be applied to the gate equal t

ܸ௧ =ݍ2

Considering interface trap charge,

ிܸ = ߶

Let’s assume the fixed oxide charg

߳

ݐ

is the permittivity o

−



all charges and

FB

Furthermore, one other parasitic

should not be neglected. If the i

must be applied to the gate equal t

ܰݍ

ܥ


߶

14 | P a g e

is the permittivity o



all charges and


e density is

f the oxide. So the voltage that to be given on gate terminal to

between metal to semiconductor and fixed oxide charge, a

te terminal. This voltage is called flat band voltage which will

all energy band diagrams will be flatter rather than bended. In

charge

nterface trap density is denoted by

o

flat band voltage of the semiconductor will be

e density is ܳᇱ and oxide thickness is tOX then capacitance per

ை

ை… … … … … … … … … … … . . (2. 10)


ܳᇱ

ைܥ… … … … … … … … … … . . (2. 11)




is depicted which balances Φms and VOX.

charge- interface trap charge may become significant and

nterface trap density is denoted by Nit (unit: cm

o Vit such that –

௧߶ி

ை… … … … … … … … … … . . (2. 12)

flat band voltage of the semiconductor will be

௦ ைܸ ܸ௧… … … … … … . . (2. 13)

Figure 2.4 : Flat Band Voltage

then capacitance per





interface trap charge may become significant and

(unit: cm-2V-1), a bias

flat band voltage of the semiconductor will be –


2.2.3 Effect of VGS on surface condition

Gate terminal voltage, VGS is the controlling parameter of the MOSFET device. It has already

been seen that what situation occurs on the interface when no voltage on gate terminal is given.

In this section, the effects of applied

2.2.3.1 AccumulationLet’s assume negative voltage is given on gate terminal i.e.

such case is shown in Figure 2.5

As negative voltage is given

surface. On the other hand p

result an electric field, E will

holes on the Si-SiO2 inter

phenomenon is called accum

The energy band diagram du

clear that on the interface con

exceeds Fermi level. As a r

region.

(a)

on surface condition

is the controlling parameter of the MOSFET device. It has already


In this section, the effects of applied VGS will be investigated further.

Let’s assume negative voltage is given on gate terminal i.e. VGS < 0, the semiconductor device in

5.


surface. On the other hand p


inter

nomenon is called accum

The energy band diagram du


exceeds Fermi level. As a r

(b)

15 | P a g e

is the controlling parameter of the MOSFET device. It has already


0, the semiconductor device in



inter


FigureFigure 2.5: Accumulation (a) structure (b)

on gate terminal, negatively charged electron appears on the metal

ositive

be generated on +ve y direction. This electric field will sweep more

face. This effect will make the interface more p

ulation.

e to accumulation is shown in

duction band is raised further in upward direction and valence band

esult, the semiconductor becomes more p

energy band diagram


ositively charged holes are prevalent in semiconductor surface. As a


face. This effect will make the interface more p

ulation.

e to accumulation is shown in Figure 2.5(b). From the figure it is


esult, the semiconductor becomes more p-type than it is on bulk

energy band diagram


ly charged holes are prevalent in semiconductor surface. As a


face. This effect will make the interface more p-type and this

(b). From the figure it is


type than it is on bulk


2.2.3.2 Depletion and InversiIf positive voltage is applied on gate terminal as shown in

accumulation situation occurs.

When small voltage on the g

a parallel plate capacitor. M

act like two parallel plates

insulator. As VGS is positive

Due to the accumulation of

will be generated as shown

along the direction of app

interface will be repelled

constitutes space charge. Th

depletion width. So, this sp

almost all of the applied vol

Depletion width, YD is meas

݀ଶ

݀

ߩ is the charge density betw

depletion region which is a

semiconductor.

Fd

epletion and InversionIf positive voltage is applied on gate terminal as shown in Figure 2.6, completely opposite to

When small voltage on the g

a parallel plate capacitor. M

act like two parallel plates

is positive

f




depletion width. So, this sp

almost all of the applied vol

is meas

is the charge density betw

depletion region which is a

Fd

16 | P a g e

, completely opposite to

is positive

f




is meas

igureigure 2.6: Depletion (a) structure (b) energy band: Depletion (a) structure (b) energy band

ate terminal (

etal surface on gate side and

while the oxide, preferably silicon

, positive charge will accumulate on metal surface on gate terminal.

positive charge on metal, a vertical electric field in

in Figure

lied electric field. So, positively charged holes near the Si

and a net negatively charge will appear on the surface, which

e width up to the space charge spreads in to the substrate is called

ace charge is often denoted by depletion

tage

ured by solving a Poisson’s equation in the depletion region.

߰ௌଶݕ

=

een the depletion region of p

lmost equal to voltage applied on gate and

iagram

ate terminal (VGS) of MOSFET is applied, MOSFET acts simply like

etal surface on gate side and semiconductor oxide surface (Si

while the oxide, preferably silicon-di-oxide (SiO


positive charge on metal, a vertical electric field in

Figure 2.6. As it is known, the direction of hol

lied electric field. So, positively charged holes near the Si

and a net negatively charge will appear on the surface, which


ace charge is often denoted by depletion region charge. Normally,

tage VGS drops along this width YD, which is the depletion width.


= −ߩ

௦߳… … … … … … … … … … . . (2. 14)

een the depletion region of p-n junction, ߰ is the potential across the

lmost equal to voltage applied on gate and ϵS is the permittivity of

iagram

) of MOSFET is applied, MOSFET acts simply like

semiconductor oxide surface (Si-SiO2)

oxide (SiO2) acts like the


positive charge on metal, a vertical electric field in –ve y-direction

. As it is known, the direction of hole propagation is

lied electric field. So, positively charged holes near the Si-SiO2and a net negatively charge will appear on the surface, which


region charge. Normally,

, which is the depletion width.


is the potential across the

is the permittivity of


By solving the equation (2.14), with considering no electric field beyond depletion and proper

boundary condition, potential ߰ௌ is found. Furthermore, for the given boundary condition the

depletion width of junction can also be found. For a step profile, it is found that depletion width

YD –

ܻ = ඨ2 ௌ߳ܰݍ

ඥ߰ௌ… … … … … … … … … … . . (2. 15)

Here, it is considered that n region is heavily doped which is the normal case when a n+ poly-

silicon gate is connected with p type semiconductor. If donor and acceptor concentration in n and

p type Si respectively become comparable, then-

ܻ = ඨ2 ௌ߳ܰ

(ܰܰݍ + ܰ)ඥ߰ௌ… … … … … . . (2. 16)

Assume, ND and NA are the donor and acceptor concentrations respectively. The depletion width

on n region in this respect will be -

ܻ = ඨ2 ௌ߳ܰ

(ܰܰݍ + ܰ)ඥ߰ௌ… … … … . . (2. 17)

As with the increase of VGS, ߰ௌ increases, so ܻ will increase. With the increase of YD depletioncharge will increase as following –

ܳᇱ = ܰݍ− ܻ … … … … … … … … … … . . (2. 18)

Where ܳᇱ is depletion charge per unit area.

The effect of band diagram due to application of positive gate voltage is shown in Figure 2.7.

In Figure 2.7(a), the energy band diagram at VGS =0 is shown which is shown earlier. In Figure

2.7(b) small amount of VGS voltage is given. If the value of VGS within threshold voltage value

VTH then there will not be necessary negatively charged electron in the Si-SiO2 surface to invert

the surface and form the channel.

The concentration of negatively charged electron on surface, nsurface can be related with the

concentration of that in bulk region n0. n0 and p0 are thermal equilibrium electron and hole

concentration. Thermal equilibrium is achieved when no external force like voltage, temperature

is given. As in the bulk, there is no electric field the electron and hole concentration in bulk

region is same as n0 and p0 respectively.


The relation between nsurface and n

௦݊௨ =

Let’s d

And let

Then it

(a)

n0 is-

݊݁టೄ

்ൗ … … … … … … … … … … . . (2. 19)

And let

(b)

(c)

18 | P a g e

efine thermal voltage as-

்ܸ =݇ܶ

ݍ

’s assume the Fermi potential of the semiconductor is

߶ி ൌ ்ܸ

݊ ൌ ݊݁

is found –

௦݊௨

Figure 2.7: Energy band diagram of MOSFET (a) V

݇ܶ

ݍ… … … … … … … … … … … … … . . (2. 20)

’s assume the Fermi potential of the semiconductor is ΦF, then it can be written

்൬݊

݊൰ǥ ǥ ǥ ǥ ǥ ǥ ǥ ǥ ǥ ǤǤǤሺʹ Ǥʹ ͳሻ

݁ିథಷ … … … … … … … … … … … . . . . (2. 22)

ൌ ݊݁(టೄିథಷ)

ൗ

… … … … … … . . (2. 23)

: Energy band diagram of MOSFET (a) VGS=0, (b) 0


Now,

߶ி ൌ ்ܸ ݈݃

Now it is found-

݊ൌ ݁

Then-

௦݊௨

For full ionization it can be consider

௦݊௨

From this equation it is seen that when

all of the charges on the interface are negatively charged electrons, this is known as inversion. As

soon as inversion is achieved, the depletion width is gained its maximum value. With the

increase of VGS, negatively charged elec

charge. As YD reaches its maximum value, depletion charge per unit area,

maximum value.

ܻሺ ௫)

ܳሺ ௫ᇱ

݈݃ ൬

݊൰ǥ ǥ ǥ ǥ ǥ ǥ ǥ ǥ ǥ ǥ ǤǤሺʹ Ǥʹ Ͷሻ

݁ିథಷ … … … … … … … … … … . . … . . (2. 25)

௦௨ ൌ ݁ሺటೄିଶథಷ)

ൗ

… … … … … . . (2. 26)

considered that ൎ ܰ then,

௦௨ ൌ ܰ݁ሺటೄିଶథಷ)

ൗ

… … … … . . . (2. 27)

From this equation it is seen that when ߰ௌ ൌ ߶ʹி then, ௦݊௨ ൌ ܰ. When this happens, then



, negatively charged electron will be generated which is known as inversion

reaches its maximum value, depletion charge per unit area, ܳ

) = ඨʹ ௌ߳ܰݍ

ඥʹ߶ி … … … … … . . . . (2. 28)

௫) ൌ െܰݍ ܻ( ௫) … … … … … . . (2.29)

19 | P a g e

. When this happens, then



tron will be generated which is known as inversion

ܳᇱ also reaches a

Figure 2.8 : Charge distribution in MOSFET with V: Charge distribution in MOSFET with VGS>VTH


2.2.4 Potential balance and charge balance

When an external voltage VGS is applied, it will mostly drop within the depletion region.

Depletion region extends from surface to the depletion width. The potential from the surface to

the bulk is called surface potential and eventually the voltage dropped across the depletion width

is surface potential and denoted as ߰ௌ. There will be also a voltage drop across oxide and metal

to semiconductor work function will remain which are denoted as VOX and Φms respectively. So,

VGS voltage will give rise three components voltage.

ܸீ ௌ = ைܸ + ߰ௌ + ߶ ௦… … … … … … … … … … . . (2.30)

This is known as potential balance. As metal to semiconductor work function is a characteristics

properties so with the change of VGS, Φms will not change. So,

Δܸீ ௌ = Δ ைܸ + Δ߰ௌ… … … … … … … … … … . . . . (2.31)

Due to the application of VGS, there will be a positive charge on the gate electrode. Let the

induced charge on gate electrode per unit area be ܳீᇱ. This charge contributes to the charge under

the oxide into the semiconductor. Let the charge in Si per unit area be ܳᇱ and fixed oxide charge

density is ܳᇱ then

ܳீᇱ + ܳ

ᇱ+ ܳᇱ = 0 … … … … … … … … … . . … . . (2.32)

This is known as charge balance and as ܳᇱ is fixed any change in charge due to change in VGS

means-

Δܳீᇱ+ Δܳ

ᇱ = 0 … … … … … … … … … … … . . . . (2.33)

The charge in semiconductor is divided into two parts. One is depletion charge density ܳᇱ and

other is inversion charge density ܳூᇱ

ܳᇱ = ܳ

ᇱ + ܳூᇱ… … … … … … … … … … … . … . . (2.34)

2.2.5 Threshold Voltage

Threshold voltage is the minimum voltage required on the gate electrode, to invert the channel

on the interface and form the channel. As it is seen earlier that when the surface potential,

߰ௌbecomes equal to 2ΦF, then inversion is achieved. This relation can be used to determine the

threshold voltage of the device.

Just prior to the inversion, the charge is mainly due to depletion charge and so inversion charge

is neglected. So, the charge density in the semiconductor will be –


ܳᇱ = ܳ

ᇱ … … … … … … … … … … . . (2.35)

ܳᇱ = ܰݍ− ܻ ௫ … … … … … … . . (2.36)

The charge balance is –

ܳீᇱ + ܳ

ᇱ+ ܳᇱ = 0 … … … … … . … . . (2.37)

ܳீᇱ = −ܳ

ᇱ− ܳᇱ… … … … … … … . . . (2.38)

The charge on gate electrode is ܳீᇱ and capacitance per unit area is COX, then voltage across oxide

ைܸ =ܳீᇱ

ைܥ… … … … … … … … … . … … . . (2.39)

ைܸ =−ܳ

ᇱ− ܳᇱ

ைܥ… … … … … … . … … . . (2.40)

The potential balance is -

ܸீ ௌ = ைܸ + ߰ௌ + ߶ ௦… … … … . … . . (2.41)

For ߰ௌ = 2߶ி, ܸீ ௌ = ்ܸ ு then it can be written-

்ܸ ு = ைܸ + 2߶ி + ߶ ௦… … … … . . (2.42)

Putting the value of VOX

்ܸ ு =−ܳ

ᇱ− ܳᇱ

ைܥ+ 2߶ி + ߶ ௦… … . . (2.43)

்ܸ ு =−ܳ

ᇱ

ைܥ+ 2߶ி + ߶ ௦−

ܳᇱ

ைܥ… . . . (2.44)

Neglecting interface trap charge flat band voltage is –

ிܸ = ߶ ௦−ܳᇱ

ைܥ… … … … … … … … . . (2.45)

The threshold voltage becomes –

்ܸ ு = −ܳ( ௫)ᇱ

ைܥ+ 2߶ி + ிܸ … … . . (2.46)


This is the threshold voltage equation for a long channel MOSFET device.

2.2.6 Current Voltage characteristics

Assuming the source and body terminal are held at ground potential. An n-channel enhancement

type MOSFET will start to operate when VGS > VTH. Due to application of such voltage, an

inversion layer will be created. If a small drain to source voltage VDS is applied then there will be

a net flow of electron from source to drain and as a result current will flow from drain to source.

For small VDS, the channel exhibits resistive nature and it can be written,

ܫ = ௗ݃ ܸௌ… … … … … … … … … … . . (2.47)

ௗ݃is the channel conductance and defined as-

ௗ݃ =ܹ

ܮ(−ܳூߤ

ᇱ) … … … … … … … . . (2.48)

Assume, W and L are the width and length of the MOSFET respectively. isߤ the mobility of

electron in the channel. ߤ depends on velocity of electron and thus electric field applied in the

channel. In the calculation of long channel drain current voltage characteristics, mobility is

assumed constant. However, mobility is not a constant parameter if high electric field appears in

the channel which is a common factor in a short channel device. With high electric field the

velocity of carrier will saturate and mobility will no longer a constant value. On the other hand,

the channel length L is assumed constant in the calculation of ID - VDS characteristics. But, L is

also not a constant parameter and shrinks with the application of high VDS.


(a)

(c)

(e)

(g)

(b)

(d)

(f)

(h)

23 | P a g e

Figure 2.9 : MOSFET operation (a) small V: MOSFET operation (a) small VDS, (b) ID-VDS for a, (c) VDS increased, (d) Iincreased, (d) ID-VDS for c, (e)

VDS=VDSsat, (f)ID-VDS for e, (g) VDSDS>VDSsat, (h) ID-VDS for g


gd depends on the inversion charge density on the channel which in turn depends on the

application of VGS. So with higher VGS higher gd means higher slope in ID - VDS curve. Figure 2.9

(a) shows the status of the device when the VGS>VTH and VDS is small. The channel is formed and

current is conducting in a resistive manner. Figure 2.9 (b) shows the ID - VDS characteristics of

this state.

In Figure 2.9 (c), the value of VDS is further increased. This voltage is distributed in the channel

and any point x in the channel gains voltage with the increase of VDS. As a result at that point the

voltage across oxide reduces. Though with the increase of VDS, electric field will be increased

and that’s why velocity of the carrier will increase. With the increased velocity, the mobility will

be enhanced and current will be increased. Figure 2.9 (d) shows ID - VDS characteristics of this

state.

In Figure 2.9 (e), the voltage VDS is increased further and at an extent that at drain end the value

of VDS is such that –

ܸீ ௌ− ܸௌ = ்ܸ ு … … … … … … … … … … . . (2.49)

At this point the voltage across the oxide reaches threshold and channel is pinched off. This

phenomenon is known as saturation and the value of VDS is called saturated drain voltage and

denoted by VDS.sat

ܸௌ(௦௧) = ܸீ ௌ− ்ܸ ு … … … … … … … … . . (2.50)

ID - VDS characteristics of this state is shown in Figure 2.9 (f).

If VDS is increased beyond VDS.sat as shown in Figure 2.9 (g), the voltage on drain end will be –

ܸௌ = ܸௌ(௦௧) + Δ ܸௌ… … … … … … … . . (2.51)

Then near the drain end, any point x will eventually gain voltage VDS.sat there and that will make

voltage across the oxide equal to threshold at that point x. So the channel length will be reduced.

Starting from the point x to the drain there will be no inversion charge and that will make

conductance zero, so drain current will be constant in saturation value. In this state, the electron

flows mainly with the help of an electric field in the space region between x and drain as shown

in Figure 2.9 (g). Figure 2.9 (h) shows the ID - VDS characteristics for this state of the device.

Qualitatively, it is seen the MOSFET device operates in two regions, first in active or resistive

region and other is in saturation region. The equation for drain current can be deduced using

simple derivation, here the derived drain current for long channel MOSFET is given.


Drain current equation in resistive region-

ܫ =ܹ ைܥߤ

ܮ2[2(ܸீ ௌ− ்ܸ ு) ܸௌ− ܸௌ

ଶ ] … … . . … … . . (2.52)

Drain current equation in saturation region-

ܫ =ܹ ைܥߤ

ܮ2(ܸீ ௌ− ்ܸ ு)

ଶ… … … … … … … … … … . . (2.53)

2.3 Short Channel MOSFET

The MOSFET device with channel length in nano meter size is often referred as short channel

MOSFETs. Channel length of such device may be few hundred nanometer or even can be scaled

down to 50 nm or less. Use of 32 nm channel length semiconductor is already considered in

different commercial plan of renowned industries. Furthermore, extensive research in academic

level is going on to shrink channel length below 20 nm. However, the choice of nano meter size

is not always as lucrative as it appears. In such miniaturized dimension, carrier shows both

particle and wave nature and quantum method becomes prevalent. Besides, there are many other

effects that hinder the development of nano meter size MOSFETs. But yet nano meter size

MOSFET is the pledge of next generation technology.

In short channel MOSFET there are some non ideal effects which becomes significant. Other

than this, there are some short channel effects [23, 24] which reduce the control on the device

and eventually reaches breakdown. In the next sections, these impediments of short channel

MOSFEs will be discussed.

Non ideal and short channel effect-

1. Channel Length Modulation

2. Threshold Voltage Roll off

3. Punch through

4. Drain Induced Barrier Lowering (DIBL)

5. Avalanche Breakdown

6. Impact Ionization and Hot Carrier Injection


2.3.1 Channel Length Modulation

As seen in section, the pinch off in the channel occurs when

Further increase of VDS will distribute voltage to the point on the channel and at any stage point

will gain voltage such that voltage across the oxide at that po

off point will be shifted towards the source with the increase of

As shown in Figure 2.1

the source. The channel

charge. The region is on

in channel length, Poisso

E is the electric field in t

charge density and ϵS i

proper boundary conditio

found that if ID is the dra

with channel length mod

hannel Length Modulation

As seen in section, the pinch off in the channel occurs when VDS becomes equal to

will distribute voltage to the point on the channel and at any stage point

will gain voltage such that voltage across the oxide at that point will be equal to

off point will be shifted towards the source with the increase of VDS.

the source. The channel


in channel length, Poisso

is the electric field in t

i

proper boundary conditio

is the dra

with channel length mod

26 | P a g e

becomes equal to VGS- VTH.

will distribute voltage to the point on the channel and at any stage point x

int will be equal to VTH . Thus pinch


i

0, channel length is reduced due to the shift of pinch off point towards

length is reduced by

ly on depletion and depletion charge prevails. To calculate the reduction

n’s equation can be solved in that depleted region of

ܧ݀

ݔ݀=

he depletion region of

s the permittivity of Si. By solving the Poisson’s equation and with

n electric field

in current without channel length modulation and

ulation then

ܫᇱ =

Figure 2

, channel length is reduced due to the shift of pinch off point towards

length is reduced by ΔL and within this length there is no inversion


n’s equation can be solved in that depleted region of ΔL

=ߩ

ௌ߳… … … … … … … … … … . . (2.54)

he depletion region of ΔL which sweeps the electron to the drain.


n electric field E can be evaluated from which the ΔL can be found

in current without channel length modulation and ܫᇱ is the drain current

ulation then –

=ܮ

െܮ ȟܮܫ … … … … … … … . . (2.55)

2.10: Channel length modulation

, channel length is reduced due to the shift of pinch off point towards

and within this length there is no inversion


L.

which sweeps the electron to the drain.ߩ� is the


can be found. It is

is the drain current


Where

ȟܮൌ ඨʹ߳ ௌܰݍ

ቈට߶௦௧+ ൫ܸ ௌ−

߶௦௧ =ʹ ௌ߳ܰݍ

൬௦௧ܧ

2൰ଶ

ǡ݄݁ݓ ݁ݎ

So it is seen that with the increase of

Furthermore, with the smaller dimension of MOSFET,

length L and channel length modulation becomes more severe.

2.3.2 Threshold Voltage Roll Off

In long channel length MOSFET, the depletion width due to source and drain is not significant if

compared with depletion width of the bulk. So, in the analysis of long channel MOSFET, the

depletion width due to source and drain is deliberately neglected. B

MOSFET device is reduced to nano meter size, the depletion width due to source and drain

becomes significant. In Figure 2

channel shown in Figure 2.11 (b)

The dep

width in

(a)

൫ − ܸௌ(௦௧)൯− ඥ߶௦௧ǡ݄݁ݓ ݁ݎ ǥ ǥ ǥ ǥ ǥ ǥ ǤǤሺ2

݄ݐ�ݏ௦௧�݅ܧ �݈݁݁݁ ݅ݎܿݐ �݂ܿ ݅݁ ݈݀ ݉ݎ݂� ݊݅� ݄ܿ ݂� ݅� ݐ݊

So it is seen that with the increase of VDS, ΔL is increased. With increased ΔL,

Furthermore, with the smaller dimension of MOSFET, ΔL becomes a significant part of channel

and channel length modulation becomes more severe.

hreshold Voltage Roll Off



depletion width due to source and drain is deliberately neglected. But when the dimension of


2.11 (a), a long channel has be shown and compared with a short

(b)

The dep

width in

(b)

27 | P a g e

2.56)

݅ ܿݎݑݏ�ݐ�ݐ݊ ݁

, ID’ will increase.

becomes a significant part of channel



ut when the dimension of


a), a long channel has be shown and compared with a short

The dep

(b)

letion width due to source and drain becomes a significant part of the total depletion

the short channel device as shown in

Figure 2.11: Depletion regions (a) long channel MOSFET, (b) short channel MOSFET


the short channel device as shown in Figure 2.11 (b).

: Depletion regions (a) long channel MOSFET, (b) short channel MOSFET


: Depletion regions (a) long channel MOSFET, (b) short channel MOSFET


So, depletion charge arises due to source and drain can no longer be neglected. So depletion

charge due to the application of VGS is reduced and

This reduction of threshold voltage is known as Threshold voltage roll off effect.

2.3.3 Punch Through

In short channel MOSFET, as the dimension is very low, electric field due to application of

voltage becomes high as –

ܧ =

Though with the scaling of dimension,

that level is not always possible. So, if

field along drain to source direction will increase too. With increased electric filed the depletion

region from the drain intends to grow. As it grows at one point it merges with the depletion

region of source. At this point there is no depletion region due to application of

controlling with VGS is totally lost and there will be no barrier between source and drain. As

electron can flow freely from source to drain, there will be huge current

phenomenon is known as punch through effect.

2.3.4 Drain Induced Barrier Lowering

This effect is very close to punch through effect. In fact this is also called near punch through

effect.

(a)

So, depletion charge arises due to source and drain can no longer be neglected. So depletion

charge due to the application of VGS is reduced and as a result threshold voltage is also reduced.

This reduction of threshold voltage is known as Threshold voltage roll off effect.

In short channel MOSFET, as the dimension is very low, electric field due to application of

=ܸ

݀… … … … … … … … … … . . (2.57)

Though with the scaling of dimension, d voltage V is scaled accordingly but voltage scaling in

possible. So, if VDS in a short channel device is increased, lateral electric

field along drain to source direction will increase too. With increased electric filed the depletion

region from the drain intends to grow. As it grows at one point it merges with the depletion

on of source. At this point there is no depletion r

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