Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

Structure:

semiconductor

metal oxide p+ n n S G D

MOSFET operation

If VG=0 Assuming VD=high, VS=0

G

S

D

p+ n nNo current

MOSFET operation

If VG=high Now if VD=high, there is a current flow between D and S

G S

D

++ ++

MOSFET structures and circuit symbols

p-type substr ate Si O2 n + Depletion r egion

Gate Sour ce

Dr ai n

+

Drain Drain Drain

n

Gate Bul k Sour ce Sour ce Sour ce

Channel

Substr ate

(b) (c) (d)(a) (a) Schematic structure of n-channel MOSFET (NMOS) and circuit symbols for (b) MOSFET, (c) n-channel MOSFET, and (d) n-channel MOSFET when the bulk (substrate) potential has to be specified in a circuit.

Complementary MOSFET pairs

Gate n-channel p-channel

Dr ain

Sour ce

+ Drain Drain +

p

n

Si O2 n-type wel l Si O2 Gate

Bul k

p-type substrate

Sour ce Sour ce

Subst r ate

Schematic structure of Complementary MOSFET (CMOS) and circuit symbols for p-channel MOSFET (PMOS). Minuses and pluses show the depletion regions.

Sub-threshold mode of MOSFET operation

�VG = 0; the MOSFET conducting channelVG = 0

is not formed

higher VG

Channel

EcSource DrainEnergyFB EF

Distance

In the subthreshold regime, the MOSFET current is a small reverse current through the source � substrate and drain � substrate p-n junctions;

Only a small number of electrons can pass over the potential barrier separating the drain and the source.

( B / kT

-F )

n �n ×e

ST Source

Sub-threshold mode of MOSFET operation

10 2 0

10

VG2 -2

VG1

10 -4

10 -6

VG3

10

Source

Drain

-8

10

VG1<VG2<VG3

-10

10

Gate-source voltage (V) 1.81.41.00.60.2-0.2 0.05 V V ds = 3.0 V I t In the sub-threshold regime, the channel current is very low and increases exponentially with the gate bias.

( B / kT

-F )

n �n ×e

ST Source

0.05 V V ds = 3.0 V I t 0.05 V V ds = 3.0 V I t MOSFET threshold voltage

VG1<VG2<VG3 10 2

0

VG1

10

Source VG2 VG3 -2

10

-4

10

-6

10

Drain

-8

10

-10

VT

10 -0.2 0.2 0.6 1.0 1.4 1.8 Gate-source voltage (V)

At certain gate bias called the threshold voltage, the conductivity type under the gate inverts and the barrier between the Source and the Drain disappears.

Electrons can enter the region under the gate to form a

conducting n-channel.

At the gate voltages above the threshold, the gate and the channel form a Metal-Insulator-Semiconductor (MIS) capacitor. 8

MOSFET above the threshold voltage

The free electron charge in the MOSFET channel (per unit area):

Q1 = CGATE × (VG �VT) (assuming that at VG = VT the free electron concentration is zero)

In MOSFETs, the gate and channel form a MIS-capacitor, hence the capacitance per unit gate area

c =e / d =ee / d

i ii ir 0 i

ei = eir e0 is the total dielectric permittivity of the gate dielectric (usually, SiO2), eir is the relative dielectric permittivity of the gate dielectric.

Total gate capacitance CG = ci ×A, where A is the gate area

The sheet electron concentration above the threshold, nS is given by:

qns = ci ( VGS - VT )= ciVGT

MOSFET above the threshold voltage

1.81.41.00.60.2 0.05 V V ds = 3.0 V I t 10 2 0

10

-2

10 -4

10 -6

10 -8

10 -1010

-0.2 Gate-source voltage (V)

qns = ci (VGS - VT )= ciVGT

Above the threshold, the sheet electron concentration and hence the channel current increase linearly with the gate bias VG.

MOSFET Threshold Voltage

semiconductor

metal oxide p+ n n S G D DrainSource

Band Diagram at the MOS interfaces

Before Contact

Vacuum level

oxide

metal p+ n n q .ox

EC

qfm

qqq ..s ss

Ei

qfs

EC

EFm

E

g

EFs

EV

EV

METAL OXIDE SEMICONDUCTOR

Metal and semiconductor Fermi levels align by

After Contact

electron transfer. Bending is the result of the presence of transferred electron

p+ n n EC EC EC

EEEV VV

EC

Ei

EEEFm FmFm

EFs

Ei

EV

EFs

EV

METAL OXIDE SEMICONDUCTOR

p + n n p + n n Flat band Voltage

VG

Gate voltage making the band flat

EC

VFB= fm-fs

EC

EFm

Ei

VG

EFs

EV

EV

EC EC

EFm

Ei VG

EFs

EV

VG

EFm

EV

VG=VFB

EC

EC

Ei

EFs

EV

EV

VG>0 VG<VFB

Conductivity conversion in MOSFET

p + n n Less holes at the

VG

VG

interface, more bending

p + n n Less p type p type

EC

EC

Ei

Ei

EFs

EFs

EV

EV

VG . VG=0 More depletion

p + n n p + n n p + n n VG

VG

Less p type p type Less p type p type

EC

EC

Onset of Channel

Channel

Ei

Ei

creation

created

EFs

EFs

EV

EV

VG ..

VG ...

n type Inversion n type Strong Inversion

Inversion condition in MOSFET

EC EV EFs Ei qfb Equilibrium hole concentration in the bulk of semiconductor qVs qfb kT

pne

=

i

qfb is the Fermi level offset from the mid-gap in the bulk material

Surface potential Vs is controlled by the gate voltage

Accumulation Depletion Onset of inversion Inversion

V<0 V<fb V=fb V>fb

sss s

Strong Inversion When Vs = 2fb, n-concentration at the surface is the same as p-concentration in the bulk

Vs>2fb

Surface potential required to reach the MOSFET threshold

qfbqfb

kTipne=EC EV EFs Ei VsT=2fb fbfbkTinne=When Vs = 2fb, n-concentration at the surface is the same as p-concentration in the bulk

Surface potential and gate voltage

� VG is the gate voltage, as source is grounded, Vi

VG=VGS

� Vi is the voltage drop across the oxide/insulator � Vs is the surface potential VG

EFm

V =V +V +V

GS FBsi

EC Vs EC

Ei

EFs

EV

EV

Voltage drop across the oxide layer

V =V +V +V

GS FB si

Vi

Vi is the voltage drop across the oxide/insulator

Gate electrode and semiconductor form the VG plates of the MOS capacitor.

EFm

Voltage drop across the capacitor:

Q

d

V =

i

C

i

EC

Ei

EFs

EV

EV

EC where Qd is the capacitor charge and Ci is the capacitance.

Since the charges on the metal and semiconductor plates are the same, Qd can be calculated as the charge in semiconductor. The semiconductor charge is formed by the charge of the depletion region

Voltage drop across the oxide layer

Vi

The relation between the depletion region width W and the applied voltage Vs:

qN W 2

a

Vs = VG2es

2eVs EFm Form this, W =

qN

a

The depletion region charge (per unit area):

EC

Ei

EFs

EV

EV

2eVs

Q = qN W = qN

. Q = 2e qN da

aqN dsas

a

Voltage drop across the oxide layer

Q Vi

d

V =

i

c

i

where,Q = 2e qN V

d sas

VG

is the depletion region charge per unit area, EFm ci is the MOS-capacitor capacitance per unit area:

e

i

c =

i

d

i

di is the thickness of the oxide film under the gate

EC

Ei

EFs

EV

EV

MOSFET threshold voltage (cont.)

The MOSFET threshold voltage is defined as the Gate voltage leading to the strong inversion, i.e. Vs = 2fb

TV=V +

At the onset of strong inversion: 2esqNa

GS FBs

()()22 bbff+2e qN V

s as

V =V +V +

c

i

FB

c

i

Finally, the threshold voltage,

V =V + 2. +. 2.

TFB b b

N

where the body effect constant, .=

N

2 saiqNc/e

Effect of Body Bias

VG

p+ n n VS VD VBS .0 the Threshold voltage,

V = V + 2. +.

T FB bN

( )BSb V2 -.

Effect of Surface States

p+ n n VS VD VBS .0 bonds are created that contributes to wanted trapped charges at the interface + + + + + + + + + + VG During the oxide growth on Si, dangling

the Threshold voltage,

VT = VFB + iCssQ+ 2.b +.N (2.b - VBS )

Qss : surface state charges per unit area